CN110071136A - Three-dimensional longitudinal direction electrical programming memory - Google Patents
Three-dimensional longitudinal direction electrical programming memory Download PDFInfo
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- CN110071136A CN110071136A CN201810056756.6A CN201810056756A CN110071136A CN 110071136 A CN110071136 A CN 110071136A CN 201810056756 A CN201810056756 A CN 201810056756A CN 110071136 A CN110071136 A CN 110071136A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
- H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
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Abstract
The present invention proposes a kind of three-dimensional longitudinal electrical programming memory (3D-EPMV).It contains the horizontal address wire of multiple-level stack, multiple storage wells for penetrating horizontally location line, the thin storage film (including programming film and diode film) of one layer of covering storage well abutment wall, thickness less than 100nm, a plurality of vertical address wire being formed in storage well.Since thin storage film has larger reverse leakage current, in order to avoid read error or high energy consumption, maximum reverse bias voltage suffered by storage member is much smaller than read voltage in storage array.
Description
Technical field
The present invention relates to integrated circuit memory fields, more precisely, being related to electrical programming memory (EPM).
Background technique
Three-dimensional electric programming memory (3D-EPM) is a kind of monomer (monolithic) semiconductor memory, it contains multiple
The storage member of vertical stacking.Storage member is distributed in three dimensions, and the storage member of traditional plane EPM is distributed in two dimension and puts down
On face.Relative to traditional EPM, the advantages such as 3D-EPM has storage density big, and carrying cost is low.
U.S. Patent application US 2017/0148851A1 (applicant: Hsu；The applying date: on November 23rd, 2016) propose one
The three-dimensional longitudinal electrical programming memory (3D-EPM of kindV), it contains the horizontal address wire of multiple-level stack, multiple to penetrate horizontally location line
Storage well, cover storage well abutment wall storage film and a plurality of vertical address wire being formed in storage well.Storage member is located at
The infall of horizontal address wire and vertical address wire.Material between horizontal address wire and vertical address wire is referred to as storage film,
It includes programming film (Hsu is referred to as memory layer) and diode film (Hsu is referred to as selective membrane selector layer).
In different conventional arts, diode film is also also referred to as selected to device steering element, quasi- conductive membrane etc..
In the prior art, in order to avoid reading interference and high power consumption, storage film contains individual, high quality diode
Film.The thickness of the diode film of high quality is generally large.By taking P-N thin film diode as an example, there is good positive counter current to select ratio
The thickness of the P-N thin film diode of (rectifying ratio) is in 100nm or more.In 3D-EPMVIn, the radius of storage well is
The sum of the radius of vertical address wire, the thickness for programming film and thickness of diode film.So thick diode film is such as formed in
In storage well, along with the thickness of programming film, it will lead to that storage well size is larger, and storage density is lower.
Fig. 7 represents traditional reading mode.Choose storage member 1ac` (with selected word line 8a` in storage array 10` to read
With choose bit line 4c` to couple) information of storage, the voltage of selected word line 8a` is raised to and maintains read voltage VR, unselected word line
The voltage of 8b`-8d` maintains 0；In addition, choosing the voltage of bit line 4c` to be down to 0, unselected neutrality line 4a` in advance, on 4b`, 4d`
Voltage maintain VR.In read phase, selected word line 8a` is by storage member 1ac` to choosing bit line 4c` charging.At this moment, every
Leakage current in unselected word line (such as 8b`) is (n-1) * I (- VR).Wherein, n is all positions coupled with unselected word line 8b`
The number of line, I (- VR) it is to store first (such as 1bd`) in reverse bias voltage-VRLeakage current when lower.Due in traditional reading mode
Under, it (is-V that it is larger, which to store reverse bias voltage suffered by first (such as 1bd`), for each reverse bias in storage array 10`R), because
The leakage current of this storage array 10` is larger, is also easier to occur to read interference.
Summary of the invention
The main object of the present invention is to improve the storage density of three-dimensional repeatedly programmable memory (3D-EPM).
It is another object of the present invention to keep the fill process of storage well simpler.
It is another object of the present invention to make the smaller of storage well.
It is another object of the present invention to guarantee the normal work of 3D-EPM in the case where diode quality is poor.
In order to realize that these and other purpose, the present invention propose a kind of improved three-dimensional longitudinal electrical programming memory (3D-
EPMV).It contains the horizontal address wire of multiple-level stack.After etching multiple storage wells for penetrating these horizontal address wires,
The abutment wall of storage well covers one layer of thin storage film, and fills conductor material to form vertical address wire.
In order to avoid storage well is oversized, the thickness of storage film should be less than 100nm.In other words, film and two poles are programmed
The overall thickness of periosteum is less than 100nm.In one embodiment of the invention, storage member contains only individually programming film, and is free of
Individual diode film, diode are the self-assembling formations between horizontal address wire, programming film and vertical address wire.Due to not
Individual diode film need to be formed on the abutment wall of storage well, the filling of storage well becomes easy, this is by simplification of flowsheet.This
Outside, this design can also reduce the size of storage well, increase storage density.
Since storage film is relatively thin, the quality of diode film contained by storage member is generally poor: positive counter current is reversed to leak than bad
Electric current is larger.Weak reverse bias is also proposed in order to avoid generating reading interference or high energy consumption, the present invention in read procedure: reading rank
Section, the maximum reverse bias voltage of all reverse bias storage members is much smaller than read voltage V in a storage arrayR.It is weak reversed inclined
It sets through a kind of full-time course mode and realizes.Under full-time course mode, the information of all storages member coupled with a wordline is at one
It is read in read cycle.Particularly, the read cycle of full-time course mode is in two stages: pre-charging stage and read phase.It is being pre-charged
In the stage, all address wires (including all wordline and all bit lines) are precharged to a predeterminated voltage in storage array.It is reading
Stage, when the voltage in selected word line rises to read voltage VRAfterwards, it is charged by storage member coupled thereto to all bit lines.
Every bit line is coupled with a sense amplifier.When the voltage change on bit line is more than the threshold voltage V of sense amplifiertWhen, it reads
Amplifier is overturn out, and the information stored in storage member is read.Notice VtValue very little (generally~0.1V), be much smaller than
VR(generally a few volts).In read phase, reverse bias stores maximum reverse bias voltage suffered by member and does not exceed VtVery much,
Value is much smaller than VR.Therefore, read error caused by reverse bias or energy consumption are far below traditional reading mode (conventional art).
Correspondingly, the present invention proposes a kind of three-dimensional longitudinal electrical programming memory (3D-EPMV), it is characterised in that contain: one
Semiconductor substrate (0) containing a substrate circuitry (0K)；Multilayer is on the substrate circuitry (0K) and the level of vertical stacking
Address wire (8a-8h)；Multiple storage wells (2a-2d) for penetrating the multiple-layer horizontal address wire (8a-8h) and being parallel to each other；One layer
The storage film (6a) of storage well (2a-2d) abutment wall is covered, the thickness of the storage film (6a) is less than 100nm；It is a plurality of to be located at this
Vertical address wire (4a-4d) in storage well (2a-2d)；It is multiple be located at the horizontal address wire (8a-8h) and it is described vertically
The storage of location line (2a-2d) infall is first (1ha-1aa)；It is described to store maximum reverse bias voltage suffered by member in read phase
Much smaller than read voltage.
Detailed description of the invention
Figure 1A is the first 3D-EPMVZ-x sectional view；Figure 1B is its x-y sectional view along AA '.
Fig. 2A is second of 3D-EPMVZ-x sectional view；Fig. 2 B is its x-y sectional view along BB '；Fig. 2 C is the first
Store the z-x sectional view of member；Fig. 2 D is the z-x sectional view of second of storage member.
Fig. 3 A- Fig. 3 C is the 3D-EPMVThe sectional view of three processing steps.
Fig. 4 A indicates the symbol and its meaning of storage member；Fig. 4 B is the circuit for the reading circuit that the first storage array uses
Figure；Fig. 4 C is its timing diagram；Fig. 4 D is a kind of I-V curve of diode film.
Fig. 5 A is the third 3D-EPMVZ-x sectional view；Fig. 5 B is its x-y sectional view along CC '；Fig. 5 C is second
The circuit diagram for the reading circuit that storage array uses.
Fig. 6 is a kind of multidigit member (multiple-bit-per-cell) 3D-EPMVX-y sectional view.
Fig. 7 is the offset mode (conventional art) that storage array is used in read phase.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure."/" indicates the relationship of "and" or "or"." in substrate " refers to that function element is respectively formed (including substrate table in the substrate
On face), and interconnection line be formed in above substrate, not with substrate contact." on substrate " refer to function element be formed in above substrate,
Not with substrate contact.
Specific embodiment
Figure 1A is a kind of three-dimensional longitudinal electrical programming memory (3D-EPMV) z-x sectional view.It contains the water of multiple-level stack
Flat address wire 8a-8h.After etching multiple storage well 2a-2d for penetrating these horizontal address wire 8a-8h, in storage well 2a-
The abutment wall of 2d covers storage film 6a-6d one layer thin.Storage film 6a-6d typically contains programming film and diode film, thickness (T)
Less than 100nm.Later, conductor material is filled in storage well 2a-2d to form vertical address wire 4a-4d.Store member 1aa-
1ha is formed in the infall of wordline 8a-8h Yu bit line 4a, they constitute storage string 1A.Storage member in this figure constitutes a storage
Array 10, storage array 10 are the set of all shared storage members for having at least one address wire.
In storage member 1aa, storage film 6a contains a programming film 16a and diode film 18a.Programming film 16a contains a volume
Journey material, resistance are changed into low resistance in programming Shi Kecong high resistance or are transformed into high resistance from low resistance.As an example
Son, programming film 16a contain phase transformation (phase-change material, referred to as PCM) material, resistive (resistive RAM,
Referred to as RRAM) the programming material such as material or memristor material.Diode film 18a has following broad aspects: when additional
The value of voltage be less than read voltage or applied voltage direction it is opposite with read voltage when, the resistance of diode film 18a be much larger than its
Resistance under read voltage.
Figure 1B is the 3D-EPMVAlong the x-y sectional view of AA '.Horizontal address wire 8a be a conductor plate, it can with two rows or
Vertical address wires more than two rows (is herein eight vertical address wire 4a-4h) coupling, to form eight storage member 1aa-1ah.
These storage member (all storages members being electrically coupled with a horizontal address wire 8a) 1aa-1ah constitutes a storage group 1a.Due to water
Flat address wire 8a is very wide, it can be formed using low accurate lithographic technology (such as characteristic line breadth > 60nm photoetching technique).
Fig. 2A is second of 3D-EPMV10 z-x sectional view；Fig. 2 B is its x-y sectional view along BB '.With Figure 1A-figure
1B is different, and storage film contains only one and individually programs film 16a-16d, and does not contain an individual diode film.
As shown in Figure 2 C, storage member 1aa contains only individually programming film 16a, and does not contain individual diode film.Two poles
Pipe is the self-assembling formation between horizontal address wire 8a, programming film 16a and vertical address wire 4a.Due to only need to be in storage well 2a
Abutment wall on form programming film 16a, without forming diode film, the filling of storage well 2a become easy, this will simplify work
Skill process.In addition, this design can also reduce the size of storage well 2a, increase storage density.
In the first embodiment of Fig. 2 C, horizontal address wire 8a contains p-type semiconductor material, vertical address wire 4a contains N
Type semiconductor, self-assembling formation semiconductor diode (i.e. self-built semiconductor diode) between them.In a second embodiment, water
Flat address wire 8a contains metal material, and vertical address wire 4a contains semiconductor material, one Schottky two of self-assembling formation between them
Pole pipe (i.e. self-built Schottky diode).In the third embodiment, horizontal address wire 8a contains semiconductor material, vertical address wire
4a contains metal material, another Schottky diode of self-assembling formation (i.e. self-built Schottky diode) between them.It is real the 4th
It applies in example, horizontal address wire 8a contains the first metal material, and vertical address wire 4a contains the second metal material, the first metal material
It is different metal material with the second metal material.Since the work function between them is different or they are between programming film 16a
Interface (interface) 7,5 it is different, positive counter current ratio can be improved using different metal material.
In the embodiment of Fig. 2 D, programming film 16a programs time film using multilayer.Wherein, programming film 16a contains the first programming
Secondary film 6 and second programs time film 6`, the two time film contains different programming materials.Such as first programs time film 6 containing gold
Belong to oxide, and the second programming time film 6` contains metal nitride.It can be improved by using different programming time film 6,6` positive and negative
Electric current ratio.In addition, being different from vertical address wire 4a- programming film by making horizontal address wire 8a- program the interface 7 between film 16a
Interface 5 between 16a can also be improved positive counter current ratio.
Fig. 3 A- Fig. 3 C indicates 3D-EPMVThree processing steps.All horizontal address layer 12a-12h are formed continuously
(Fig. 3 A).Particularly, after by substrate circuitry 0K planarization, first level conductor layer 12a is formed.This horizontal conductor layer
12a does not contain any figure.The first insulating layer 5a is formed on first level conductor layer 12a.Similarly, the first insulating layer 5a
Any figure is not contained yet.The second horizontal conductor layer 12b is re-formed on the first insulating layer 5a.So analogize, until forming institute
Some horizontal conductor layers (totally eight layers herein).In the forming process of Fig. 3 A, without image conversion step (such as lithography step).By
Keep good in the planarization of each horizontal conductor layer, 3D-EPMVTens of a horizontal conductor layers up to a hundred can be contained.It is foring
After all horizontal conductor layer 12a-12h, all horizontal conductor layer 12a-12h are etched disposably with shape by the first etching
At the horizontal address wire 8a-8h (Fig. 3 B) of a plurality of vertical stacking.Later, it is disposably formed by the second etching and multiple penetrates institute
There is the storage well 2a-2d (Fig. 3 C) of horizontal address wire 8a-8h.Storage film 6a-6d is covered on its side wall, and fills conductor material
Material, to form a plurality of vertical address wire 4a-4d.
Fig. 4 A is the symbol of storage member 1.Storage member 1 contains wordline 8 and bit line 4, and volume is contained between wordline 8 and bit line 4
Journey film 12 and diode 14.The resistance for programming film 12 is changed into low resistance in programming Shi Kecong high resistance or changes from low resistance
At high resistance.When alive numerical value is less than read voltage or direction opposite with read voltage outside, the resistance of diode 14, which is greater than, to be read
Resistance.Diode 14, which can be, to be formed by individual diode film, or by horizontal address wire, programming film and vertical address
(the i.e. self-built diode) of line self-assembling formation.
Due to thinner thickness, the positive counter current for programming film 6a-6d is more bad than general, and leakage current is larger.In order to avoid reading
Cause error or energy consumption larger since leakage current is excessive in the process, the present invention also proposes a kind of full-time course mode: in a read cycle
The information for all storage members storage that middle reading is electrically coupled with a selected word line.In read phase, maximum reverse is inclined in storage member
Set value of the value much smaller than its minimum forward bias voltage of voltage
Fig. 4 B indicates the reading circuit that the first storage array 10 uses.It uses full-time course mode.In this embodiment, horizontally
Location line 8a-8h is wordline, and vertical address wire 4a-4h is bit line.In other embodiments, horizontal address wire 8a-8h is bit line, is erected
Straight address wire 4a-4h is wordline, this has no effect on 3D-EPMVOperation.Storage array 10 contains wordline 8a- 8h, bit line 4a-
4h and storage member 1aa-1ad....The peripheral circuit of storage array 10, which contains multiplexer (MUX) 40 and one, to be read
Amplifier 30 out.In this embodiment, MUX 40 is 4-to-1MUX.
Fig. 4 C is its timing diagram.Read cycle T contains a pre-charging stage tpreWith a read phase tR: in precharge tpreRank
Section, all address wires (8a-8h, 4a-4h) are all charged to a predeterminated voltage V in storage array 16i(such as input of amplifying circuit 30
Bias voltage).In read phase tR, all bit line 4a-4h suspend, and the voltage of selected wordline 8a rises to read voltage VR, and lead to
Storage member 1aa-1ah is crossed to charge to all bit line 4a-4h.Voltage on every bit line is sent to sense amplifier by MUX 40 respectively
30.If the voltage is greater than the threshold voltage V of sense amplifier 30t, then V is exportedOOverturning.At the end of read cycle T, storage group
The digital informations that all storage member 1aa-1ah are stored in 1a are read, and at this moment the voltage change on all bit line 4a-4h is not
It can be more than VtToo much.Therefore, the reverse bias voltage of all reverse bias storage members is much smaller than read voltage in storage array 10
VR。
Fig. 4 D is the I-V curve of diode 14.Voltage change on read phase, all bit line 4a-4h is Vt, storage member
On reverse bias voltage be-Vt, forward bias voltage VR-Vt.As long as electrical (I-V) characteristic of diode 14 meets condition I
(VR-Vt)>>(n-1)*I(-Vt), 3D-EPM would not be influencedVNormal work.Here, n is institute on a bit line (such as 4a)
There is the number of storage member.It is noted that due to reverse bias voltage-VtValue be far smaller than read voltage VR.Even if 14 mass of diode
It is poor, due to VtVery little (~0.1V), above-mentioned condition is easily met.
For convenience of address decoding, the present invention also forms multiple vertical transistors using the side wall of storage well.Fig. 5 A- Fig. 5 C table
Show the third 3D-EPMV..It contains vertical transistor 3aa-3ad.Wherein, vertical transistor 3aa is a transmission transistor
(pass transistor), it contains grid 7a, gate medium 6a and channel 9a (Fig. 5 A).Channel 9a is by being filled in the storage well
Semiconductor material in 2a is constituted, and doping can be identical as vertical address wire 4a, thin or opposite.Grid 7a surrounds storage
Well 2a, 2e, and control transmission transistor 3aa, 3ae (Fig. 5 B)；Grid 7b is surrounded storage well 2b, 2f, and controls transmission crystal
Pipe 3ab, 3af；Grid 7c surrounds storage well 2c, 2g, and controls transmission transistor 3ac, 3ag；Grid 7d encirclement storage well 2d,
2h, and control transmission transistor 3ad, 3ah.Transmission transistor 3aa-3ah forms an at least decoder stage (Fig. 5 C).In an embodiment
In, when the voltage on grid 7a is height, and the voltage on grid 7b-7d is low, only transmission transistor 3aa and 3ae conducting,
Its transmission transistor disconnects.At this moment, the MUX 40` in substrate circuitry layer selects a signal in bit line 4a and 4e, send to
Sense amplifier 30.By forming multiple vertical transistor 3aa-3ad in storage well 2a-2d, the present invention can simplify decoder
Design.
Fig. 6 indicates a kind of multidigit member (multiple-bit-per-cell) 3D-EPMV.It contains multiple storage member 1aa-
1ah.In this embodiment, there are four types of states: ' 0 ' for storage member 1aa-1ah tool, and ' 1 ', ' 2 ', ' 3 ', the storage member of different conditions
The program current that 1aa-1ah is used is different, and therefore, they have different resistance.Wherein, storage member 1ac, 1ae, 1ah is shape
State ' 0 ', it is unprogrammed, and programming film 6c, 6e, 6h are complete.Other storage members have programmed.Wherein, storage member 1ab, 1ag is
State ' 1 ', conductor silk 11b is most thin, and resistance is maximum in all programming films programmed；Storage member 1aa is state ' 3 ',
Conductor silk 11d is most thick, and resistance is minimum in all programming films programmed；Storing member 1ad, 1af is state ' 2 ', conductor silk
Between conductor silk 11b and 11d, resistance also falls between the size of 11c.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention
It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims,
The present invention should not be any way limited.
Claims (10)
1. a kind of three-dimensional longitudinal electrical programming memory (3D-EPMV), it is further characterized in that containing:
One contains the semiconductor substrate (0) of a substrate circuitry (0K)；
Multilayer is on the substrate circuitry (0K) and the horizontal address wire (8a-8h) of vertical stacking；
Multiple storage wells (2a-2d) for penetrating the multiple-layer horizontal address wire (8a-8h) and being parallel to each other；
The thickness of one layer of storage film (6a) for covering storage well (2a-2d) abutment wall, the storage film (6a) is less than 100nm；
The a plurality of vertical address wire (4a-4d) in the storage well (2a-2d)；
Multiple storage member (1ha- positioned at the horizontal address wire (8a-8h) and the vertical address wire (2a-2d) infall
1aa)；
Under read phase, maximum reverse bias voltage suffered by the storage member is much smaller than read voltage.
2. memory according to claim 1, it is further characterized in that: the storage film (6a) does not contain individual diode
Film.
3. memory according to claim 1, it is further characterized in that: the storage film (6a) contains programming film (16a)
With a diode film (18a).
4. memory according to claim 1, it is further characterized in that: a horizontal address wire corresponds to a wordline, and one
The vertical address wire corresponds to a bit line.
5. memory according to claim 1, it is further characterized in that: a horizontal address wire corresponds to a bit line, and one
The vertical address wire corresponds to a wordline.
6. memory according to claim 1, it is further characterized in that: the wordline and the bit line contain respectively reversely to be mixed
Miscellaneous semiconductor material.
7. memory according to claim 1, it is further characterized in that: the wordline and the bit line contain metal material respectively
Material and semiconductor material.
8. memory according to claim 1, it is further characterized in that: the wordline and the bit line contain different metal material
Material.
9. memory according to claim 1, it is further characterized in that: the programmable film (6a) is contained first and second times
Film, first and second films contain different programmable materials.
10. memory according to claim 1, it is further characterized in that: each storage member has N(N > 2) kind state
(11b-11d), the programmable film (6a) under different conditions have different resistance.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810056756.6A CN110071136A (en) | 2018-01-21 | 2018-01-21 | Three-dimensional longitudinal direction electrical programming memory |
| US15/911,078 US20180190715A1 (en) | 2016-04-16 | 2018-03-03 | Three-Dimensional Vertical Multiple-Time-Programmable Memory with A Thin Memory Layer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810056756.6A CN110071136A (en) | 2018-01-21 | 2018-01-21 | Three-dimensional longitudinal direction electrical programming memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023011561A1 (en) * | 2021-08-06 | 2023-02-09 | 南方科技大学 | Memory |
| WO2024067048A1 (en) * | 2022-09-30 | 2024-04-04 | 华为技术有限公司 | Three-dimensional memory array, memory and electronic device |
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