CN110544742A - Ferroelectric phase change hybrid storage unit, memory and operation method - Google Patents
Ferroelectric phase change hybrid storage unit, memory and operation method Download PDFInfo
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- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
- H10N70/235—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
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Abstract
the invention relates to a ferroelectric phase change hybrid memory unit, a memory and an operation method. The ferroelectric phase change hybrid memory cell includes: the lower electrode, the functional layer and the upper electrode are arranged in sequence; the lower electrode is a low work function electrode, and the upper electrode is a high work function electrode; the functional layer is made of ferroelectric phase change materials. By adopting the above structure, the ferroelectric-phase-change hybrid memory cell can selectively operate in a ferroelectric memory state or a phase-change memory state.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a ferroelectric phase change hybrid memory unit, a memory and an operation method.
Background
The popularization of smart phones and various wearable electronic devices causes the data volume needing to be stored to increase explosively, and higher requirements are put forward on the capacity, power consumption and other performances of a memory. Existing memory products include volatile DRAM and SRAM, non-volatile Flash, ferroelectric storage FeRAM, phase change memory PCM, and the like. The read-write speed of the DRAM and the SRAM is extremely high, but the storage density is very low; due to the development of the 3D NAND technology, the Flash can greatly improve the storage capacity at present, and is expected to replace an HDD (hard disk drive) as a new main memory, but the single-layer density of the Flash is close to the limit, the number of stackable layers is limited by the depth-width ratio which can be realized by deep hole etching and the step coverage of material filling, and the read-write speed of the Flash is 100us level, so that the higher speed cannot be realized.
The ferroelectric storage FeRAM is recently seen again due to the ferroelectricity found in the CMOS process compatible material HfO2, the extremely low power consumption and the fast read-write capability thereof are concerned, the fast read-write thereof can reach the level of DRAM, and the low power consumption and the non-volatility thereof make it hopefully replace DRAM, but the endurance against writing is poor.
the phase change memory PCM has three-dimensional stackability similar to flash, can realize large capacity, is expected to replace the flash, has the read-write speed of 100ns, needs to adopt larger current for erasing and writing in order to melt and amorphize materials due to lower crystalline resistance, and has serious power consumption problem on the current integration level.
Disclosure of Invention
In view of the above drawbacks and needs of the prior art, the present invention provides a ferroelectric-phase-change hybrid memory cell, a memory and an operating method thereof, which can selectively operate in a phase-change memory state or a ferroelectric memory state, and can integrate the advantages of ferroelectric memory and phase-change memory.
According to one aspect of the present invention, a ferroelectric phase change hybrid memory cell of the present invention comprises:
The lower electrode, the functional layer and the upper electrode are arranged in sequence;
The lower electrode is a low work function electrode, and the upper electrode is a high work function electrode;
The functional layer is made of ferroelectric phase change materials.
As a further improvement of the present invention, the ferroelectric phase change material is:
A multi-component compound [ GeTe ] x [ Sb2Te3] y formed by GeTe and Sb2Te3, wherein x is a positive integer, y is a natural number, and x is more than y;
Or a superlattice of a multilayer structure formed by alternately growing GeTe and Sb2Te 3;
Or the compound In2Se 3;
or a compound formed by doping element Se or C with GeTe, wherein the doping proportion is 10-50%.
as a further improvement of the invention, the compound [ GeTe ] x [ Sb2Te3] y is one or more of Ge2Sb2Te5, Ge1Sb2Te4 and GeTe.
as a further improvement of the invention, the low work function electrode is one or more of Ti, Al, TiW and Cr, and/or the high work function electrode is one or more of Au, Pt, Ni and Pd.
As a further improvement of the present invention, if the functional layer is an n-type semiconductor, the functional layer forms ohmic contact with the low work function electrode, and the functional layer forms schottky contact with the high work function electrode; if the functional layer is a p-type semiconductor, the functional layer and the low work function electrode form Schottky contact, and the functional layer and the high work function electrode form ohmic contact.
as a further improvement of the invention, a first voltage is applied to the ferroelectric phase change hybrid memory cell in a crystallization state, so that the ferroelectric phase change hybrid memory cell works in a phase change memory state, the first voltage amplitude is larger than the voltage amplitude required by melting of the ferroelectric phase change hybrid memory cell, the pulse width is smaller than 200ns, and the pulse falling edge is smaller than 20 ns;
Or applying a second voltage to the ferroelectric phase change hybrid memory cell in the crystallization state to enable the ferroelectric phase change hybrid memory cell to work in the ferroelectric memory state, wherein the second voltage is a forward voltage, and the amplitude of the second voltage exceeds the ferroelectric coercivity of the ferroelectric phase change material and is lower than the voltage amplitude required by melting of the material.
According to a second aspect of the present invention, a method of operating a ferroelectric phase change hybrid memory cell of the present invention comprises the steps of:
applying a first voltage to the ferroelectric phase change hybrid memory cell in a crystallization state to enable the ferroelectric phase change hybrid memory cell to work in a phase change memory state, wherein the amplitude of the first voltage is larger than the amplitude of the voltage required by melting of the ferroelectric phase change hybrid memory cell, the pulse width is smaller than 200ns, and the pulse falling edge is smaller than 20 ns;
Or applying a second voltage to the ferroelectric phase change hybrid memory cell in the crystallization state to enable the ferroelectric phase change hybrid memory cell to work in the ferroelectric memory state, wherein the second voltage is a forward voltage, and the amplitude of the second voltage exceeds the ferroelectric coercivity of the ferroelectric phase change material and is lower than the voltage amplitude required by melting of the material.
According to a third aspect of the present invention, a ferroelectric phase change hybrid memory of the present invention comprises: a plurality of ferroelectric phase change hybrid memory cells as described in any one of the above.
According to a fourth aspect of the present invention, an operation method of a ferroelectric phase change hybrid memory of the present invention includes the steps of:
Applying a first voltage to a part of ferroelectric phase change hybrid memory cells in a crystallization state to enable the part of ferroelectric phase change hybrid memory cells to work in a phase change memory state, wherein the amplitude of the first voltage is larger than the amplitude of the voltage required by melting of the ferroelectric phase change hybrid memory cells, the pulse width is smaller than 200ns, and the pulse falling edge is smaller than 20 ns;
And applying a second voltage to the other part of the ferroelectric phase change hybrid memory cells in the crystallization state to enable the part of the ferroelectric phase change hybrid memory cells to work in the ferroelectric memory state, wherein the second voltage is a forward voltage, and the amplitude of the second voltage exceeds the ferroelectric coercive force of the ferroelectric phase change material and is lower than the voltage amplitude required by melting of the material.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
(1) the memory unit and the memory function layer of the invention adopt ferroelectric phase change materials, and simultaneously the lower electrode is a low work function electrode, and the upper electrode is a high work function electrode, so that the memory unit and the memory function layer can work in a phase change memory state or a ferroelectric memory state optionally by adopting different initial operation logics, and can integrate the advantages of ferroelectric memory and phase change memory.
(2) Because the phase change memory unit and the ferroelectric memory unit are on the same chip, the phase change memory can be used as a main memory, the ferroelectric memory can replace a DRAM (dynamic random access memory), the distance between the phase change memory unit and the ferroelectric memory is very close, the communication interconnection line between the phase change memory unit and the ferroelectric memory is greatly simplified, the communication speed and efficiency between the phase change memory unit and the ferroelectric memory are greatly improved, the interconnection distance is shortened, and the communication power consumption is reduced.
(3) The ferroelectric phase change hybrid memory with the phase change storage function and the ferroelectric storage function can be obtained based on the same preparation process steps, so that the process preparation cost is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of a ferroelectric-phase-change hybrid memory cell according to an embodiment of the present invention;
Fig. 2 to 4 are schematic diagrams illustrating an operation method of a memory cell according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are intended to be illustrative only and are not intended to be limiting. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
the ferroelectric phase change hybrid memory cell comprises a lower electrode, a functional layer and an upper electrode, wherein the functional layer is filled with a ferroelectric phase change material, the functional layer is arranged between the lower electrode and the upper electrode, the lower electrode is a low work function electrode, the low work function generally means that the work function is between 4.0 and 4.4eV, such as one or more of Ti, Al, TiW and Cr, and can be used as a heating rod of the phase change material, the upper electrode is a high work function electrode, and the high work function generally means that the work function is between 5.0 and 5.6eV, such as one or more of Au, Pt, Ni and Pd. If the functional layer is an n-type semiconductor, the functional layer and the low work function electrode form ohmic contact, and the functional layer and the high work function electrode form Schottky contact; in the case of a p-type semiconductor, the functional layer forms a schottky contact with the low work function electrode and the functional layer forms an ohmic contact with the high work function electrode.
As shown in fig. 1, a T-shaped structure may be adopted, and the contact area between the lower electrode and the functional layer is small.
the functional layer is a ferroelectric phase change material, and can have ferroelectric properties and phase change properties under different conditions, and specifically can be any one or more of the following compounds: (1) a compound [ GeTe ] x- [ Sb2Te3] y, (x is a positive integer, y is a natural number, x > y), such as Ge2Sb2Te5, Ge1Sb2Te4, GeTe; (2) a superlattice formed by GeTe and Sb2Te3, a multilayer structure formed by GeTe and Sb2Te3 which are alternately grown, and the thickness ratio is preferably one of 4:1,3:1,2:1,1:1,1:2,1:3 and 1: 4; (3) indium selenide In2Se 3; (4) GeTe is doped with compounds of elements such as Se, C and the like to improve the resistivity, such as GeTe1-xSex, wherein x is preferably 10-50%; GeTe1-yCy, wherein y is preferably 10% -50%.
The ferroelectric phase change hybrid memory cell can realize the unilateral Schottky barrier required by the ferroelectric diode device through the arrangement of the upper electrode and the lower electrode, so as to realize the diode rectification characteristic. When the actual device is operated, the direction of ferroelectric polarization is changed by using an electric field, so that the height of a Schottky barrier can be changed, the high resistance and the low resistance of the device are converted, and the aim of nonvolatile storage is fulfilled.
The memory cell based on the ferroelectric phase change material adopts a cross lattice structure, and a ferroelectric phase change hybrid memory can be prepared. The ferroelectric phase change hybrid memory comprises a plurality of ferroelectric phase change hybrid memory cells.
the ferroelectric phase change hybrid memory cell has two pre-operation methods, and can make the memory cell work in a phase change memory state or a ferroelectric memory state. The following description takes an In2Se3 ferroelectric phase change cell with a lateral dimension of 5um as an example:
Before operation, the ferroelectric phase change mixed memory unit is subjected to annealing treatment exceeding the crystallization temperature of the ferroelectric phase change material, so that the ferroelectric phase change mixed memory unit is in a crystallization state. If a deposition phase change-ferroelectric film is adopted, the memory is initially in an amorphous high-resistance state Rhigh _ Ph, and the whole array is subjected to annealing treatment exceeding the crystallization temperature of the phase change material once, if GeTe is adopted as a functional layer, the annealing condition can be set to 300 ℃ for 1 h. The memory can be in a crystalline state through annealing treatment, and the resistance value is Rlow _ Ph.
And operation A, applying a first voltage to the ferroelectric phase change hybrid memory cell in the crystallization state to enable the ferroelectric phase change hybrid memory cell to work in the phase change memory state, wherein the first voltage amplitude is larger than the voltage amplitude required by melting of the ferroelectric phase change hybrid memory cell, the pulse width is smaller than 200ns, and the pulse falling edge is smaller than 20 ns. The ferroelectric phase change memory cell in a crystallization state is applied with a narrow and high voltage pulse to change the memory cell into an amorphous state, typical values are, for example, Vreset is 3V, treset is 70ns, and pulse falling edge tset _ tail is 8ns, the phase change material is characterized in that the amorphous state can be obtained when the ferroelectric phase change memory cell is applied above a melting temperature and then suddenly cooled, the resistance value is a high resistance value Rhigh _ Ph, and the range is generally 1M-10M Ω, so that the memory cell works in the phase change memory state. After that, along with the erasing logic of the phase change memory, wide and short voltage pulses are respectively adopted, the amplitude Vset exceeds the voltage required by crystallization of the phase change unit and is lower than the voltage required by melting, the pulse width tset is 500ns-10us, the pulse falling edge treset _ tail is 100ns-1us, typical values are 1.5V and 5 mus, the pulse falling edge treset _ tail is 100ns, so that the device is changed into a low-resistance state Rlow _ Ph, generally ranging from 1k to 10k omega, and the device is changed into a high-resistance state Rhigh _ Ph by adopting a narrow and high pulse Vreset.
and B, applying a second voltage to the ferroelectric phase change hybrid memory cell in the crystallization state to enable the ferroelectric phase change hybrid memory cell to work in the ferroelectric memory state, wherein the second voltage is a forward voltage, and the amplitude of the second voltage exceeds the ferroelectric coercivity of the ferroelectric phase change material and is lower than the voltage amplitude required by melting of the material. The ferroelectric phase change memory cell In the crystallized state has ferroelectricity, for example, for an In2Se3 thin film with the thickness of 100nm and the transverse dimension of 5um, the out-of-plane coercive force is 10-20V/um, the use of a forward voltage of 2V can enable the In2Se3 In the crystalline state to have ferroelectric polarization, specifically, the ferroelectric polarization direction can be towards the lower electrode, the schottky barrier height between the upper electrode and the functional layer is reduced, and thus the device is In the Rlow _ fe state, so that the memory cell works In the ferroelectric memory state. Then, along with the erasing logic of the ferroelectric diode, the forward voltage + Vfe is respectively adopted to enable the device to be in the Rlow _ fe state (the resistance value range is 1k-5k omega), and the reverse voltage-Vfe is adopted to enable the ferroelectric polarization direction to be upward, increase the Schottky barrier height and enable the device to be in the Rhigh _ fe state (the resistance value range is 100k-500k omega).
Based on the two operation modes a and B, different memory cells of the same memory can be respectively operated in the phase-change memory state and the ferroelectric memory state. For application scenes requiring low power consumption and high-speed reading and writing, the memory cell or a certain area is set to be in a ferroelectric memory state by adopting operation B and used as a ferroelectric memory. For general application, operation A is adopted to enable a storage area to be in a phase change storage state, and higher erasing resistance and reliability are achieved.
an operation method of a ferroelectric phase change memory according to an embodiment of the present invention is described below with reference to fig. 2 to 4. The ferroelectric phase change hybrid memory is composed of 4 sedimentary ferroelectric phase change hybrid units. Each ferroelectric phase change hybrid memory cell is initially in a homogeneous high resistance state Rhigh _ Ph as shown in fig. 2. The operation method of the ferroelectric phase change memory includes the steps of:
(1) the entire memory array may be annealed beyond the crystallization temperature of the phase change material once prior to operation. If GeTe is used as the functional layer, the annealing condition may be set to 300 ℃ for 1 h. All the memory cells can be in a crystalline state Rlow _ Ph through annealing treatment, and the crystal state Rlow _ Ph is shown in FIG. 3;
(2) taking 4 memory cells in a polycrystalline state after annealing in the step as an example, operation B is performed on the cell 4, and a forward voltage is applied, the magnitude Vfe of which exceeds the ferroelectric coercivity Ec of the phase change-ferroelectric material and is much lower than the voltage Vset required for melting the material, so that the ferroelectric polarization direction can be oriented toward the lower electrode, and the device is in a ferroelectric polarization state Rlow _ fe, as shown in fig. 4 for the cell 4. For the remaining 3 cells, operation a is performed, such as applying narrow and high voltage pulses, amplitude Vreset, pulse width tresset, to cells 1 and 2, causing the memory cell to become amorphous, such as cells 1 and 2, Rhigh _ Ph in fig. 4.
the 4 cells processed in step 2,1, 2, and 3, can be used as phase change memory cells, and the erase/write logic of the phase change memory is adopted to apply a wide and short voltage pulse, an amplitude Vset, a pulse width tset, and a falling edge tset _ tail to change the device into a low resistance state, i.e., a polycrystalline state, with a resistance value Rlow _ Ph, and apply a narrow and high pulse, an amplitude Vreset, a pulse width treset, and a falling edge treset _ tail to change the device into a high resistance state, i.e., an amorphous state, with a resistance value Rhigh _ Ph, respectively. The cell 4 can be used as a ferroelectric memory cell, and the erasing logic of a ferroelectric diode is used, and the forward voltage + Vfe is respectively adopted to enable the device to be in an Rlow _ fe state, and the reverse voltage-Vfe is adopted to enable the device to be in an Rhigh _ fe state.
applying operations a and B to the entire memory array, it is possible to realize a part of the area as phase change memory cells and another part as ferroelectric memory cells.
the memory unit and the memory function layer of the invention adopt ferroelectric phase change materials, and simultaneously the lower electrode is a low work function electrode, and the upper electrode is a high work function electrode, so that the memory unit and the memory function layer can work in a phase change memory state or a ferroelectric memory state optionally by adopting different initial operation logics, and can integrate the advantages of ferroelectric memory and phase change memory. Because the phase change memory unit and the ferroelectric memory unit are on the same chip, the phase change memory can be used as a main memory, the ferroelectric memory can replace a DRAM (dynamic random access memory), the distance between the phase change memory unit and the ferroelectric memory is very short, the communication interconnection line between the phase change memory unit and the ferroelectric memory is greatly simplified, the communication speed and efficiency between the phase change memory unit and the ferroelectric memory are greatly improved, the interconnection distance is shortened, and the communication power consumption is reduced. In addition, the ferroelectric phase change hybrid memory with the phase change memory and the ferroelectric memory functions can be obtained based on the same preparation process steps, so that the process preparation cost is greatly reduced.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A ferroelectric phase change hybrid memory cell, comprising:
The lower electrode, the functional layer and the upper electrode are arranged in sequence;
the lower electrode is a low work function electrode, and the upper electrode is a high work function electrode;
The functional layer is made of ferroelectric phase change materials.
2. A ferroelectric phase change hybrid memory cell as in claim 1, wherein said ferroelectric phase change material is:
a multi-component compound [ GeTe ] x [ Sb2Te3] y formed by GeTe and Sb2Te3, wherein x is a positive integer, y is a natural number, and x is more than y;
Or a superlattice of a multilayer structure formed by alternately growing GeTe and Sb2Te 3;
or the compound In2Se 3;
or a compound formed by doping element Se or C with GeTe, wherein the doping proportion is 10-50%.
3. A ferroelectric phase change hybrid memory cell as in claim 2, wherein said compound [ GeTe ] x [ Sb2Te3] y is one or more of Ge2Sb2Te5, Ge1Sb2Te4 and GeTe.
4. a ferroelectric phase change hybrid memory cell as in claim 2, wherein the low work function electrode is one or more of Ti, Al, TiW and Cr and/or the high work function electrode is one or more of Au, Pt, Ni and Pd.
5. A ferroelectric phase change hybrid memory cell as in any one of claims 1 to 4, wherein if said functional layer is an n-type semiconductor, said functional layer forms an ohmic contact with said low work function electrode and said functional layer forms a Schottky contact with said high work function electrode;
if the functional layer is a p-type semiconductor, the functional layer and the low work function electrode form Schottky contact, and the functional layer and the high work function electrode form ohmic contact.
6. a ferroelectric phase change hybrid memory cell as in any one of claims 1 to 4, wherein a first voltage is applied to the ferroelectric phase change hybrid memory cell in a crystallized state so that the ferroelectric phase change hybrid memory cell operates in a phase change memory state, said first voltage has a magnitude larger than a voltage magnitude required for melting the ferroelectric phase change hybrid memory cell and has a pulse width of less than 200ns and a pulse falling edge of less than 20 ns;
or applying a second voltage to the ferroelectric phase change hybrid memory cell in the crystallization state to enable the ferroelectric phase change hybrid memory cell to work in the ferroelectric memory state, wherein the second voltage is a forward voltage, and the amplitude of the second voltage exceeds the ferroelectric coercivity of the ferroelectric phase change material and is lower than the voltage amplitude required by melting of the material.
7. a method of operating a ferroelectric phase change hybrid memory cell as in any of claims 1 to 6, comprising the steps of:
Applying a first voltage to the ferroelectric phase change hybrid memory cell in a crystallization state to enable the ferroelectric phase change hybrid memory cell to work in a phase change memory state, wherein the amplitude of the first voltage is larger than the amplitude of the voltage required by melting of the ferroelectric phase change hybrid memory cell, the pulse width is smaller than 200ns, and the pulse falling edge is smaller than 20 ns;
or applying a second voltage to the ferroelectric phase change hybrid memory cell in the crystallization state to enable the ferroelectric phase change hybrid memory cell to work in the ferroelectric memory state, wherein the second voltage is a forward voltage, and the amplitude of the second voltage exceeds the ferroelectric coercivity of the ferroelectric phase change material and is lower than the voltage amplitude required by melting of the material.
8. A method of operating a ferroelectric phase change hybrid memory cell as in claim 7, further comprising, prior to said applying of said first voltage or said second voltage, the steps of:
And applying annealing treatment exceeding the crystallization temperature of the ferroelectric phase change material to the ferroelectric phase change hybrid memory unit so as to enable the ferroelectric phase change hybrid memory unit to be in a crystallization state.
9. a ferroelectric phase change hybrid memory, comprising: a plurality of ferroelectric phase change hybrid memory cells as claimed in any one of claims 1 to 6.
10. a method of operating a ferroelectric phase change hybrid memory as in claim 9, comprising the steps of:
Applying a first voltage to a part of ferroelectric phase change hybrid memory cells in a crystallization state to enable the part of ferroelectric phase change hybrid memory cells to work in a phase change memory state, wherein the amplitude of the first voltage is larger than the amplitude of the voltage required by melting of the ferroelectric phase change hybrid memory cells, the pulse width is smaller than 200ns, and the pulse falling edge is smaller than 20 ns;
And applying a second voltage to the other part of the ferroelectric phase change hybrid memory cells in the crystallization state to enable the part of the ferroelectric phase change hybrid memory cells to work in the ferroelectric memory state, wherein the second voltage is a forward voltage, and the amplitude of the second voltage exceeds the ferroelectric coercive force of the ferroelectric phase change material and is lower than the voltage amplitude required by melting of the material.
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| WO2022082605A1 (en) * | 2020-10-22 | 2022-04-28 | 中国科学院微电子研究所 | Method for manufacturing programmable diode, programmable diode, and ferroelectric memory |
| WO2022189300A1 (en) * | 2021-03-11 | 2022-09-15 | International Business Machines Corporation | Phase-change memory device with reduced programming voltage |
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