CN110061125B - Manufacturing method of magnetic random access memory with three-dimensional structure - Google Patents

Manufacturing method of magnetic random access memory with three-dimensional structure Download PDF

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CN110061125B
CN110061125B CN201810048261.9A CN201810048261A CN110061125B CN 110061125 B CN110061125 B CN 110061125B CN 201810048261 A CN201810048261 A CN 201810048261A CN 110061125 B CN110061125 B CN 110061125B
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CN110061125A (en
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刘少鹏
陆宇
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CETHIK Group Ltd
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
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    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a manufacturing method of a three-dimensional magnetic random access memory, which comprises the steps of firstly depositing a first electrode layer on a substrate, and sequentially generating multiple layers of MTJ (magnetic tunnel junction) units on the first electrode layer according to the number of preset MTJ unit layers and the same method to form a three-dimensional structure; and etching a channel between each column of MTJ units in the three-dimensional structure, manufacturing a selective switch tube in the channel, finally performing oxide deposition in the channel, etching away the deposited oxide along the side wall of the channel, performing substrate ion implantation and epitaxy in the channel, etching out an isolation groove, filling the isolation groove with an insulating material, and finally performing ion implantation to finish the preparation. The invention stereoscopically realizes the planar structure, and the capacity of the magnetic random access memory is multiplied under the condition of not increasing the area.

Description

Manufacturing method of magnetic random access memory with three-dimensional structure
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of a magnetic random access memory with a three-dimensional structure.
Background
MRAM (Magnetic Random Access Memory) is a nonvolatile magnetic random access memory. It has high-speed read-write capability of Static Random Access Memory (SRAM), high integration of Dynamic Random Access Memory (DRAM), and far lower power consumption than DRAM, and performance does not degrade with increasing use time relative to Flash memory (Flash). MRAM is considered to be capable of replacing SRAM, DRAM, EEPROM and Flash because of the above-described features that MRAM has, which is called universal memory (universal memory).
Unlike conventional random access memory chip fabrication techniques, the data in MRAM is not stored in the form of charge or current, but rather is stored in a magnetic state, and is sensed by measuring resistance without disturbing the magnetic state. MRAM employs a Magnetic Tunnel Junction (MTJ) structure for data storage, and generally, MRAM cells are formed of a transistor (1T) and a Magnetic Tunnel Junction (MTJ) together to form a memory cell, where the Magnetic Tunnel Junction (MTJ) structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. One of the electromagnetic layers is a fixed magnetic layer, and the electrode is fixed in a specific direction through a strong fixed field. And the other is a freely rotatable magnetic layer holding the electrode on one of the two sides.
However, conventional MRAM is fabricated based on planar technology, with slightly larger capacity requiring a large area.
Disclosure of Invention
The invention aims to provide a manufacturing method of a magnetic random access memory with a three-dimensional structure, which adopts the three-dimensional structure to manufacture, and increases the number of Magnetic Tunnel Junctions (MTJs) in a unit area, thereby improving the capacity of the magnetic random access memory.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a method for manufacturing a magnetic random access memory with a three-dimensional structure, comprising:
step 1, depositing a first electrode layer on a substrate;
step 2, generating a first layer of MTJ (magnetic tunnel junction) unit on the first electrode layer through photoetching and etching;
step 3, performing oxide deposition and chemical mechanical polishing on the first layer of MTJ unit, and depositing a protective layer;
step 4, etching the protection layer corresponding to the first layer of MTJ unit, and depositing a second electrode layer on the protection layer and the first layer of MTJ unit;
step 5, stacking on the second electrode layer by adopting the method from step 2 to step 4 according to the preset number of MTJ (magnetic tunnel junction) unit layers to form a three-dimensional structure;
step 6, etching a channel between each column of MTJ units in the three-dimensional structure, wherein the bottom of the etched channel reaches the substrate;
step 7, etching oxide corresponding to each MTJ unit along the side wall of the channel by wet etching according to a first preset depth;
step 8, backfilling the channel and the etched oxide part by using polysilicon, and re-etching the channel, wherein the bottom of the etched channel reaches the upper part of the substrate;
step 9, etching polysilicon corresponding to each MTJ unit along the side wall of the channel according to a second preset depth;
step 10, oxide deposition is carried out in the channel, and the deposited oxide is etched away along the side wall of the channel;
and 11, performing substrate ion implantation and epitaxy in the channel, etching the isolation groove, filling the isolation groove with an insulating material, and finally performing ion implantation to finish preparation.
Further, ni is deposited between the substrate and the first electrode layer.
Further, the thickness of the Ni deposit is 200-300A.
Further, the forming the first layer MTJ cell by photolithography and etching on the first electrode layer further includes:
and depositing a protective layer around the etched MTJ cylinder on the first electrode layer.
Further, the protective layer is silicon nitride SIN with the thickness of 200-400A.
Further, the oxide deposited on the MTJ cell has a thickness of 300 to 600A and the protective layer has a thickness of 200 to 400A.
Further, the first preset depth is 500-800A.
Further, the second preset depth is 100-300A.
Further, the isolation groove is filled with an insulating material, and the insulating material is SiO 2 。
The invention provides a manufacturing method of a three-dimensional magnetic random access memory, which sequentially generates multiple layers of MTJ (magnetic tunnel junction) units on a first electrode layer according to the number of preset MTJ unit layers to form a three-dimensional structure; and etching a channel between each column of MTJ units in the three-dimensional structure, manufacturing a selective switch tube in the channel, finally performing oxide deposition in the channel, etching away the deposited oxide along the side wall of the channel, performing substrate ion implantation and epitaxy in the channel, etching out an isolation groove, filling the isolation groove with an insulating material, and finally performing ion implantation to finish the preparation. The invention stereoscopically realizes the planar structure, and the capacity of the magnetic random access memory is multiplied under the condition of not increasing the area.
Drawings
FIG. 1 is a schematic diagram of a method for fabricating a magnetic random access memory with a three-dimensional structure according to the present invention;
FIG. 2 is a schematic diagram of a first layer MTJ cell structure according to an embodiment of the invention;
FIG. 3 is a schematic view of an oxide deposition and polishing structure according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure after depositing a passivation layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a passivation layer etching structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a second electrode layer deposition structure according to an embodiment of the present invention;
FIG. 7 is a schematic perspective view of an embodiment of the present invention;
FIG. 8 is a schematic diagram of a trench etching structure according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a trench sidewall oxide etch structure in accordance with an embodiment of the present invention;
FIG. 10 is a schematic diagram of a trench polysilicon fill structure in accordance with an embodiment of the present invention;
FIG. 11 is a schematic diagram of a polysilicon etching structure according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a polysilicon pullback etching structure according to an embodiment of the present invention;
FIG. 13 is a schematic view of a trench maintenance filling structure in accordance with an embodiment of the present invention;
FIG. 14 is a schematic diagram of a trench oxide etch configuration in accordance with an embodiment of the present invention;
FIG. 15 is a schematic view showing the structure of a silicon substrate after ion implantation and epitaxy in accordance with an embodiment of the present invention;
FIG. 16 is a schematic diagram of the structure of an embodiment of the invention after isolation trench etching and filling and ion implantation;
fig. 17 is a schematic diagram of a magnetic random access memory circuit corresponding to a three-dimensional structure according to an embodiment of the invention.
Detailed Description
The technical scheme of the present invention will be further described in detail below with reference to the accompanying drawings and examples, which are not to be construed as limiting the present invention.
The method for manufacturing the magnetic random access memory with the three-dimensional structure in the embodiment, as shown in fig. 1, comprises the following steps:
and S1, depositing a first electrode layer on the substrate.
In particular, the substrate of the present embodiment is a semiconductor substrate, and the substrate of the mram may be a metal, glass, silicon or metal alloy, and silicon is the best choice because it is easy to process into an integrated circuit (although a magnetic sensor does not always require such a circuit). This embodiment will be described with silicon as an example.
The first electrode layer is deposited on the silicon substrate and used as the lower electrode of the first layer MTJ cell, and the thickness of the first electrode layer is 400A-700A. In the magnetic random access memory, the upper electrode and the lower electrode are films formed by conductive materials commonly used in the field, and are selected from any one of Ta, taN, ti, tiN, taAlN and TiAlN, and TaN is adopted in the embodiment.
Preferably, ni (200-300A) is also deposited between the silicon substrate and the first electrode layer for forming silicide in combination with Si to reduce resistance.
For convenience of description, the electrode layers TaN and Ni are also denoted by one layer in the drawings of the present embodiment, and are denoted as TaN or TaN/Ni.
And S2, generating a first-layer MTJ (magnetic tunnel junction) unit by photoetching and etching on the first electrode layer.
Specifically, as shown in fig. 2, the stack of MTJ cells is fabricated by conventional methods, which are not described in detail herein. The MTJ element is composed of a pinned Layer (Pinning Layer), a Tunnel Barrier Layer (Tunnel Barrier), and a Free Layer (Free Layer). The pinning Layer is composed of a ferromagnetic Layer (Pinned Layer) and an antiferromagnetic Layer (AFM Layer), and the exchange coupling between the ferromagnetic Layer and the antiferromagnetic Layer determines the magnetic moment direction of the ferromagnetic Layer; the tunnel barrier layer is typically composed of MgO or Al2O3 and is located on top of the ferromagnetic layer. The ferromagnetic layer is located on top of the tunnel barrier layer. The lower (Bottom Conducting Layer) and upper (Top Conducting Layer) electrode layers are in direct electrical contact with the associated antiferromagnetic and free layers, and the electrode layers are typically of a non-magnetic conductive material.
In this embodiment, a protective layer is deposited around the etched MTJ cylinder on the first electrode layer, where the protective layer is usually made of silicon nitride SIN, siNx, alOx, or other materials, and has a thickness of about 200-400A, preferably 150A, a being 10 nm to the minus 10 nm.
And S3, performing oxide deposition and chemical mechanical polishing on the first layer of MTJ unit, and depositing a protective layer.
As shown in fig. 3, the present embodiment performs oxide deposition and chemical mechanical polishing on the first layer MTJ cell. In the fabrication of magnetic random access memory, the oxide may be a dielectric material commonly known in the art, such as SiO2 or other oxides. The chemical mechanical polishing of CMP (Chemical Mechanical Polishing) of this embodiment planarizes the surface and makes the uppermost MTJ layer level with the oxide surface for subsequent contact with the overlying second electrode layer.
As shown in fig. 4, a protective layer is deposited on the MTJ cell and the oxide of the first layer, and the protective layer is usually made of silicon nitride SIN, siNx, alOx, or other materials, and has a thickness of about 200-400A, preferably 150A, a being 10 nm to the minus 10 th power of a.
In the fabrication, the surface is not flat after filling oxide and SIN, and CMP planarization can be used. The thickness of the oxide is 300A-600A, and the thickness of the protective layer is about 200-400A.
The deposition of the oxide of the present embodiment may fill the space and also facilitate the subsequent fabrication of other components. The deposition of the protection layer is also used to protect the MTJ cell from being affected in subsequent fabrication.
The oxide deposited in this embodiment is convenient for lateral etching to fill polysilicon in the subsequent steps to manufacture the gate of the select switch tube, and will not be described here again.
And S4, etching the protection layer corresponding to the first layer of the MTJ unit, and depositing a second electrode layer on the protection layer and the first layer of the MTJ unit.
As shown in fig. 5, the present embodiment etches away the corresponding protective layer of the MTJ cell, and deposits a second electrode layer (as shown in fig. 6) on the protective layer and the first layer MTJ cell, so that the second electrode layer is electrically connected to the MTJ cell.
In this embodiment, the second electrode layer is used as the upper electrode of the first MTJ cell and is used as the lower electrode of the next MTJ cell, which are not described herein.
And S5, continuing to stack the second electrode layer by adopting the method of the steps S2-S4 according to the preset number of the MTJ (magnetic tunnel junction) unit layers to form a three-dimensional structure.
In order to increase the number of MTJs in a unit area, the embodiment adopts a layer-by-layer stacking method to continuously increase the number of MTJs, and the stacking is performed by continuously repeating the steps S2-S4 according to the number of MTJ cell layers preset during design. For example, three layers are designed, i.e. the number of MTJ cell layers is 3, and the stacked three-dimensional structure is shown in fig. 7.
And S6, etching a channel between each column of MTJ units in the three-dimensional structure, wherein the bottom of the etched channel reaches the substrate.
As shown in fig. 8, in the three-dimensional structure of this embodiment, a plurality of MTJ cells aligned up and down are used as a column, and channels can be etched between MTJ cells in each column through a preset mesh pattern mask.
The bottom of the etched channel reaches the substrate and is used for manufacturing a later-stage selective switch tube.
As shown in the embodiment of FIG. 8, this step finally etches MTJ cylinders with feature sizes of 60-80 nm, each cylinder comprising three MTJ cells.
And S7, etching the oxide corresponding to each MTJ unit along the side wall of the channel by wet etching according to a first preset depth.
The purpose of this step is to pull back the oxide corresponding to the MTJ, as shown in fig. 9, and etch inwards along the sidewall of the trench according to the first preset depth (500-800A) of the design, so as to facilitate the polysilicon poly filling in the subsequent step, for manufacturing the gate of the select switch tube. In this embodiment, the oxide is etched by wet etching, and the chemical etching solution only has an etching effect on the oxide, so that the SIN is not consumed.
And S8, backfilling the channel and the etched oxide part by using polysilicon, and re-etching the channel, wherein the bottom of the etched channel reaches the upper part of the substrate.
In this step, as shown in fig. 10 and 11, the oxide portion and the trench etched in step S7 are backfilled with polysilicon, then polysilicon in the trench portion is removed, and TaN in the first electrode layer corresponding to the trench is etched to directly reach the substrate.
And S9, etching the polysilicon corresponding to each MTJ unit along the side wall of the channel according to a second preset depth.
As shown in fig. 12, polysilicon corresponding to each MTJ cell is etched along the sidewall of the trench according to a second preset depth (100-300A), so that a portion of polysilicon (400-700A) remains between the two MTJ protective layers, and is used as the gate of the subsequent select switch tube.
And S10, oxide deposition is carried out in the channel, and the deposited oxide is etched away along the side wall of the channel.
As shown in fig. 13 and 14, oxide deposition is performed in the trench, and then the excess oxide is etched away, so that the polysilicon etched away in step S9 is partially filled with oxide as part of the selective switch.
And S11, performing substrate ion implantation and epitaxy in the channel, etching the isolation groove, filling the isolation groove with an insulating material, and finally performing ion implantation to finish preparation.
As shown in fig. 15, substrate ion implantation and epitaxy are performed in the channel, wherein n+ ion implantation is performed in the substrate to form the source of the selection switch tube, and Si epitaxy is performed to fill the channel.
As shown in FIG. 16, an isolation trench is etched in the trench, the isolation trench being a middle portion of the trench, isolating the MTJ on both sides, and the isolation trench is filled with an insulating material such as SiO 2 (alternatively SIN or organic SOG, SOC, etc.).
And finally, performing N+ ion implantation on the upper part of the epitaxial silicon to form the drain electrode of the selective switch tube.
The embodiment is suitable for manufacturing the magnetic random access memory shown in fig. 17, and T1, T2 and T3 in fig. 17 are selection switch tubes corresponding to the MTJs. Only MTJ1, MTJ2, and MTJ3 are shown in the fabrication process illustration of the embodiment (as shown in fig. 16), with MTJ1, MTJ2, and MTJ3 aligned vertically. If the lateral direction is taken as the X-axis and the vertical column is taken as the Z-axis, then MTJ4, MTJ5, and MTJ6 in FIG. 17 are fabricated in the Y-axis direction. The right portion of fig. 16 can be considered as another set of MTJs, so that a large capacity magnetic random access memory can be fabricated in a limited area, and will not be described again.
It should be noted that, for word lines, bit lines, etc. of the mram, the word lines, the bit lines, etc. may be fabricated by conventional methods in the art, and will not be described herein. Meanwhile, the manufacturing processes such as photolithography, etching, deposition, CMP and the like adopted in the technical scheme of the embodiment have a great number of alternative technical schemes in the prior art, and are not described herein again.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting it, and those skilled in the art will be able to make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, but these corresponding changes and modifications should fall within the protection scope of the appended claims.

Claims (9)

1. The manufacturing method of the magnetic random access memory with the three-dimensional structure is characterized by comprising the following steps of:
step 1, depositing a first electrode layer on a substrate;
step 2, generating a first layer of MTJ (magnetic tunnel junction) unit on the first electrode layer through photoetching and etching;
step 3, performing oxide deposition and chemical mechanical polishing on the first layer of MTJ unit, and depositing a protective layer;
step 4, etching the protection layer corresponding to the first layer of MTJ unit, and depositing a second electrode layer on the protection layer and the first layer of MTJ unit;
step 5, stacking on the second electrode layer by adopting the method from step 2 to step 4 according to the preset number of MTJ (magnetic tunnel junction) unit layers to form a three-dimensional structure;
step 6, etching a channel between each column of MTJ units in the three-dimensional structure, wherein the bottom of the etched channel reaches the substrate;
step 7, etching oxide of a first preset depth of each MTJ unit inwards along the side wall of the channel through wet etching;
step 8, backfilling the channel and the etched oxide part by using polysilicon, and re-etching the channel, wherein the bottom of the etched channel reaches the upper part of the substrate;
step 9, etching polysilicon of a second preset depth of each MTJ unit inwards along the side wall of the channel;
step 10, oxide deposition is carried out in the channel, and the deposited oxide is etched away along the side wall of the channel;
and 11, performing substrate ion implantation and epitaxy in the channel, etching the isolation groove, filling the isolation groove with an insulating material, and finally performing ion implantation to finish preparation.
2. The method of claim 1, wherein Ni is further deposited between the substrate and the first electrode layer.
3. The method for manufacturing the three-dimensional magnetic random access memory according to claim 2, wherein the thickness of the Ni deposit is
Figure FDA0004051118950000011
4. The method for fabricating the magnetic random access memory of the three-dimensional structure according to claim 1, wherein the forming the MTJ cell of the first layer by photolithography and etching on the first electrode layer further comprises:
and depositing a protective layer around the etched MTJ cylinder on the first electrode layer.
5. The method of claim 4, wherein the passivation layer deposited around the MTJ cylinder is silicon nitride with a thickness of
Figure FDA0004051118950000021
6. The method of claim 1, wherein the oxide deposited on the MTJ cell has a thickness of
Figure FDA0004051118950000022
The thickness of the protective layer is->
Figure FDA0004051118950000023
7. The method of claim 1, wherein the first predetermined depth is
Figure FDA0004051118950000024
8. The method of claim 1, wherein the second predetermined depth is
Figure FDA0004051118950000025
9. The method for manufacturing a three-dimensional magnetic random access memory according to claim 1, wherein the isolation groove is filled with an insulating material, and the insulating material is SiO 2 。
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