CN113948631A - Preparation method of storage bit and preparation method of MRAM - Google Patents

Preparation method of storage bit and preparation method of MRAM Download PDF

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Publication number
CN113948631A
CN113948631A CN202010700145.8A CN202010700145A CN113948631A CN 113948631 A CN113948631 A CN 113948631A CN 202010700145 A CN202010700145 A CN 202010700145A CN 113948631 A CN113948631 A CN 113948631A
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layer
tunnel junction
material layer
etching
sacrificial
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刘波
李辉辉
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Hikstor Technology Co Ltd
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Hikstor Technology Co Ltd
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Priority to CN202010700145.8A priority Critical patent/CN113948631A/en
Priority to PCT/CN2020/123277 priority patent/WO2022011878A1/en
Publication of CN113948631A publication Critical patent/CN113948631A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Abstract

The invention provides a preparation method of a storage bit and a preparation method of an MRAM. The preparation method comprises the following steps: providing a first substrate with a first surface, wherein a first tunnel junction material layer and a first mask layer are arranged on the first surface, and the first mask layer is positioned on one side, far away from the first substrate, of the first tunnel junction material layer; etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer, wherein the second tunnel junction material layer is provided with a naked first side wall; forming a sacrificial layer on the first surface, wherein at least part of the sacrificial layer covers the first side wall; and etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction on the second tunnel junction material layer. The etching process of the magnetic tunnel junction is divided into two times, so that short circuit caused by side wall metal deposition in the etching process of the magnetic tunnel junction is avoided, and meanwhile, the magnetoelectric performance of the magnetic tunnel junction is improved.

Description

Preparation method of storage bit and preparation method of MRAM
Technical Field
The invention relates to the field of semiconductor memory chip manufacturing, in particular to a preparation method of a memory bit and a preparation method of an MRAM.
Background
The Magnetic Random Access Memory (MRAM) uses a Magnetic Tunnel Junction (MTJ) as an information storage bit, records information 0 and 1 by using the high and low states of the TMR resistance value, has excellent properties of fast read-write speed, non-volatility, radiation resistance and the like, and is a next-generation non-volatile storage technology with great potential. However, the integration technology of the MRAM fabrication process faces a number of difficulties:
1) the etching difficulty of the MTJ is high, in order to avoid damaging the electromagnetic performance of the MTJ by RIE chemical corrosion, the MTJ is etched by adopting an IBE method generally, and the IBE etching brings serious short circuit and magnetic damage along with the phenomena of side wall metal deposition and plasma bombardment;
2) the sidewall metal deposition and magnetic damage layer caused by IBE are generally removed by adding an over-etching method, and the excessive over-etching depth can affect the bottom electrode and the bottom through hole and reduce or damage the performance of the bottom electrode and the bottom through hole; moreover, the IBE over-etching depth is large (generally about 30% of the main etching amount), and in order to avoid the influence on the metal connection (metal leakage, diffusion, etc.), the height of the via under the MTJ bit is usually increased, and this method will occupy a large amount of space between metal layers, which is not favorable for the application in the embedded memory.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a storage bit and a preparation method of an MRAM (magnetic random access memory), so as to solve the problem of short circuit caused by side wall metal deposition caused by etching of a magnetic tunnel junction in the prior art.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for manufacturing a memory bit cell, including the steps of: providing a first substrate with a first surface, wherein a first tunnel junction material layer and a first mask layer are arranged on the first surface, and the first mask layer is positioned on one side, far away from the first substrate, of the first tunnel junction material layer; etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer, wherein the second tunnel junction material layer is provided with a naked first side wall; forming a sacrificial layer on the first surface, wherein at least part of the sacrificial layer covers the first side wall; and etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction on the second tunnel junction material layer.
Further, the first tunnel junction material layer is subjected to IBE etching or RIE etching to form a second tunnel junction material layer.
Further, the first tunnel junction material layer includes a fixed material layer, a barrier material layer and a free material layer which are sequentially stacked along a direction far away from the first surface, and the step of etching the first tunnel junction material layer to form the second tunnel junction material layer includes: etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer comprising a free layer, wherein the first side wall at least comprises an exposed surface of the free layer; or etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer comprising a free layer and a barrier layer, wherein the first side wall at least comprises exposed surfaces of the free layer and the barrier layer; or etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer comprising a free layer, a barrier layer and a fixed layer, wherein the first side wall comprises exposed surfaces of the free layer, the barrier layer and the fixed layer.
Further, the step of forming a sacrificial layer includes: forming a sacrificial preparation layer on the first surface so that the sacrificial preparation layer covers the first mask layer and the second tunnel junction material layer; and etching the sacrificial preparation layer to expose the first mask layer, wherein the remaining sacrificial preparation layer forms a sacrificial layer covering the first side wall, preferably, the sacrificial preparation layer is etched by adopting a self-alignment process, and more preferably, before the step of etching the sacrificial preparation layer by adopting the self-alignment process, the sacrificial preparation layer is subjected to planarization treatment to expose the surface of one side, away from the first substrate, of the first mask layer.
Further, RIE etching is performed on the sacrificial preparation layer to expose the first mask layer.
Further, the material forming the sacrificial layer is an insulator, and preferably, the material forming the sacrificial layer is selected from any one or more of silicon oxide, silicon nitride, and silicon carbide.
Further, the second tunnel junction material layer is etched by a self-alignment process to form a magnetic tunnel junction.
Further, in the step of etching the second tunnel junction material layer and the sacrificial layer, the adopted etching process has a first etching rate to the first sidewall and a second etching rate in a direction perpendicular to the first surface, and the first etching rate is greater than the second etching rate.
Further, the first substrate includes a connection metal layer and a bottom electrode which are stacked, a surface of a side of the bottom electrode away from the connection metal layer is a part of the first surface, and the step of forming the first mask layer includes: sequentially forming a first tunnel junction material layer, a first mask material layer and a second mask material layer on the first surface so that the first tunnel junction material layer covers the bottom electrode; patterning the second mask material layer to form a second mask layer; and etching the first mask material layer through the second mask layer to form a first mask layer.
Further, after the step of forming the magnetic tunnel junction, the first mask layer is a top electrode layer, and the preparation method further comprises the following steps: forming a protective film covering the magnetic tunnel junction and the top electrode on the first surface; conductive paths connected to the top electrodes are formed in the protective film.
According to another aspect of the present invention, there is provided a method for fabricating an MRAM, including a step of forming at least one memory bit, the memory bit being formed by the above-mentioned fabrication method.
After the technical scheme of the invention is applied, the preparation method of the storage bit is provided, the preparation method comprises the steps of providing a first substrate with a first tunnel junction material layer and a first mask layer on a first surface, etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer, enabling the second tunnel junction material layer to have an exposed first side wall, then forming a sacrificial layer on the first surface, at least partially covering the sacrificial layer on the first side wall, etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and enable the second tunnel junction material layer to form a magnetic tunnel junction, dividing the etching process of the magnetic tunnel junction into two steps, obtaining an independent storage bit through etching or enabling the storage bit not to realize complete conductive separation in the first step, and finely modifying the first side wall after introducing the sacrificial layer in the second step, the short circuit caused by the metal deposition on the side wall in the etching process of the magnetic tunnel junction is avoided, and meanwhile, the magnetoelectric performance of the magnetic tunnel junction is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view illustrating a substrate after a first tunnel junction material layer, a first mask material layer, a second mask material layer and a patterned photoresist are sequentially formed on a first substrate in a method for manufacturing a memory bit cell according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of the substrate after a second mask layer is formed on the second mask material layer shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of the substrate after a first mask layer is formed on the first mask material layer shown in FIG. 2;
FIG. 4 is a schematic cross-sectional view of the substrate after etching the first tunnel junction material layer shown in FIG. 3 to form a second tunnel junction material layer, wherein the second tunnel junction material layer includes a free layer;
FIG. 5 is a cross-sectional view of the substrate after etching the first tunnel junction material layer of FIG. 3 to form a second tunnel junction material layer, wherein the second tunnel junction material layer comprises a free layer and a barrier layer;
FIG. 6 is a schematic cross-sectional view of the substrate after etching the first tunnel junction material layer shown in FIG. 3 to form a second tunnel junction material layer, wherein the second tunnel junction material layer comprises a free layer, a barrier layer and a fixed layer;
FIG. 7 is a cross-sectional view of the substrate after forming a sacrificial layer covering the first sidewall shown in FIG. 6;
FIG. 8 is a cross-sectional view of a substrate after planarization of the sacrificial layer of FIG. 7;
FIG. 9 is a schematic cross-sectional view of the substrate after etching the sacrificial layer of FIG. 8 by a self-aligned process;
FIG. 10 is a cross-sectional view of the substrate after etching the second tunnel junction material layer and the sacrificial layer of FIG. 9 to form a magnetic tunnel junction;
FIG. 11 is a schematic cross-sectional view of the substrate after forming a protective film covering the magnetic tunnel junction and the top electrode shown in FIG. 9;
FIG. 12 is a schematic cross-sectional view of the substrate after forming an interlayer dielectric layer covering the protective film shown in FIG. 10;
fig. 13 is a schematic cross-sectional view of the substrate after forming a conductive via connected to the top electrode in the protective film shown in fig. 12.
Wherein the figures include the following reference numerals:
100. an insulating dielectric layer; 10. connecting the metal layers; 20. a bottom electrode; 30. a magnetic tunnel junction; 301. a first tunnel junction material layer; 302. a second tunnel junction material layer; 310. a fixed layer; 311. a layer of securing material; 320. a barrier layer; 321. a layer of barrier material; 330. a free layer; 331. a free material layer; 40. a first mask layer; 410. a first masking material layer; 50. a second mask layer; 510. a second masking material layer; 60. patterning the photoresist; 70. a sacrificial layer; 710. a sacrificial preparation layer; 80. a protective film; 90. an interlayer dielectric layer; 110. a conductive path.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background section, the prior art magnetic tunnel junction etch is prone to short-circuiting the sidewall metal deposition. In order to solve the above technical problems, the present applicant provides a method for preparing a storage bit, comprising the following steps: providing a first substrate with a first surface, wherein a first tunnel junction material layer and a first mask layer are arranged on the first surface, the first mask layer is positioned on one side, away from the first substrate, of the first tunnel junction material layer, the first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer, and the second tunnel junction material layer is provided with an exposed first side wall; forming a sacrificial layer on the first surface, wherein at least part of the sacrificial layer covers the first side wall; and etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction on the second tunnel junction material layer.
By adopting the preparation method, the etching process of the magnetic tunnel junction is divided into two steps, the first step is mainly to obtain an independent storage bit element through etching or ensure that the storage bit element does not realize complete conductive separation, and the second step is to finely modify the first side wall after introducing the sacrificial layer, so that short circuit caused by metal deposition on the side wall in the etching process of the magnetic tunnel junction is avoided, and the magnetoelectric performance of the magnetic tunnel junction is improved.
An exemplary embodiment of a method for manufacturing a memory bit according to the present invention will be described in more detail with reference to fig. 1 to 13. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a first substrate having a first surface is provided, a first tunnel junction material layer 301 and a first mask layer 40 are disposed on the first surface, and the first mask layer 40 is located on a side of the first tunnel junction material layer 301 away from the first substrate.
In a preferred embodiment, the first substrate includes a connection metal layer 10 and a bottom electrode 20 stacked, a surface of the bottom electrode 20 away from the connection metal layer 10 is a portion of a first surface, and a first tunnel junction material layer 301 covers the surface of the bottom electrode 20, as shown in fig. 1. The bottom electrode 20 may be formed on the surface of the connection metal layer 10 in the insulating dielectric layer 100, and those skilled in the art may reasonably select the materials for forming the connection metal layer 10 and the bottom electrode 20 according to the prior art, which is not described herein again.
The above preparation method of the present invention further includes a step of sequentially forming a first tunnel junction material layer 301 and a first mask layer 40 on the first surface of the first substrate, and the step of forming the first tunnel junction material layer 301 may include: a layer of pinned material 311, a layer of barrier material 321 and a layer of free material 331 are deposited in sequence on the first surface, as shown in fig. 1, resulting in a magnetic tunnel junction 30 comprising a reference layer, a barrier layer 320 and a free layer 330 after etching, see fig. 8.
The free material layer 331 is used to form the free layer 330 after etching, the fixed material layer 311 may include a magnetic metal such as cofeb and the like, and the barrier material layer 321 may be a dielectric material such as mgo or alumina, by which data is stored in the spin direction of the free layer 330.
It should be noted that the structure of the first tunnel junction material layer 301 is different according to the kind of the magnetic tunnel junction 30 to be formed, and the magnetic tunnel junction 30 may include, but is not limited to, an in-plane MTJ, a perpendicular MTJ, a top pinned MTJ, a bottom pinned MTJ, a dual-layer MgO MTJ, a single-layer MgO MTJ, and a multi-state MTJ, in which case the barrier layer 320 in the magnetic tunnel junction 30 may be made to be the first barrier layer, and functional layers such as a second barrier layer, a pinning layer, a capping layer, and a buffer layer may be added.
In a preferred embodiment, the step of forming the first mask layer 40 includes: sequentially forming a first mask material layer 410 and a second mask material layer 510 on the first tunnel junction material layer 301, covering a photoresist on the second mask material layer 510, patterning the photoresist through a photolithography and development process, and etching the second mask material layer 510 by using the patterned photoresist 60 as a mask to obtain a second mask layer 50 having a pattern identical to that of the patterned photoresist 60, as shown in fig. 1 and 2; the first masking material layer 410 is then etched through the second masking layer 50 to transfer the pattern of the patterned photoresist 60 to obtain the first masking layer 40, as shown in fig. 3.
In the above preferred embodiment, the first mask layer 40 can be used as a top electrode of the memory bit after the etching process for forming the magnetic tunnel junction 30, and those skilled in the art can reasonably select the materials of the first mask layer 40 and the second mask layer 50 according to the prior art, for example, the material for forming the first mask layer 40 can be Ta, TaN, TiN, etc., and the material for forming the second mask layer 50 can be SiOx，SiNxAnd the like.
The skilled person can also reasonably set the process conditions of the above-mentioned photolithography process according to the prior art, and the photoresist can select different structures, such as PR/ARC/LTO/SOC and PR/ARC, according to the thicknesses of the first mask layer 40 and the second mask layer 50 and the light source of the photolithography machine, and when the photoresist is etched, the etching is performed in a layer-by-layer transfer manner, that is, PR is etched on ARC, ARC is etched on LTO, and LTO is etched on SOC.
Then, the first tunnel junction material layer 301 is etched by the first mask layer 40 to form a second tunnel junction material layer 302, wherein the second tunnel junction material layer 302 has a first sidewall exposed, as shown in fig. 4 to 6. The etching process may be an IBE etch or an RIE etch.
In a first alternative embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes: the first tunnel junction material layer 301 is etched through the first mask layer 40 to form a second tunnel junction material layer 302 including the free layer 330, and the first sidewall includes at least the exposed surface of the free layer 330, as shown in fig. 4.
In the above alternative embodiment, the barrier material layer 321 may be further etched by etching the first tunnel junction material layer 301 to form the free material layer 331 into the free layer 330, but at this time, the barrier layer 320 is not formed on the barrier material layer 321, and the fixed material layer 311 is not etched, so that the fixed layer 310 is not formed, so that the second tunnel junction material layer 302 is formed to have a plurality of unformed magnetic tunnel junctions and is connected through the barrier material layer 321, and complete conductive separation is not achieved.
In a second alternative embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes: the first tunnel junction material layer 301 is etched through the first mask layer 40 to form a second tunnel junction material layer 302 including the free layer 330 and the barrier layer 320, and the first sidewall includes at least exposed surfaces of the free layer 330 and the barrier layer 320, as shown in fig. 5 to 6.
In the above alternative embodiment, the fixed material layer 311 may be further etched by etching the first tunnel junction material layer 301 to form the free material layer 331 into the free layer 330 and the barrier material layer 321 into the barrier layer 320, but at this time, the fixed material layer 311 still does not form the fixed layer 310, and the second tunnel junction material layer 302 is formed to have a plurality of unformed magnetic tunnel junctions and is connected through the fixed material layer 311 without achieving complete conductive separation.
In a third alternative embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes: the first tunnel junction material layer 301 is etched through the first mask layer 40 to form a second tunnel junction material layer 302 including the free layer 330, the barrier layer 320, and the fixed layer 310, and the first sidewall includes exposed surfaces of the free layer 330, the barrier layer 320, and the fixed layer 310, as shown in fig. 6.
In the above alternative embodiment, by etching the first tunnel junction material layer 301 to form the free layer 330 from the free material layer 331, the barrier layer 320 from the barrier material layer 321, and the fixed layer 310 from the fixed material layer 311, the second tunnel junction material layer 302 including the free layer 330, the barrier layer 320, and the fixed layer 310 can be formed in independent plural numbers and complete conductive separation can be achieved, but with impurities remaining from etching on the first sidewall thereof.
In order to remove the impurities remaining on the first sidewall, after the step of forming the second tunnel junction material layer 302 by etching, a sacrificial layer 70 is formed on the first surface, the sacrificial layer 70 at least partially covers the first sidewall, as shown in fig. 7 to 9, and then the second tunnel junction material layer 302 and the sacrificial layer 70 are etched by the first mask layer 40 to remove the sacrificial layer 70 and form the second tunnel junction material layer 302 into a magnetic tunnel junction, as shown in fig. 10.
The sacrificial layer 70 is non-conductive and non-magnetic, preferably, the material forming the sacrificial layer 70 may be selected from any one or more of silicon oxide, silicon nitride and silicon carbide, and the step of forming the sacrificial layer 70 may include: forming a sacrificial preparation layer 710 on the first surface such that the sacrificial preparation layer 710 covers the first mask layer 40 and the second tunnel junction material layer 302, as shown in fig. 7; the sacrificial preparation layer 710 is etched to expose the first mask layer 40, and the remaining sacrificial preparation layer 710 forms the sacrificial layer 70 covering the first sidewall, as shown in fig. 8 and 9.
In the step of forming the sacrificial layer 70, the sacrificial preparation layer 710 is preferably etched by RIE, and the etching process can obtain a better selectivity ratio, so that the etching rate of the sacrificial preparation layer 710 is greater than the etching rate of the second tunnel junction material layer 302 and the first mask layer 40.
In a preferred embodiment, the sacrificial preparation layer 710 is directly etched by a self-aligned process, so that the remaining sacrificial preparation layer 710 forms the sacrificial layer 70 covering the first sidewall, as shown in fig. 9.
In another preferred embodiment, the sacrificial preparation layer 710 is planarized to expose a surface of the first mask layer 40 away from the first substrate, and then the sacrificial preparation layer 710 is directly etched by using a self-aligned process, so that the remaining sacrificial preparation layer 710 forms the sacrificial layer 70 covering the first sidewall, as shown in fig. 8 and 9.
After the sacrificial layer 70 covering the first sidewall is formed, the second tunnel junction material layer 302 and the sacrificial layer 70 are etched to form the magnetic tunnel junction 30 formed by the second tunnel junction material layer 302, and the sacrificial layer 70 is removed to perform a modified etching on the magnetic tunnel junction 30, so that impurities such as metal remaining on the first sidewall can be taken away, as shown in fig. 10.
In the above process of forming the second tunnel junction material layer 302 into the magnetic tunnel junction 30, the second tunnel junction material layer 302 may be etched by using a self-aligned process to form the above magnetic tunnel junction 30, and the etching time and the etching end point may be determined according to the degree of sidewall deposition or magnetic damage. When the second tunnel junction material layer 302 does not achieve complete conductive separation, the overgrowth during etching of the second tunnel junction material layer 302 is required to ensure a sufficient amount of over-etching to achieve conductive separation between the magnetic tunnel junctions 30.
In the step of etching the second tunnel junction material layer 302 and the sacrificial layer 70, an etching process is preferably used, which has a first etching rate for the first sidewall and a second etching rate in a direction perpendicular to the first surface, and the first etching rate is greater than the second etching rate.
After the step of forming the magnetic tunnel junction 30, the first mask layer 40 may be used as a top electrode layer of the memory bit, and the method of the present invention may further include the following steps: forming a protective film 80 covering the magnetic tunnel junction 30 and the top electrode on the first surface, as shown in fig. 11; conductive paths 110 connected to the top electrodes are formed in the protective film 80, as shown in fig. 12 and 13.
Specifically, by etching the second tunnel junction material layer 302 to form a plurality of magnetic tunnel junctions 30 on the first surface of the first substrate, after the step of forming the protective film 80 covering the magnetic tunnel junctions 30 and the top electrode, an interlayer dielectric layer 90 covering the protective film 80 may be formed on the first surface, then a conductive via penetrating to the top electrode is formed in the interlayer dielectric layer 90 and the protective film 80, and then a conductive material is deposited in the conductive via to form the conductive via 110; before the step of forming the conductive via, the interlayer dielectric layer 90 may be subjected to a planarization process, such as CMP polishing, and the polishing stop may be located above the magnetic tunnel junction 30 or just flush with the surface of the magnetic tunnel junction 30.
The protective film 80 is non-conductive and non-magnetic, and preferably, the material forming the protective film 80 is selected from any one or more of silicon oxide, silicon nitride, tantalum nitride, silicon carbonitride, silicon oxynitride and aluminum oxide, but is not limited to the above preferred species, and the specific species can be reasonably selected by those skilled in the art according to the prior art; the material of the interlayer dielectric layer 90 may be silicon oxide, silicon nitride, silicon carbide, low K material, etc.
The skilled person can also reasonably select the deposition process for forming the protective film 80 and the interlayer dielectric layer 90 according to the prior art, for example, chemical vapor deposition or atomic layer deposition is adopted; and, the conductive through holes can be formed by adopting a dual damascene etching process.
According to another aspect of the present invention, there is also provided a method for fabricating an MRAM, including the step of forming at least one memory bit, the memory bit being formed by the above-described fabrication method.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
by adopting the preparation method, the etching process of the magnetic tunnel junction is divided into two steps, the first step is mainly to obtain an independent storage bit element through etching or ensure that the storage bit element does not realize complete conductive separation, and the second step is to finely modify the first side wall after introducing the sacrificial layer, so that short circuit caused by metal deposition on the side wall in the etching process of the magnetic tunnel junction is avoided, and the magnetoelectric performance of the magnetic tunnel junction is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A method for preparing a memory bit cell, comprising the steps of:
providing a first substrate with a first surface, wherein a first tunnel junction material layer and a first mask layer are arranged on the first surface, and the first mask layer is positioned on one side, far away from the first substrate, of the first tunnel junction material layer;
etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer, wherein the second tunnel junction material layer is provided with a naked first side wall;
forming a sacrificial layer on the first surface, wherein the sacrificial layer at least partially covers the first side wall;
and etching the second tunnel junction material layer and the sacrificial layer through the first mask layer to remove the sacrificial layer and form a magnetic tunnel junction on the second tunnel junction material layer.
2. The method of claim 1, wherein the first tunnel junction material layer is subjected to IBE etching or RIE etching to form the second tunnel junction material layer.
3. The method according to claim 1, wherein the first tunnel junction material layer includes a fixed material layer, a barrier material layer, and a free material layer sequentially stacked in a direction away from the first surface, and the step of etching the first tunnel junction material layer to form the second tunnel junction material layer includes:
etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer comprising a free layer, wherein the first side wall at least comprises an exposed surface of the free layer; or
Etching the first tunnel junction material layer through the first mask layer to form the second tunnel junction material layer including a free layer and a barrier layer, the first sidewall including at least exposed surfaces of the free layer and the barrier layer; or
Etching the first tunnel junction material layer through the first mask layer to form the second tunnel junction material layer including a free layer, a barrier layer, and a fixed layer, the first sidewall including exposed surfaces of the free layer, the barrier layer, and the fixed layer.
4. The production method according to claim 1, wherein the step of forming the sacrificial layer includes:
forming a sacrificial preparation layer on the first surface so that the sacrificial preparation layer covers the first mask layer and the second tunnel junction material layer;
etching the sacrificial preparation layer to expose the first mask layer, wherein the residual sacrificial preparation layer forms the sacrificial layer covering the first side wall,
preferably, the sacrificial preparation layer is etched using a self-aligned process,
more preferably, before the step of etching the sacrificial preparation layer by using a self-aligned process, the sacrificial preparation layer is subjected to planarization treatment, so that a surface of one side, away from the first substrate, of the first mask layer is exposed.
5. The method according to claim 4, wherein the sacrificial preparation layer is RIE etched to expose the first mask layer.
6. The production method according to any one of claims 1 to 5, wherein a material forming the sacrificial layer is an insulator, and preferably, the material forming the sacrificial layer is selected from any one or more of silicon oxide, silicon nitride, and silicon carbide.
7. The method of any one of claims 1 to 5, wherein the second tunnel junction material layer is etched using a self-aligned process to form the magnetic tunnel junction.
8. The method according to any one of claims 1 to 5, wherein in the step of etching the second tunnel junction material layer and the sacrificial layer, an etching process is used that has a first etching rate for the first sidewall and a second etching rate in a direction perpendicular to the first surface, and the first etching rate is greater than the second etching rate.
9. The production method according to any one of claims 1 to 5, wherein the first substrate includes a connection metal layer and a bottom electrode stacked, a surface of the bottom electrode on a side away from the connection metal layer is a part of the first surface, and the step of forming the first mask layer includes:
sequentially forming the first tunnel junction material layer, a first mask material layer and a second mask material layer on the first surface so that the first tunnel junction material layer covers the bottom electrode;
patterning the second mask material layer to form a second mask layer;
and etching the first mask material layer through the second mask layer to form the first mask layer.
10. The method of manufacturing of any of claims 1 to 5, wherein the first mask layer is a top electrode layer after the step of forming the magnetic tunnel junction, the method further comprising the steps of:
forming a protective film on the first surface covering the magnetic tunnel junction and the top electrode;
forming a conductive path in the protective film to be connected to the top electrode.
11. A method of fabricating an MRAM comprising the step of forming at least one memory bit, wherein the memory bit is formed using the method of any of claims 1 to 10.
CN202010700145.8A 2020-07-17 2020-07-17 Preparation method of storage bit and preparation method of MRAM Pending CN113948631A (en)

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