WO2022011878A1

WO2022011878A1 - Memory bit preparation method and mram preparation method

Info

Publication number: WO2022011878A1
Application number: PCT/CN2020/123277
Authority: WO
Inventors: 刘波; 李辉辉
Original assignee: 浙江驰拓科技有限公司
Priority date: 2020-07-17
Filing date: 2020-10-23
Publication date: 2022-01-20
Also published as: CN113948631A

Abstract

Provided are a memory bit preparation method and an MRAM preparation method. The memory bit preparation method comprises the following steps: providing a first substrate having a first surface, wherein a first tunnel junction material layer and a first mask layer are arranged on the first surface, and the first mask layer is located on the side of the first tunnel junction material layer that is away from the first substrate; etching the first tunnel junction material layer by means of the first mask layer to form a second tunnel junction material layer, wherein the second tunnel junction material layer has an exposed first side wall; forming a sacrificial layer on the first surface, wherein the sacrificial layer at least partially covers the first side wall; and etching the second tunnel junction material layer and the sacrificial layer by means of the first mask layer, so as to remove the sacrificial layer and form the second tunnel junction material layer into a magnetic tunnel junction. An etching process of a magnetic tunnel junction is divided into two instances in which same is carried out, such that a short circuit brought about by metal deposition on a side wall during the etching process of the magnetic tunnel junction is prevented, and the magnetoelectric performance of the magnetic tunnel junction is also improved.

Description

Preparation method of storage bit and preparation method of MRAM

The present disclosure takes the patent document filed on July 17, 2020 with the application number of 202010700145.8 and titled "Method for preparing storage bits and method for preparing MRAM" as a priority document, the entire contents of which are incorporated into this disclosure by reference .

technical field

The present disclosure relates to the field of semiconductor memory chip manufacturing, and in particular, to a method for preparing storage bits and a method for preparing MRAM.

Background technique

Magnetic random access memory (MRAM) uses a magnetic tunnel junction (MTJ) as an information storage bit, and uses the high and low states of its TMR resistance to record information 0 and 1. It has excellent properties such as fast read and write speed, non-volatile, and radiation resistance. It is the next-generation non-volatile storage technology with great potential. However, the fabrication process integration technology of MRAM faces many difficulties:

1) MTJ etching is difficult. In order to avoid RIE chemical corrosion destroying its electromagnetic properties, MTJ etching generally adopts IBE method. IBE etching is accompanied by sidewall metal deposition and plasma bombardment, which will bring serious short circuit and magnetic damage. ;

2) The industry generally removes the sidewall metal deposition and magnetic damage layer caused by IBE by increasing the over-etching method. Excessive over-etching depth will affect the bottom electrode and bottom via, reducing or destroying their performance; and, IBE The depth of over-etching is relatively large (generally about 30% of the main etching amount). In order to avoid affecting the metal connection (metal leakage and diffusion, etc.), the industry usually increases the height of the via hole under the MTJ bit, while This method will occupy a lot of space between metal layers, which is not conducive to its application in embedded memory.

SUMMARY OF THE INVENTION

The main purpose of the present disclosure is to provide a method for preparing storage bits and a method for preparing MRAM, so as to solve the problem of short circuit caused by sidewall metal deposition caused by magnetic tunnel junction etching in the prior art.

In order to achieve the above object, according to an aspect of the present disclosure, there is provided a method for preparing a storage bit cell, comprising the following steps: providing a first substrate having a first surface, on which a first tunnel junction material layer is provided; a first mask layer, the first mask layer is located on the side of the first tunnel junction material layer away from the first substrate; the first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer, and the second tunnel junction material layer is formed. The two tunnel junction material layers have exposed first sidewalls; a sacrificial layer is formed on the first surface, and the sacrificial layer at least partially covers the first sidewalls; the second tunnel junction material layer and the sacrificial layer are etched through the first mask layer layer to remove the sacrificial layer and form the second tunnel junction material layer into a magnetic tunnel junction.

Optionally, IBE etching or RIE etching is performed on the first tunnel junction material layer to form a second tunnel junction material layer.

Optionally, the first tunnel junction material layer includes a fixed material layer, a barrier material layer and a free material layer sequentially stacked in a direction away from the first surface, and the first tunnel junction material layer is etched to form a second tunnel junction material layer The step includes: etching the first tunnel junction material layer through the first mask layer to form a second tunnel junction material layer including a free layer, and the first sidewall at least includes the exposed surface of the free layer; or through the first mask etching the first tunnel junction material layer layer by layer to form a second tunnel junction material layer including a free layer and a barrier layer, and the first sidewall includes at least the exposed surface of the free layer and the barrier layer; or through the first mask layer The first tunnel junction material layer is etched to form a second tunnel junction material layer including a free layer, a barrier layer and a pinned layer, and the first sidewall includes an exposed surface of the free layer, the barrier layer and the pinned layer.

Optionally, the step of forming the sacrificial layer includes: forming a sacrificial preparatory layer on the first surface, so that the sacrificial preparatory layer covers the first mask layer and the second tunnel junction material layer; and etching the sacrificial preparatory layer so that the first The mask layer is exposed, and the remaining sacrificial preparation layer forms a sacrificial layer covering the first sidewall. Preferably, the sacrificial preparation layer is etched by a self-alignment process, and more preferably, the sacrificial preparation layer is etched by a self-alignment process. Before the step of preparing the layer, the sacrificial preparation layer is planarized to expose the surface of the first mask layer on the side away from the first substrate.

Optionally, RIE etching is performed on the sacrificial preparation layer to expose the first mask layer.

Optionally, the material for forming the sacrificial layer is an insulator, and preferably, the material for forming the sacrificial layer is selected from any one or more of silicon oxide, silicon nitride and silicon carbide.

Optionally, a self-aligned process is used to etch the second tunnel junction material layer to form a magnetic tunnel junction.

Optionally, in the step of etching the second tunnel junction material layer and the sacrificial layer, the adopted etching process has a first etching rate for the first sidewall and a second etching rate in a direction perpendicular to the first surface. etching rate, and the first etching rate is greater than the second etching rate.

Optionally, the first base body includes a stacked connection metal layer and a bottom electrode, the surface of the bottom electrode on the side away from the connection metal layer is a part of the first surface, and the step of forming the first mask layer includes: on the first surface forming a first tunnel junction material layer, a first masking material layer and a second masking material layer in sequence so that the first tunneling junction material layer covers the bottom electrode; patterning the second masking material layer to form a second masking material film layer; etching the first mask material layer through the second mask layer to form the first mask layer.

Optionally, after the step of forming the magnetic tunnel junction, the first mask layer is a top electrode layer, and the preparation method further includes the following steps: forming a protective film covering the magnetic tunnel junction and the top electrode on the first surface; A conductive channel connected to the top electrode is formed in it.

According to another aspect of the present disclosure, a method for manufacturing an MRAM is provided, which includes the step of forming at least one storage bit, and the storage bit is formed by using the above-mentioned preparation method.

By applying the technical solutions of the present disclosure, a method for preparing a storage bit is provided. The film layer etches the first tunnel junction material layer to form a second tunnel junction material layer, so that the second tunnel junction material layer has exposed first sidewalls, and then forms a sacrificial layer on the first surface, the sacrificial layer at least partially covers the On the first sidewall, the second tunnel junction material layer and the sacrificial layer are etched through the first mask layer to remove the sacrificial layer and the second tunnel junction material layer to form a magnetic tunnel junction, so that by etching the magnetic tunnel junction The etching process is divided into two steps. The first step is to obtain independent storage bits by etching or the storage bits have not yet achieved complete conductive separation. The second step is to introduce a sacrificial layer and then finely modify the first sidewall. The short circuit caused by sidewall metal deposition during the etching process of the magnetic tunnel junction is avoided, and the magnetoelectric performance of the magnetic tunnel junction is improved at the same time.

Description of drawings

The accompanying drawings that constitute a part of the present disclosure are used to provide further understanding of the present disclosure, and the exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the attached image:

FIG. 1 shows that in the method for preparing a storage bit provided by an embodiment of the present application, a first tunnel junction material layer, a first mask material layer, a second mask material layer and a pattern are sequentially formed on a first substrate Schematic diagram of the cross-sectional structure of the substrate after photoresist treatment;

FIG. 2 is a schematic diagram showing the cross-sectional structure of the substrate after the second mask material layer shown in FIG. 1 is formed into a second mask layer;

FIG. 3 shows a schematic diagram of the cross-sectional structure of the substrate after the first mask material layer shown in FIG. 2 is formed into a first mask layer;

4 shows a schematic cross-sectional structure diagram of the substrate after etching the first tunnel junction material layer shown in FIG. 3 to form a second tunnel junction material layer, wherein the second tunnel junction material layer includes a free layer;

5 shows a schematic cross-sectional structure diagram of the substrate after etching the first tunnel junction material layer shown in FIG. 3 to form a second tunnel junction material layer, wherein the second tunnel junction material layer includes a free layer and a barrier layer;

6 is a schematic diagram showing the cross-sectional structure of the substrate after etching the first tunnel junction material layer shown in FIG. 3 to form a second tunnel junction material layer, wherein the second tunnel junction material layer includes a free layer, a barrier layer and a fixed layer Floor;

FIG. 7 shows a schematic cross-sectional structure diagram of the substrate after forming the sacrificial layer covering the first sidewall shown in FIG. 6;

FIG. 8 is a schematic diagram showing the cross-sectional structure of the substrate after the sacrificial layer shown in FIG. 7 is planarized;

FIG. 9 shows a schematic diagram of the cross-sectional structure of the substrate after the sacrificial layer shown in FIG. 8 is etched by a self-alignment process;

FIG. 10 is a schematic diagram showing the cross-sectional structure of the substrate after etching the second tunnel junction material layer and the sacrificial layer shown in FIG. 9 to form a magnetic tunnel junction;

11 shows a schematic cross-sectional structure diagram of the substrate after forming the protective film covering the magnetic tunnel junction and the top electrode shown in FIG. 9;

FIG. 12 shows a schematic cross-sectional structure diagram of the substrate after forming the interlayer dielectric layer covering the protective film shown in FIG. 10;

FIG. 13 is a schematic diagram showing the cross-sectional structure of the substrate after forming a conductive channel connected to the top electrode in the protective film shown in FIG. 12 .

Wherein, the above-mentioned drawings include the following reference signs:

100, insulating medium layer; 10, connecting metal layer; 20, bottom electrode; 30, magnetic tunnel junction; 301, first tunnel junction material layer; 302, second tunnel junction material layer; 310, fixed layer; 311, fixed material layer; 320, barrier layer; 321, barrier material layer; 330, free layer; 331, free material layer; 40, first mask layer; 410, first mask material layer; 50, second mask layer 510, second mask material layer; 60, patterned photoresist; 70, sacrificial layer; 710, sacrificial preparation layer; 80, protective film; 90, interlayer dielectric layer;

detailed description

It should be noted that the embodiments of the present disclosure and the features of the embodiments may be combined with each other under the condition of no conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

In order to make those skilled in the art better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only Embodiments are part of the present disclosure, but not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

It should be noted that the terms "first", "second" and the like in the description and claims of the present disclosure and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the present disclosure described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

As described in the background art, in the prior art, the etching of the magnetic tunnel junction is likely to lead to a short circuit caused by sidewall metal deposition. In order to solve the above-mentioned technical problems, the applicant of the present disclosure provides a method for preparing a storage bit cell, which includes the following steps: providing a first substrate with a first surface, on which a first tunnel junction material layer and a first substrate are provided. a mask layer, the first mask layer is located on the side of the first tunnel junction material layer away from the first substrate, the first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer, the second The tunnel junction material layer has an exposed first sidewall; a sacrificial layer is formed on the first surface, the sacrificial layer at least partially covers the first sidewall; the second tunnel junction material layer and the sacrificial layer are etched through the first mask layer , to remove the sacrificial layer and form a magnetic tunnel junction with the second tunnel junction material layer.

Using the above-mentioned preparation method of the present disclosure, the etching process of the magnetic tunnel junction is divided into two times. The first time is mainly to obtain independent storage bits by etching or the storage bits have not yet achieved complete conductive separation. The first sidewall is finely modified after the sacrificial layer is introduced step by step, so as to avoid short circuit caused by metal deposition on the sidewall during the etching process of the magnetic tunnel junction, and at the same time improve the magnetoelectric performance of the magnetic tunnel junction.

Exemplary embodiments of the method for fabricating storage bits provided according to the present disclosure will be described in more detail below with reference to FIGS. 1 to 13 . These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.

First, a first base body with a first surface is provided, a first tunnel junction material layer 301 and a first mask layer 40 are disposed on the first surface, and the first mask layer 40 is located at the first tunnel junction material layer 301 away from the first side of the base.

In a preferred embodiment, the above-mentioned first substrate includes a laminated connection metal layer 10 and a bottom electrode 20 , the surface of the bottom electrode 20 on the side away from the connection metal layer 10 is a part of the first surface, and the first tunnel junction material The layer 301 covers the surface of the bottom electrode 20 as shown in FIG. 1 . The bottom electrode 20 can be formed on the surface of the connecting metal layer 10 in the insulating dielectric layer 100. Those skilled in the art can reasonably select the materials for forming the connecting metal layer 10 and the bottom electrode 20 according to the prior art. Repeat.

The above-mentioned preparation method of the present disclosure further includes the step of sequentially forming a first tunnel junction material layer 301 and a first mask layer 40 on the first surface of the first substrate, and the step of forming the above-mentioned first tunnel junction material layer 301 may include: A fixed material layer 311, a barrier material layer 321 and a free material layer 331 are sequentially deposited on the first surface, as shown in FIG. 1, and a magnetic tunnel junction including a reference layer, a barrier layer 320 and a free layer 330 is obtained after etching 30, referring to FIG. 8 .

The above-mentioned free material layer 331 is used to form the free layer 330 after etching, and stores data through the spin direction of the free layer 330. The fixed material layer 311 may contain magnetic metals such as cobalt iron boron, and the barrier material layer 321 may be magnesium oxide or Dielectric materials such as alumina.

It should be noted that the structure of the first tunnel junction material layer 301 is also different according to the type of the magnetic tunnel junction 30 to be formed. The above-mentioned magnetic tunnel junction 30 may include but not limited to in-plane MTJ, vertical MTJ, top pin Pinned MTJ, bottom pinned MTJ, double-layer MgO MTJ, single-layer MgO MTJ and multi-state MTJ, at this time, the barrier layer 320 in the magnetic tunnel junction 30 can be the first barrier layer, and the second barrier layer can be added , pinning layer, cover layer and buffer layer and other functional layers.

In a preferred embodiment, the step of forming the first mask layer 40 includes: sequentially forming a first mask material layer 410 and a second mask material layer 510 on the first tunnel junction material layer 301 , and forming the first mask material layer 410 and the second mask material layer 510 on the first tunnel junction material layer 301 The second mask material layer 510 is covered with photoresist, and the photoresist is patterned through photolithography and developing processes, and the second mask material layer 510 is etched by using the patterned photoresist 60 as a mask to obtain The second mask layer 50 with the pattern consistent with the patterned photoresist 60, as shown in FIG. 1 and FIG. 2; then the first mask material layer 410 is etched through the second mask layer 50 to The pattern of the photoresist 60 is transferred to obtain the first mask layer 40 , as shown in FIG. 3 .

In the above-mentioned preferred embodiment, the first mask layer 40 can be used as the top electrode of the storage bit cell after the etching process for forming the magnetic tunnel junction 30. Those skilled in the art can apply the above-mentioned first mask layer according to the prior art. 40 and the materials of the second mask layer 50 are reasonably selected. For example, the materials forming the first mask layer 40 can be Ta, TaN, TiN, etc., and the materials forming the second mask layer 50 can be SiO _x , SiN _x etc.

Those skilled in the art can also reasonably set the process conditions of the above lithography process according to the prior art, and the photoresist can be selected according to the thickness of the first mask layer 40 and the second mask layer 50 and the light source of the lithography machine Use different structures, such as PR/ARC/LTO/SOC and PR/ARC structures, when performing photoresist etching, use layer-by-layer transfer for etching, that is, PR etching ARC, ARC etching LTO, LTO etching SOC.

Then, the first tunnel junction material layer 301 is etched through the first mask layer 40 to form a second tunnel junction material layer 302 , and the second tunnel junction material layer 302 has an exposed first sidewall, as shown in FIGS. 4 to 6 . Show. The above etching process may be IBE etching or RIE etching.

In a first optional embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes: etching the first tunnel junction material layer 301 through the first mask layer 40, To form the second tunnel junction material layer 302 including the free layer 330 , the first sidewall includes at least the exposed surface of the free layer 330 , as shown in FIG. 4 .

In the above-mentioned optional embodiment, by etching the first tunnel junction material layer 301 to form the free material layer 331 into the free layer 330, the barrier material layer 321 may be further etched, but at this time the barrier material layer 321, the barrier layer 320 has not yet been formed, and the fixed material layer 311 has not been etched, so that the fixed layer 310 has not been formed, so that the formed second tunnel junction material layer 302 has a plurality of magnetic tunnel junctions that have not yet been formed. The barrier material layer 321 is connected without achieving complete conductive separation.

In a second optional embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes: etching the first tunnel junction material layer 301 through the first mask layer 40, To form the second tunnel junction material layer 302 including the free layer 330 and the barrier layer 320 , the first sidewall includes at least the exposed surface of the free layer 330 and the barrier layer 320 , as shown in FIGS. 5 to 6 .

In the above-mentioned optional embodiment, by etching the first tunnel junction material layer 301, the free material layer 331 is formed into the free layer 330, and the barrier material layer 321 is formed into the barrier layer 320, and the fixed material can be further The layer 311 is etched, but the fixed layer 310 has not yet been formed in the fixed material layer 311 at this time. Similarly, the formed second tunnel junction material layer 302 has a plurality of magnetic tunnel junctions that have not yet been formed, and are connected through the fixed material layer 311. Complete conductive separation is not achieved.

In a third optional embodiment, the step of etching the first tunnel junction material layer 301 to form the second tunnel junction material layer 302 includes: etching the first tunnel junction material layer 301 through the first mask layer 40, To form the second tunnel junction material layer 302 including the free layer 330, the barrier layer 320 and the fixed layer 310, the first sidewall includes the exposed surface of the free layer 330, the barrier layer 320 and the fixed layer 310, as shown in FIG. 6 .

In the above-mentioned optional embodiment, by etching the first tunnel junction material layer 301, the free material layer 331 is formed into the free layer 330, the barrier material layer 321 is formed into the barrier layer 320, and the fixed material layer 311 is formed The fixed layer 310, at this time, the second tunnel junction material layer 302 including the above-mentioned free layer 330, the above-mentioned barrier layer 320 and the above-mentioned fixed layer 310 can be formed into independent multiple layers, and complete conductive separation can be achieved, but the first sidewall of the fixed layer 310 can be formed independently. There are impurities remaining on the etching.

In order to remove the impurities remaining on the above-mentioned first sidewall, after the step of forming the second tunnel junction material layer 302 by etching, a sacrificial layer 70 is formed on the first surface, and the sacrificial layer 70 at least partially covers the first sidewall 7 to 9 , the second tunnel junction material layer 302 and the sacrificial layer 70 are then etched through the first mask layer 40 to remove the sacrificial layer 70 and the second tunnel junction material layer 302 to form a magnetic tunnel junction , as shown in Figure 10.

The above-mentioned sacrificial layer 70 is non-conductive and non-magnetic. Preferably, the material for forming the above-mentioned sacrificial layer 70 can be selected from any one or more of silicon oxide, silicon nitride and silicon carbide, and the steps of forming the above-mentioned sacrificial layer 70 can be Including: forming a sacrificial preparation layer 710 on the first surface, so that the sacrificial preparation layer 710 covers the first mask layer 40 and the second tunnel junction material layer 302, as shown in FIG. 7; and etching the sacrificial preparation layer 710 to make The first mask layer 40 is exposed, and the remaining sacrificial preparation layer 710 forms a sacrificial layer 70 covering the first sidewall, as shown in FIG. 8 and FIG. 9 .

In the above step of forming the sacrificial layer 70, preferably, RIE etching is performed on the sacrificial preparatory layer 710, and the above-mentioned etching process can obtain a better selectivity ratio, so that the etching rate of the sacrificial preparatory layer 710 is higher than that of the first sacrificial preparatory layer 710. The etching rates of the two tunnel junction material layers 302 and the first mask layer 40 .

In a preferred embodiment, the sacrificial preparation layer 710 is directly etched by a self-alignment process, so that the remaining sacrificial preparation layer 710 forms a sacrificial layer 70 covering the first sidewall, as shown in FIG. 9 .

In another preferred embodiment, the sacrificial preparation layer 710 is planarized to expose a surface of the first mask layer 40 away from the first substrate, and then the sacrificial preparation layer is directly etched by a self-alignment process 710 , so that the remaining sacrificial preparation layer 710 forms a sacrificial layer 70 covering the first sidewall, as shown in FIG. 8 and FIG. 9 .

After the above-mentioned sacrificial layer 70 covering the first sidewall is formed, the second tunnel junction material layer 302 and the sacrificial layer 70 are etched to form the second tunnel junction material layer 302 to form the magnetic tunnel junction 30, and the magnetic tunnel junction 30 is formed by removing The sacrificial layer 70 is used to perform modified etching on the magnetic tunnel junction 30, so that impurities such as metal remaining on the first sidewall can be taken away, as shown in FIG. 10 .

In the above-mentioned process of forming the second tunnel junction material layer 302 into the magnetic tunnel junction 30, the second tunnel junction material layer 302 may be etched by a self-aligned process to form the above-mentioned magnetic tunnel junction 30, the etching time and the etching end point It can be determined by the degree of sidewall deposition or magnetic damage. When the above-mentioned second tunnel junction material layer 302 has not yet achieved complete conductive separation, the over-growth of the second tunnel junction material layer 302 needs to ensure a sufficient amount of over-etching to achieve conductive separation between the magnetic tunnel junctions 30 .

In the step of etching the above-mentioned second tunnel junction material layer 302 and the above-mentioned sacrificial layer 70, preferably, the adopted etching process has a first etching rate for the first sidewall and a direction perpendicular to the first surface. a second etching rate, and the first etching rate is greater than the second etching rate.

After the step of forming the magnetic tunnel junction 30, the above-mentioned first mask layer 40 can be used as the top electrode layer of the storage bit cell. At this time, the above-mentioned preparation method of the present disclosure can further include the following steps: forming a covering magnetic layer on the first surface The protective film 80 of the tunnel junction 30 and the top electrode is shown in FIG. 11 ; a conductive channel 110 connected to the top electrode is formed in the protective film 80 , as shown in FIG. 12 and FIG. 13 .

Specifically, by etching the second tunnel junction material layer 302 to form a plurality of magnetic tunnel junctions 30 on the first surface of the first base, after the step of forming the protective film 80 covering the magnetic tunnel junctions 30 and the top electrode, The interlayer dielectric layer 90 covering the protective film 80 may be formed on the first surface first, then conductive vias are formed in the interlayer dielectric layer 90 and the protective film 80 through to the top electrode, and then conductive materials are deposited in the conductive vias to form the above-mentioned conductive channel 110; before the step of forming the above-mentioned conductive through hole, the interlayer dielectric layer 90 can also be planarized, such as CMP polishing, and the polishing stop position can be above the magnetic tunnel junction 30, or it can be just level with the surface of the magnetic tunnel junction 30 .

The above protective film 80 is non-conductive and non-magnetic, preferably, the material for forming the above protective film 80 is selected from any one of silicon oxide, silicon nitride, tantalum nitride, silicon carbonitride, silicon oxynitride and aluminum oxide or Various, but not limited to the above-mentioned preferred types, those skilled in the art can reasonably select their specific types according to the prior art; the material of the above-mentioned interlayer dielectric layer 90 can be silicon oxide, silicon nitride, silicon carbide and low K material, etc.

Those skilled in the art can also reasonably select the process for depositing the above-mentioned protective film 80 and the interlayer dielectric layer 90 according to the prior art, such as chemical vapor deposition or atomic layer deposition; and, can use the double damascene etching process to form the above-mentioned conductive vias.

According to another aspect of the present disclosure, a method for manufacturing an MRAM is also provided, including the step of forming at least one storage bit, where the storage bit is formed by the above-mentioned preparation method.

From the above description, it can be seen that the above-mentioned embodiments of the present disclosure achieve the following technical effects:

The above descriptions are only preferred embodiments of the present disclosure, and are not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

A method for preparing a storage bit, comprising the following steps:

A first base body with a first surface is provided, a first tunnel junction material layer and a first mask layer are disposed on the first surface, and the first mask layer is located away from the first tunnel junction material layer and away from the one side of the first substrate;

The first tunnel junction material layer is etched through the first mask layer to form a second tunnel junction material layer, the second tunnel junction material layer has exposed first sidewalls;

forming a sacrificial layer on the first surface, the sacrificial layer at least partially covering the first sidewall;

The second tunnel junction material layer and the sacrificial layer are etched through the first mask layer to remove the sacrificial layer and form the second tunnel junction material layer into a magnetic tunnel junction.
The preparation method according to claim 1, wherein the first tunnel junction material layer is subjected to IBE etching or RIE etching to form the second tunnel junction material layer.
The preparation method according to claim 1, wherein the first tunnel junction material layer comprises a fixed material layer, a barrier material layer and a free material layer sequentially stacked in a direction away from the first surface, The step of etching the first tunnel junction material layer to form the second tunnel junction material layer includes:

The first tunnel junction material layer is etched through the first mask layer to form the second tunnel junction material layer including a free layer, and the first sidewall includes at least an exposed surface of the free layer; or

The first tunnel junction material layer is etched through the first mask layer to form the second tunnel junction material layer including a free layer and a barrier layer, and the first sidewall includes at least the free layer and the exposed surface of the barrier layer; or

The first tunnel junction material layer is etched through the first mask layer to form the second tunnel junction material layer including a free layer, a barrier layer and a fixed layer, and the first sidewall includes the exposed surfaces of the free layer, the barrier layer and the pinned layer.
The preparation method according to claim 1, wherein the step of forming the sacrificial layer comprises:

forming a sacrificial preparation layer on the first surface so that the sacrificial preparation layer covers the first mask layer and the second tunnel junction material layer;

etching the sacrificial preparation layer to expose the first mask layer, and the remaining sacrificial preparation layer forms the sacrificial layer covering the first sidewall,

Preferably, the sacrificial preparation layer is etched by a self-alignment process,

More preferably, before the step of etching the sacrificial preparatory layer using a self-alignment process, the sacrificial preparatory layer is planarized to keep the first mask layer away from a portion of the first substrate. Side surfaces are exposed.
The preparation method according to claim 4, wherein RIE etching is performed on the sacrificial preparation layer to expose the first mask layer.
The preparation method according to any one of claims 1 to 5, wherein the material for forming the sacrificial layer is an insulator, preferably, the material for forming the sacrificial layer is selected from silicon oxide, silicon nitride and carbide Any one or more of silicon.
The preparation method according to any one of claims 1 to 5, wherein the second tunnel junction material layer is etched by a self-alignment process to form the magnetic tunnel junction.
The preparation method according to any one of claims 1 to 5, characterized in that in the step of etching the second tunnel junction material layer and the sacrificial layer, the etching process used has the A first etching rate of a sidewall and a second etching rate in a direction perpendicular to the first surface, and the first etching rate is greater than the second etching rate.
The preparation method according to any one of claims 1 to 5, wherein the first base body comprises a stacked connection metal layer and a bottom electrode, and a surface of the bottom electrode on a side away from the connection metal layer is As part of the first surface, the step of forming the first mask layer includes:

forming the first tunnel junction material layer, the first mask material layer and the second mask material layer sequentially on the first surface, so that the first tunnel junction material layer covers the bottom electrode;

patterning the second layer of masking material to form a second masking layer;

The first mask material layer is etched through the second mask layer to form the first mask layer.
The preparation method according to any one of claims 1 to 5, wherein after the step of forming the magnetic tunnel junction, the first mask layer is a top electrode layer, and the preparation method further comprises the following steps: step:

forming a protective film covering the magnetic tunnel junction and the top electrode on the first surface;

A conductive channel connected to the top electrode is formed in the protective film.
A preparation method of MRAM, comprising the step of forming at least one storage bit, characterized in that the storage bit is formed by the preparation method according to any one of claims 1 to 10.