CN112670313A

CN112670313A - Semiconductor structure and forming method thereof

Info

Publication number: CN112670313A
Application number: CN201910984109.6A
Authority: CN
Inventors: 金吉松
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-10-16
Filing date: 2019-10-16
Publication date: 2021-04-16

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a storage area and a logic area, the storage area is provided with a first conducting layer, the logic area is provided with a second conducting layer, and the substrate exposes the top surface of the first conducting layer and the top surface of the second conducting layer; forming a first electrode layer, a magnetic tunnel junction positioned on the surface of the first electrode layer and a second electrode layer positioned on the surface of the magnetic tunnel junction on the surface of the first conductive layer; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface; and forming a third conductive layer in the first dielectric layer, wherein the bottom of the third conductive layer is in contact with the top surface of the second electrode layer. The method can save the process steps and improve the compatibility of the process.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

Mram (magnetic Random Access memory) is a non-volatile magnetic Random Access memory. The high-speed read-write capacity of a Static Random Access Memory (SRAM) is possessed, the high integration degree of a Dynamic Random Access Memory (DRAM) is far lower than that of the DRAM, and compared with a Flash memory (Flash), the performance is not degraded along with the increase of the service time. Due to the above-mentioned characteristics of MRAM, it is called universal memory (universal memory) and is considered to be capable of replacing SRAM, DRAM, EEPROM and Flash.

Unlike conventional random access memory chip fabrication techniques, data in MRAM is not stored in the form of an electrical charge or current, but rather is stored in a magnetic state, and is sensed by measuring resistance without disturbing the magnetic state. MRAM uses a Magnetic Tunnel Junction (MTJ) structure for data storage, generally, an MRAM cell is composed of a transistor (1T) and a Magnetic Tunnel Junction (MTJ) together to form a memory cell, and the magnetic tunnel junction structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. Current flows vertically from one electromagnetic layer through the insulating layer or "through" the other electromagnetic layer. One of the electromagnetic layers is a pinned magnetic layer that fixes the electrode in a specific direction by a strong pinning field. And the other electromagnetic layer is a freely rotatable magnetic layer for holding the electrode on one of the two sides.

However, the process steps of the magnetic random access memory formed by the prior art are complicated.

Disclosure of Invention

The present invention provides a semiconductor structure and a method for forming the same, which can save the process steps and improve the compatibility of the process.

To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: providing a substrate, wherein the substrate comprises a storage area and a logic area, the storage area is provided with a first conducting layer, the logic area is provided with a second conducting layer, and the substrate exposes the top surface of the first conducting layer and the top surface of the second conducting layer; forming a first electrode layer, a magnetic tunnel junction positioned on the surface of the first electrode layer and a second electrode layer positioned on the surface of the magnetic tunnel junction on the surface of the first conductive layer; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface; and forming a third conductive layer in the first dielectric layer, wherein the bottom of the third conductive layer is in contact with the top surface of the second electrode layer.

Optionally, the method further includes: and before the first electrode layer is formed, forming an etching stop layer on the surface of the logic area.

Optionally, the forming method of the etching stop layer includes: forming a stopping material layer on the surface of the substrate; forming a first graphical layer on the surface of the stop material layer on the logic region, wherein the first graphical layer exposes the surface of the stop material layer on the storage region; and etching the stop material layer by adopting a first etching process and taking the first patterning layer as a mask until the surface of the substrate is exposed to form the etching stop layer.

Optionally, the etching rate of the first etching process to the stop material layer is greater than the etching rate to the substrate, and the etching rate of the first etching process to the stop material layer is greater than the etching rate to the first conductive layer.

Optionally, the material of the stop material layer is different from the material of the substrate, and the material of the stop material layer is different from the material of the first conductive layer; the material of the stop material layer includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

Optionally, the method for forming the first dielectric layer includes: forming a first dielectric material film covering the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface and the top surface of the second electrode layer and the surface of the second conductive layer on the substrate, wherein the top surface of the first dielectric material film is higher than the top surface of the second electrode layer; and flattening the first medium material film to form the first medium layer.

Optionally, the method further includes: and forming a plug in the first dielectric layer after forming the first dielectric layer, wherein the bottom of the third conductive layer is contacted with the top surface of the plug, and the plug is positioned on the surface of the second conductive layer.

Optionally, the top surface of the first dielectric layer is higher than the top surface of the second electrode layer; the forming method of the plug and the third conductive layer comprises the following steps: forming a through hole and a groove in the first dielectric layer, wherein the bottom of the groove is exposed out of the through hole and the top surface of the second electrode layer, and the bottom of the through hole is exposed out of the surface of the second conductive layer; forming a conductive material film in the through hole, the groove and the surface of the first medium layer; and flattening the conductive material film until the surface of the first medium layer is exposed, forming the plug in the through hole, and forming the third conductive layer in the groove.

Optionally, the material of the plug comprises: one or more of copper, tungsten, aluminum, titanium and tantalum; the material of the third conductive layer includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

Optionally, the method further includes: after the first electrode layer, the magnetic tunnel junction and the second electrode layer are formed and before the first dielectric layer is formed, protective layers are formed on the substrate surface, the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface of the second electrode layer.

Optionally, the protective layer and the dielectric layer are made of different materials; the material of the protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

Optionally, the material of the first electrode layer includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

Optionally, the thickness of the first electrode layer ranges from 50 angstroms to 300 angstroms.

Optionally, the material of the second electrode layer includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

Optionally, the thickness of the second electrode layer ranges from 50 angstroms to 300 angstroms.

Optionally, the method for forming the first electrode layer, the magnetic tunnel junction, and the second electrode layer includes: forming a first electrode film, a magnetic tunnel film on the surface of the first electrode film, and a second electrode film on the surface of the magnetic tunnel film on the substrate; forming a second patterned layer on the surface of the second electrode film, wherein the second patterned layer covers a part of the surface of the second electrode film on the first conductive layer, and the second patterned layer exposes the surface of the second electrode film on the logic region; and etching the second electrode film, the magnetic tunnel film and the first electrode film by taking the second patterning layer as a mask until the surface of the substrate is exposed, and forming the first electrode layer, the magnetic tunnel junction positioned on the surface of the first electrode layer and the second electrode layer positioned on the surface of the magnetic tunnel junction on the first conductive layer.

Optionally, a second etching process is adopted, and the second electrode film, the magnetic tunnel film and the first electrode film are etched by taking the second patterning layer as a mask; the second etching process further includes: and after the surface of the substrate is exposed, continuously taking the second patterning layer as a mask to carry out over-etching.

Optionally, the magnetic tunnel junction includes: the electromagnetic sensor comprises a lower electromagnetic layer positioned on the surface of the first electrode layer, an insulating layer positioned on the surface of the lower electromagnetic layer and an upper electromagnetic layer positioned on the surface of the insulating layer.

Optionally, the substrate comprises: the first conducting layer and the second conducting layer are positioned in the second dielectric layer; logic devices are arranged in the substrate of the logic area and in the second dielectric layer.

Correspondingly, the technical solution of the present invention further provides a semiconductor structure formed by any one of the above methods, including: the substrate comprises a storage area and a logic area, wherein the storage area is provided with a first conductive layer, the logic area is provided with a second conductive layer, and the substrate exposes the top surface of the first conductive layer and the top surface of the second conductive layer; the first electrode layer is positioned on the first conducting layer, the magnetic tunnel junction is positioned on the surface of the first electrode layer, and the second electrode layer is positioned on the surface of the magnetic tunnel junction; the first dielectric layer is positioned on the substrate and covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface; and the bottom of the third conductive layer is in contact with the top surface of the second electrode layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, the first electrode layer is formed on the surface of the first conductive layer, and the bottom of the formed third conductive layer is contacted with the top surface of the second electrode layer, so that the first electrode layer, the magnetic tunnel junction and the second electrode layer are respectively contacted with the first conductive layer and the third conductive layer through the upper surface and the lower surface, thereby realizing electric connection, and enabling the formed semiconductor structure to have a storage function.

Further, forming a first electrode layer, a magnetic tunnel junction and a second electrode layer by a patterning process; and after the first electrode layer, the magnetic tunnel junction and the second electrode layer are formed, a plug and a third conductive layer are formed, wherein the plug is electrically connected with the second conductive layer of the logic region. And forming a first electrode layer, a magnetic tunnel junction and a second electrode layer through a one-time exposure and development process and a one-time etching process, wherein the plug is used for electrically connecting the logic device, so that the formed semiconductor structure can have a storage function. Therefore, the method can be well compatible with the existing logic process, and meanwhile, the process steps are fewer.

Further, before the first electrode film is formed, an etching stop layer is formed on the surface of the logic region, and the etching stop layer exposes the surface of the storage region. Therefore, the second patterning layer is used as a mask to etch the first electrode film, the magnetic tunnel film and the second electrode film on the storage region, so that in the process of forming the first electrode layer, the magnetic tunnel layer and the second electrode layer, etching damage to the substrate surface of the logic region and the surface of the second conductive layer is avoided, the influence on the logic region is reduced, and the performance of the formed semiconductor structure is improved.

Further, the plug and the third conductive layer may be formed by depositing a conductive material film in the via hole and the trench by a one-time deposition process; and after the conductive material film is flattened, forming a plug in the through hole and forming a third conductive layer in the groove. The process steps for forming the plug and the third conductive layer are fewer, thereby being beneficial to improving the production efficiency.

Drawings

FIGS. 1-6 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;

fig. 7 to 17 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background, the conventional process for forming a semiconductor structure is complicated.

The reason why the process steps for forming the semiconductor structure are complicated is described in detail below with reference to the accompanying drawings, and fig. 1 to 6 are schematic structural views of the steps of a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a storage area a and a logic area B, the storage area a has a first conductive layer 101 therein, the logic area B has a second conductive layer 102 therein, and the substrate 100 exposes a top surface of the first conductive layer 101 and a top surface of the second conductive layer 102.

Referring to fig. 2, a first dielectric layer 110 is formed on the surface of the substrate 100, and a first plug 111 is disposed in the first dielectric layer 110.

Referring to fig. 3, a second dielectric layer 120 is formed on the surface of the first plug 111 and the surface of the first dielectric layer 110, the second dielectric layer 120 has a first electrode layer 121, a magnetic tunnel junction 122 located on the surface of the first electrode layer 121, and a second electrode layer 123 located on the surface of the magnetic tunnel junction 122, and the bottom of the first electrode layer 121 contacts the first plug 111.

Referring to fig. 4, a third dielectric layer 130 is formed on the surface of the second electrode layer 123 and the surface of the second dielectric layer 120, a second plug 131 is disposed in the third dielectric layer 130, and the bottom of the second plug 131 contacts the surface of the second electrode layer 123.

Referring to fig. 5, a third plug 132 is formed in the first dielectric layer 110, the second dielectric layer 120 and the third dielectric layer 130, and the bottom of the third plug 132 contacts the surface of the second conductive layer 102.

Referring to fig. 6, a fourth dielectric layer 140 is formed on the surface of the second plug 131, the surface of the third plug 132 and the surface of the third dielectric layer 130, a third conductive layer 141 is disposed in the fourth dielectric layer 140, and the bottom of the third conductive layer 141 contacts the top surface of the second plug 131 and the top surface of the third plug 132.

In the above method, the first electrode layer 121, the magnetic tunnel junction 122 on the surface of the first electrode layer 121, and the second electrode layer 123 on the surface of the magnetic tunnel junction 122 are formed on the surface of the first plug 111 on the storage region a; and forming a second plug 131 in the third dielectric layer 130, wherein the second plug 131 is electrically connected with the second electrode layer 123. The first electrode layer 121, the magnetic tunnel junction 122, and the second electrode layer 123 are used in common as a memory device, and the memory device is electrically connected to other devices through the first plug 111 and the second plug 131. Meanwhile, the substrate 100 of the logic region B has logic devices (not shown), such as: a gate structure, a source and a drain. Therefore, the semiconductor structure formed by the method has a memory function.

However, in order to form the first electrode layer 121, the magnetic tunnel junction 122, and the second electrode layer 123 on the storage region a, it is necessary to form a first opening (not shown) in the first dielectric layer 110 and a first plug 111 in the first opening before forming the first electrode layer 121, the magnetic tunnel junction 122, and the second electrode layer 123; after the first electrode layer 121, the magnetic tunnel junction 122, and the second electrode layer 123 are formed, a second opening (not shown) is formed in the third dielectric layer 130, and a second plug 131 is formed in the second opening; after the second plug 131 is formed, a third opening (not shown) is formed in the first dielectric layer 110, the second dielectric layer 120 and the third dielectric layer 130, and a third plug 132 is formed in the third opening. The formation of the first plug 111, the second plug 131, and the third plug 132 requires a multi-exposure development process and a deposition process. Therefore, the method has complex process steps and is not beneficial to improving the production efficiency.

To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a first electrode layer, a magnetic tunnel junction positioned on the surface of the first electrode layer and a second electrode layer positioned on the surface of the magnetic tunnel junction on the surface of the first conductive layer; forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface of the second electrode layer; and forming a third conductive layer in the dielectric layer, wherein the bottom of the third conductive layer is in contact with the top surface of the second electrode layer. The method can save the process steps and improve the compatibility of the process.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 7, a substrate 200 is provided, where the substrate 200 includes a storage area a and a logic area B, the storage area a has a first conductive layer 201 therein, the logic area B has a second conductive layer 202 therein, and the substrate 200 exposes a top surface of the first conductive layer 201 and a top surface of the second conductive layer 202.

In this embodiment, the substrate 200 includes: the substrate 203 and the second dielectric layer 204 are positioned on the surface of the substrate 203, and the first conducting layer 201 and the second conducting layer 202 are positioned in the second dielectric layer 204; the substrate 203 and the second dielectric layer 204 of the logic region B have logic devices (not shown).

The material of the substrate 203 is a semiconductor material. In this embodiment, the material of the substrate 203 is silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

The material of the second dielectric layer 204 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

In this embodiment, the material of the second dielectric layer 204 is silicon oxide.

Next, an etching stop layer is formed on the surface of the logic region, and please refer to fig. 8 to fig. 10 for a process of forming the etching stop layer.

Referring to fig. 8, a stop material layer 210 is formed on the surface of the substrate 200.

The stop material layer 210 is used to provide material for the subsequent formation of an etch stop layer.

The process of forming the stop material layer 210 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In the present embodiment, the process of forming the stop material layer 210 is a chemical vapor deposition process.

The material of the stop material layer 210 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

Referring to fig. 9, a first patterned layer 220 is formed on the surface of the stop material layer 210 on the logic region B, and the first patterned layer 220 exposes the surface of the stop material layer 210 on the memory region a.

The first patterned layer 220 is used as a mask for forming an etch stop layer for the subsequent etch stop material layer 210.

Since the first patterning layer 220 exposes the surface of the stop material layer 210 on the storage region a, the subsequent etching process can remove the stop material layer 210 on the storage region a, so that an etching stop layer is formed only on the logic region B, and the process requirements are met.

Referring to fig. 10, a first etching process is performed to etch the stop material layer 210 by using the first patterned layer 220 as a mask until the surface of the substrate 200 is exposed, so as to form the etch stop layer 211.

The etching stop layer 211 is used for protecting the surface of the logic region B and reducing the influence on the logic region B in the process of forming the first electrode layer, the magnetic tunnel junction and the second electrode layer by subsequent etching.

The material of the stop material layer 210 is different from the material of the substrate 200, and the material of the stop material layer 210 is different from the material of the first conductive layer 201.

Because the material of the stop material layer 210 is different from the material of the substrate 200, and the material of the stop material layer 210 is different from the material of the first conductive layer 201, it is beneficial to adopt a proper etching process to etch the stop material layer 210 until the surface of the substrate 200 and the surface of the first conductive layer 201 are exposed, so that in the process of forming the etching stop layer 211, the etching loss caused to the substrate 200 and the first conductive layer 201 is reduced, and the performance of the formed semiconductor structure is improved.

The etching rate of the first etching process to the stop material layer 210 is greater than the etching rate to the substrate 200, and the etching rate of the first etching process to the stop material layer 210 is greater than the etching rate to the first conductive layer 201.

In this embodiment, specifically, the etching rate of the first etching process to the stop layer 210 is greater than the etching rate to the second dielectric layer 204 on the surface of the substrate 203.

In this embodiment, the material of the stop material layer 210 is silicon nitride, so that the material of the formed etch stop layer 211 is silicon nitride.

In other embodiments, the etch stop layer may not be formed.

In this embodiment, after forming the etch stop layer 211, the method further includes: the first patterned layer 220 is removed.

After the etching stop layer is formed, a first electrode layer, a magnetic tunnel junction located on the surface of the first electrode layer, and a second electrode layer located on the surface of the magnetic tunnel junction are formed on the surface of the first conductive layer, and please refer to fig. 11 to 13 for a process of specifically forming the first electrode layer, the magnetic tunnel junction, and the second electrode layer.

Referring to fig. 11, a first electrode film 221, a magnetic tunnel film 222 on a surface of the first electrode film 221, and a second electrode film 223 on a surface of the magnetic tunnel film 222 are formed on the substrate 200.

In this embodiment, the first electrode film 221 also covers the sidewall surface and the top surface of the etch stop layer 211.

The first electrode film 221 provides a material for a first electrode layer to be formed later, the magnetic tunnel film 222 provides a material for a magnetic tunnel junction to be formed later, and the second electrode film 223 provides a material for a second electrode layer to be formed later.

The material of the first electrode film 221 includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

In this embodiment, the first electrode film 221 has a stacked structure, and the material of the first electrode film 221 is titanium nitride and tungsten. In other embodiments, the first electrode film is a stacked structure formed of other materials. In other embodiments, the first electrode film may also have a single-layer structure.

The material of the second electrode film 223 includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

In the present embodiment, the second electrode film 223 has a stacked structure, and the material of the second electrode film 223 is titanium nitride and tungsten. In other embodiments, the second electrode film is a stacked structure formed of other materials. In other embodiments, the second electrode film may also have a single-layer structure.

The magnetic tunnel film 222 includes: a lower electromagnetic film (not shown) on the surface of the first electrode film 221; an insulating film (not shown) on the surface of the lower electromagnetic film; an upper electromagnetic film (not shown) on the surface of the insulating film.

The lower electromagnetic film is used for forming a lower electromagnetic layer subsequently, the insulating film is used for forming an insulating layer subsequently, and the upper electromagnetic film is used for forming an upper electromagnetic layer subsequently.

Referring to fig. 12, a second patterned layer 230 is formed on the surface of the second electrode film 223, the second patterned layer 230 covers a portion of the surface of the second electrode film 223 on the first conductive layer 201, and the second patterned layer 230 exposes the surface of the second electrode film 223 on the logic region B.

The second patterning layer 230 is used as a mask for etching the second electrode film 223, the magnetic tunnel film 222, and the first electrode film 221.

Since the second patterning layer 230 exposes the second electrode film 223 on the logic region B, a first electrode layer, a magnetic tunnel structure on the surface of the first electrode layer, and a second electrode layer on the surface of the magnetic tunnel structure are formed on the surface of the storage region a, that is, a device with a storage function is formed on the surface of the storage region a.

Because the surface of the logic region B is provided with the etching stop layer 211, and the etching stop layer 211 exposes the surface of the storage region a, the first electrode film 221, the magnetic tunnel film 222, and the second electrode film 223 on the storage region a are etched by using the second patterning layer 230 as a mask, so that in the process of forming the first electrode layer 241, the magnetic tunnel layer 242, and the second electrode layer 243, no etching damage is caused to the surface of the substrate 200 of the logic region B and the surface of the second conductive layer 202, thereby reducing the influence on the logic region B, and facilitating the improvement of the performance of the formed semiconductor structure.

Referring to fig. 13, the second electrode film 223, the magnetic tunnel film 222 and the first electrode film 221 are etched by using the second patterning layer 230 as a mask until the surface of the substrate 200 is exposed, and the first electrode layer 241, the magnetic tunnel junction 242 on the surface of the first electrode layer 241 and the second electrode layer 243 on the surface of the magnetic tunnel junction 242 are formed on the first conductive layer 201.

It should be noted that the first electrode layer 241, the magnetic tunnel junction 242 located on the surface of the first electrode layer 241, and the second electrode layer 243 located on the surface of the magnetic tunnel junction are used together as a memory device.

In this embodiment, a second etching process is adopted to etch the second electrode film 223, the magnetic tunnel film 222 and the first electrode film 221 by using the second patterning layer 230 as a mask.

The first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243 are formed by a patterning process using a second etching process, that is, a number of process steps is reduced by a single exposure and development process and a single etching process.

In this embodiment, the second etching process further includes: after the surface of the substrate 200 is exposed, the second patterning layer 230 is continuously used as a mask to perform over-etching.

Through the over-etching treatment, the first electrode layers 241 formed on the adjacent first conductive layers 201 can be sufficiently isolated, so that the electric crosstalk between the adjacent memory devices is avoided, and the performance of the formed semiconductor structure is better.

In this embodiment, after forming the first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243, the method further includes: the second patterned layer 230 is removed.

The first electrode layer 241 is formed of a first electrode film 221, and accordingly, the material of the first electrode layer 241 includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

In this embodiment, the first electrode layer 241 is a stacked structure of titanium nitride and tungsten.

The thickness range of the first electrode layer 241 is 50 angstroms to 300 angstroms, and the thicker first electrode layer 241 is beneficial to meeting the process requirements.

The material of the second electrode layer 243 includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

The thickness of the second electrode layer 243 ranges from 50 angstroms to 300 angstroms, and the thicker second electrode layer 243 is beneficial to meeting the process requirement.

The magnetic tunnel junction 242 includes: a lower electromagnetic layer (not shown) on the surface of the first electrode layer 241, an insulating layer (not shown) on the surface of the lower electromagnetic layer, and an upper electromagnetic layer (not shown) on the surface of the insulating layer.

The material of the upper electromagnetic film comprises: one or a combination of more of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron, nickel-iron or lanthanum-strontium-manganese-oxygen. In this embodiment, the material of the upper electromagnetic film and the material of the lower electromagnetic film are the same, and cobalt, iron and boron are used. In other embodiments, the material of the upper electromagnetic film is different from the material of the lower electromagnetic film.

The material of the insulating film includes: one or more of magnesium oxide, aluminum oxide, silicon nitride, silicon oxynitride, hafnium oxide and zirconium dioxide. In this embodiment, the material of the insulating film is magnesium oxide.

The common height of the first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243 is consistent with the height of a plug to be formed later, thereby satisfying compatibility of the memory region a and the logic region B.

Referring to fig. 14, after the first electrode layer 241, the magnetic tunnel junction 242 and the second electrode layer 243 are formed, a protective layer 250 is formed on the surface of the substrate 200, the sidewall surface of the first electrode layer 241, the sidewall surface of the magnetic tunnel junction 242 and the sidewall surface and the top surface of the second electrode layer 243.

The protective layer 250 is used to protect the surfaces of the first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243, and reduce the influence of the subsequent processes, and to improve the stability of the first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243 on different first conductive layers 201 as a whole.

In this embodiment, the protection layer 250 is also located on the surface of the etch stop layer 211.

The material of the protective layer 250 is different from that of the first dielectric layer formed later.

The material of the protective layer 250 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

In this embodiment, the material of the protection layer 250 is silicon oxynitride.

In other embodiments, the protective layer may not be formed.

Referring to fig. 15, after the first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243 are formed, a first dielectric layer 260 is formed on the substrate 200, and the first dielectric layer 260 covers a sidewall surface of the first electrode layer 241, a sidewall surface of the magnetic tunnel junction 242, a sidewall surface of the second electrode layer 243, and a top surface of the second electrode layer 243.

The method for forming the first dielectric layer 260 comprises the following steps: forming a first dielectric material film (not shown) on the substrate 200 covering the sidewall surface of the first electrode layer 241, the sidewall surface of the magnetic tunnel junction 242, the sidewall surface of the second electrode layer 242, and the top surface of the first dielectric material film higher than the top surface of the second electrode layer 243; and flattening the first dielectric material film to form the first dielectric layer 260.

In this embodiment, the first dielectric layer 260 is located on the surface of the protection layer 250.

The material of the first medium material film includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

The first dielectric layer 260 is formed by a first dielectric material film, and accordingly, the material of the first dielectric layer 260 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride. In this embodiment, the first dielectric layer is made of silicon oxide.

In the present embodiment, the top surface of the first dielectric layer 260 formed after planarization is higher than the top surface of the second electrode layer 242.

In other embodiments, the first dielectric material film may also be not planarized, i.e., the first dielectric material film directly serves as the first dielectric layer.

After the first dielectric layer 260 is formed, a third conductive layer is formed in the first dielectric layer 260, and the bottom of the third conductive layer is in contact with the top surface of the second electrode layer 243.

In this embodiment, after forming the first dielectric layer 260, the method further includes: and forming a plug in the first dielectric layer 260, wherein the bottom of the third conductive layer is in contact with the top surface of the plug, and the plug is positioned on the surface of the second conductive layer 202.

In this embodiment, the third conductive layer and the plug are formed simultaneously, and in detail, please refer to fig. 16 to 17 for a process of forming the third conductive layer and the plug.

Referring to fig. 16, a via hole 261 and a trench 262 are formed in the first dielectric layer 260, the bottom of the trench 262 exposes the via hole 261 and the top surface of the second electrode layer 243, and the bottom of the via hole 261 exposes the surface of the second conductive layer 202.

The bottom of the through hole 261 exposes the surface of the second conductive layer 202, so that after a plug is formed by subsequently filling a conductive material, the device in the logic region B can be electrically connected with a peripheral circuit.

The bottom of the trench 262 exposes the surface of the second electrode layer 243, so that after a conductive material is subsequently filled to form a third conductive layer, the device in the storage region a can be electrically connected to a peripheral circuit.

In the present embodiment, the trenches 262 and the vias 261 are connected, so that the subsequently formed third conductive layer can electrically connect the devices in the memory region a and the devices in the logic region B at the same time.

In other embodiments, the trench 262 and the via 261 do not communicate.

Referring to fig. 17, a conductive material film (not shown) is formed in the through hole 261, the trench 262 and the surface of the first dielectric layer 260; and flattening the conductive material film until the surface of the first dielectric layer 260 is exposed, forming the plug 271 in the through hole 261, and forming the third conductive layer 272 in the groove 262.

The material of the plug 271 includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

The material of the third conductive layer 272 includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

In this embodiment, the plug 271 and the third conductive layer 272 are formed by planarizing the conductive material film, so that the material of the plug 271 and the third conductive layer 272 is the same.

In this embodiment, the material of the conductive material film is tungsten, so the material of the plug 271 and the third conductive layer 272 is tungsten.

Since the first electrode layer 241 is formed on the surface of the first conductive layer 201, and the bottom surface of the formed third conductive layer 272 is in contact with the top surface of the second electrode layer 243, the first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243 are in contact with the first conductive layer 201 and the third conductive layer 272 through the upper and lower surfaces, respectively, so as to achieve electrical connection, so that the formed semiconductor structure can have a memory function.

Forming a first electrode layer 241, a magnetic tunnel junction 242, and a second electrode layer 243 through a patterning process; after the first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243 are formed, a plug 271 and a third conductive layer 272 are formed, and the plug 271 is electrically connected to the second conductive layer 202 of the logic region B. The first electrode layer 241, the magnetic tunnel junction 242, and the second electrode layer 243 are formed by one exposure and development process and one etching process, and the plug 271 is used to electrically connect the logic device, so that the formed semiconductor structure can have a memory function. Therefore, the method can be well compatible with the existing logic process, and meanwhile, the process steps are fewer.

The plug 271 and the third conductive layer 272 are formed by depositing a conductive material film in the via 261 and the trench 262 through a one-time deposition process; after the conductive material film is planarized, the plug 271 is formed in the through hole 261, and the third conductive layer 272 is formed in the trench 262, so that the process steps for forming the plug 271 and the third conductive layer 272 are fewer, which is beneficial to improving the production efficiency.

Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to fig. 17, which includes: the substrate 200 comprises a storage area A and a logic area B, wherein the storage area A is provided with a first conductive layer 201, the logic area B is provided with a second conductive layer 202, and the substrate 200 exposes the top surface of the first conductive layer 201 and the top surface of the second conductive layer 202; a first electrode layer 241 on the first conductive layer 201, a magnetic tunnel junction 242 on the surface of the first electrode layer 241, and a second electrode layer 243 on the surface of the magnetic tunnel junction 242; a first dielectric layer 260 on the substrate 200, wherein the first dielectric layer 260 covers a sidewall surface of the first electrode layer 241, a sidewall surface of the magnetic tunnel junction 242, a sidewall and a top surface of the second electrode layer 243; and a third conductive layer 272 located in the first dielectric layer 260, wherein the bottom of the third conductive layer 272 contacts with the top surface of the second electrode layer 242.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a storage area and a logic area, the storage area is provided with a first conducting layer, the logic area is provided with a second conducting layer, and the substrate exposes the top surface of the first conducting layer and the top surface of the second conducting layer;

forming a first electrode layer, a magnetic tunnel junction positioned on the surface of the first electrode layer and a second electrode layer positioned on the surface of the magnetic tunnel junction on the surface of the first conductive layer;

forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface;

and forming a third conductive layer in the first dielectric layer, wherein the bottom of the third conductive layer is in contact with the top surface of the second electrode layer.

2. The method of forming a semiconductor structure of claim 1, further comprising: and before the first electrode layer is formed, forming an etching stop layer on the surface of the logic area.

3. The method of forming a semiconductor structure of claim 2, wherein the method of forming the etch stop layer comprises: forming a stopping material layer on the surface of the substrate; forming a first graphical layer on the surface of the stop material layer on the logic region, wherein the first graphical layer exposes the surface of the stop material layer on the storage region; and etching the stop material layer by adopting a first etching process and taking the first patterning layer as a mask until the surface of the substrate is exposed to form the etching stop layer.

4. The method of forming a semiconductor structure of claim 3, wherein the first etch process etches the stop material layer at a rate greater than the substrate and the first etch process etches the stop material layer at a rate greater than the first conductive layer.

5. The method according to claim 3, wherein a material of the stop material layer is different from a material of the substrate, and the material of the stop material layer is different from a material of the first conductive layer; the material of the stop material layer includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

6. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first dielectric layer comprises: forming a first dielectric material film covering the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface and the top surface of the second electrode layer and the surface of the second conductive layer on the substrate, wherein the top surface of the first dielectric material film is higher than the top surface of the second electrode layer; and flattening the first medium material film to form the first medium layer.

7. The method of forming a semiconductor structure of claim 1, further comprising: and forming a plug in the first dielectric layer after forming the first dielectric layer, wherein the bottom of the third conductive layer is contacted with the top surface of the plug, and the plug is positioned on the surface of the second conductive layer.

8. The method of forming a semiconductor structure of claim 7, wherein a top surface of the first dielectric layer is higher than a top surface of the second electrode layer; the forming method of the plug and the third conductive layer comprises the following steps: forming a through hole and a groove in the first dielectric layer, wherein the bottom of the groove is exposed out of the through hole and the top surface of the second electrode layer, and the bottom of the through hole is exposed out of the surface of the second conductive layer; forming a conductive material film in the through hole, the groove and the surface of the first medium layer; and flattening the conductive material film until the surface of the first medium layer is exposed, forming the plug in the through hole, and forming the third conductive layer in the groove.

9. The method of forming a semiconductor structure of claim 7, wherein a material of the plug comprises: one or more of copper, tungsten, aluminum, titanium and tantalum; the material of the third conductive layer includes: one or more of copper, tungsten, aluminum, titanium and tantalum.

10. The method of forming a semiconductor structure of claim 1, further comprising: after the first electrode layer, the magnetic tunnel junction and the second electrode layer are formed and before the first dielectric layer is formed, protective layers are formed on the substrate surface, the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface of the second electrode layer.

11. The method of forming a semiconductor structure of claim 10, wherein the protective layer and the dielectric layer are of different materials; the material of the protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

12. The method of forming a semiconductor structure of claim 1, wherein a material of the first electrode layer comprises: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

13. The method of forming a semiconductor structure of claim 1, wherein the first electrode layer has a thickness in a range of 50 angstroms to 300 angstroms.

14. The method of forming a semiconductor structure according to claim 1, wherein a material of the second electrode layer comprises: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.

15. The method of forming a semiconductor structure of claim 1, wherein the second electrode layer has a thickness in a range of 50 angstroms to 300 angstroms.

16. The method of forming a semiconductor structure according to claim 1, wherein the method of forming the first electrode layer, the magnetic tunnel junction, and the second electrode layer comprises: forming a first electrode film, a magnetic tunnel film on the surface of the first electrode film, and a second electrode film on the surface of the magnetic tunnel film on the substrate; forming a second patterned layer on the surface of the second electrode film, wherein the second patterned layer covers a part of the surface of the second electrode film on the first conductive layer, and the second patterned layer exposes the surface of the second electrode film on the logic region; and etching the second electrode film, the magnetic tunnel film and the first electrode film by taking the second patterning layer as a mask until the surface of the substrate is exposed, and forming the first electrode layer, the magnetic tunnel junction positioned on the surface of the first electrode layer and the second electrode layer positioned on the surface of the magnetic tunnel junction on the first conductive layer.

17. The method of forming a semiconductor structure according to claim 16, wherein the second electrode film, the magnetic tunnel film, and the first electrode film are etched using the second patterned layer as a mask by a second etching process; the second etching process further includes: and after the surface of the substrate is exposed, continuously taking the second patterning layer as a mask to carry out over-etching.

18. The method of forming a semiconductor structure of claim 1, wherein the magnetic tunnel junction comprises: the electromagnetic sensor comprises a lower electromagnetic layer positioned on the surface of the first electrode layer, an insulating layer positioned on the surface of the lower electromagnetic layer and an upper electromagnetic layer positioned on the surface of the insulating layer.

19. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: the first conducting layer and the second conducting layer are positioned in the second dielectric layer; logic devices are arranged in the substrate of the logic area and in the second dielectric layer.

20. A semiconductor structure formed by the method of any of claims 1 to 19, comprising:

the substrate comprises a storage area and a logic area, wherein the storage area is provided with a first conductive layer, the logic area is provided with a second conductive layer, and the substrate exposes the top surface of the first conductive layer and the top surface of the second conductive layer;

the first electrode layer is positioned on the first conducting layer, the magnetic tunnel junction is positioned on the surface of the first electrode layer, and the second electrode layer is positioned on the surface of the magnetic tunnel junction;

the first dielectric layer is positioned on the substrate and covers the side wall surface of the first electrode layer, the side wall surface of the magnetic tunnel junction, the side wall surface of the second electrode layer and the top surface of the second electrode layer;

and the bottom of the third conductive layer is in contact with the top surface of the second electrode layer.