CN112635659B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112635659B
CN112635659B CN201910954848.0A CN201910954848A CN112635659B CN 112635659 B CN112635659 B CN 112635659B CN 201910954848 A CN201910954848 A CN 201910954848A CN 112635659 B CN112635659 B CN 112635659B
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layer
forming
magnetic tunnel
trench
mask
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CN112635659A (en
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate is internally provided with a first conductive layer, the first conductive layer extends along a first direction, and the first conductive layer is arranged along a second direction; forming an initial magnetic tunnel structure on the surface of the first conductive layer and the surface of the substrate; forming a first trench and a second trench in the initial magnetic tunnel structure, wherein the second trench extends along a first direction, the first trench is positioned between adjacent second trenches, the first trench extends along a second direction, the first trench has a first size along the first direction, the second trench has a second size along the second direction, and the first size is smaller than the second size; forming a mask layer in the first groove and on the surface of the side wall of the second groove, wherein the mask layer is filled in the first groove; and etching the initial magnetic tunnel structure by taking the mask layer as a mask until the surface of the substrate is exposed, and forming the magnetic tunnel structure on the surface of the first conductive layer. The semiconductor structure formed by the method has better performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
MRAM (Magnetic Random Access Memory) is a non-volatile Magnetic Random Access Memory. The high-speed read-write capacity of a Static Random Access Memory (SRAM) is possessed, the high integration degree of a Dynamic Random Access Memory (DRAM) is far lower than that of the DRAM, and compared with a Flash memory (Flash), the performance is not degraded along with the increase of the service time. Due to the above-mentioned characteristics of MRAM, it is called universal memory (universal memory) and is considered to be capable of replacing SRAM, DRAM, EEPROM and Flash.
Unlike conventional random access memory chip fabrication techniques, data in MRAM is not stored in the form of an electrical charge or current, but rather is stored in a magnetic state, and is sensed by measuring resistance without disturbing the magnetic state. MRAM uses a Magnetic Tunnel Junction (MTJ) structure for data storage, and generally, an MRAM cell is a memory cell composed of a transistor (1T) and a Magnetic Tunnel Junction (MTJ), and the Magnetic Tunnel Junction (MTJ) structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. Current flows vertically from one electromagnetic layer through the insulating layer or "through" the other electromagnetic layer. One of the electromagnetic layers is a pinned magnetic layer that fixes the electrode in a specific direction by a strong pinning field. And the other electromagnetic layer is a freely rotatable magnetic layer for holding the electrode on one of the two sides.
However, the performance of the magnetic random access memory formed by the prior art is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the formed semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a storage area, a plurality of first conductive layers are arranged in the storage area, the top surfaces of the first conductive layers are exposed out of the substrate, the first conductive layers extend along a first direction, and the first conductive layers are arranged along a second direction; forming an initial magnetic tunnel structure on the surface of the first conductive layer and the surface of the substrate; forming a first trench and a second trench in the initial magnetic tunnel structure, wherein the second trench extends along a first direction, the first trench is located between adjacent second trenches, the first trench extends along a second direction, the first trench is located on the first conductive layer, the second trench is located on the substrate, the first trench has a first size along the first direction, the second trench has a second size along the second direction, and the first size is smaller than the second size; forming mask layers on the surface of the side wall and the bottom of the first groove and the surface of the side wall of the second groove, wherein the first groove is filled with the mask layers; and etching the initial magnetic tunnel structure by taking the mask layer as a mask until the surface of the substrate is exposed, and forming the magnetic tunnel structure on the surface of the first conductive layer.
Optionally, the substrate further comprises: the logic area is provided with a second conducting layer, and the substrate exposes the top surface of the second conducting layer; the initial magnetic tunnel structure exposes a logic region surface.
Optionally, the method for forming the initial magnetic tunnel structure includes: forming a first electrode film on the surface of the first conductive layer and the surface of the substrate; forming a magnetic tunnel film on the surface of the first electrode film; forming a second electrode film on the surface of the magnetic tunnel film; the first trench top surface and the second trench top surface are lower than a top surface of the first electrode film.
Optionally, the method for forming the first trench and the second trench includes: forming a first patterning layer on the surface of the second electrode film on part of the storage region, wherein the pattern in the first patterning layer corresponds to the positions and the sizes of the first groove and the second groove; and etching parts of the first electrode film, the magnetic tunnel film and the second electrode film by taking the first patterning layer as a mask to expose the surface of the first electrode film, and forming a first groove and a second groove in the initial tunnel structure.
Optionally, the forming method of the mask layer includes: forming a layer of masking material within the first trench and on the second trench sidewall and bottom surfaces and on the initial magnetic tunnel structure top surface; and etching the mask material layer back until the bottom surface of the second groove and the top surface of the initial magnetic tunnel structure are exposed, and forming the mask layer in the first groove and on the side wall surface of the second groove.
Optionally, the process for forming the mask material layer includes: and (5) an atomic layer deposition process.
Optionally, the material of the mask layer is different from the material of the initial magnetic tunnel structure; the mask layer is made of materials including: titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
Optionally, the method further includes: and forming an etching stop layer on the surface of the logic area before forming the initial magnetic tunnel structure.
Optionally, the forming method of the etching stop layer includes: forming a stop material layer on the surfaces of the storage area and the logic area; forming a second graphical layer on the surface of the stop material layer on the logic area, wherein the second graphical layer exposes the surface of the stop material layer on the storage area; and etching the stop material layer by taking the second patterning layer as a mask until the surface of the substrate is exposed to form the etching stop layer.
Optionally, the material of the etching stop layer is different from the material of the mask layer; the material of the etching stop layer is different from the materials of the substrate, the first conducting layer and the second conducting layer; the material of the etching stop layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
Optionally, with the first patterning layer as a mask, etching a part of the first electrode film, the magnetic tunnel film, and the second electrode film until the surface of the etching stop layer is exposed, and forming a first trench and a second trench in the initial magnetic tunnel structure, where the bottoms of the first trench and the second trench are flush with the surface of the etching stop layer.
Optionally, the method further includes: after the magnetic tunnel structure is formed, forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the top surface and the side wall surface of the magnetic tunnel structure; and forming a plug and a third conducting layer in the first dielectric layer, wherein the third conducting layer is contacted with the surface of the second electrode layer, the third conducting layer is contacted with the top surface of the plug, and the plug is positioned on the surface of the second conducting layer in the logic area.
Optionally, the mask layer is used as a mask to etch the initial magnetic tunnel structure, and after the substrate surface is exposed, the mask layer is continuously used as a mask to perform over-etching.
Optionally, the method further includes: and after the magnetic tunnel structure is formed and before the first dielectric layer is formed, forming protective layers on the surface of the substrate, the surface of the side wall and the top surface of the mask layer and the surface of the top of the magnetic tunnel structure.
Optionally, the protective layer and the first dielectric layer are made of different materials; the material of the protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
Optionally, the material of the first conductive layer includes: one or a combination of more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum; the material of the second conductive layer includes: copper, cobalt, tungsten, aluminum, titanium nitride, tantalum.
Optionally, the magnetic tunnel structure includes: the first electrode layer is positioned on the surface of the first conductive layer; a magnetic tunnel junction located at a portion of the first electrode layer surface; a second electrode layer on a surface of the magnetic tunnel junction; the material of the first electrode layer includes: one or a combination of more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum; the material of the second electrode layer includes: one or more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum.
Optionally, the magnetic tunnel junction includes: the electromagnetic shielding film comprises a lower electromagnetic layer positioned on the surface of the first electrode layer, an insulating layer positioned on the surface of the lower electromagnetic layer and an upper electromagnetic layer positioned on the surface of the insulating layer.
Optionally, the substrate comprises: the first conducting layer and the second conducting layer are positioned in the second dielectric layer; logic devices are arranged in the logic area and in the second medium layer on the surface of the logic area.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, an initial magnetic tunnel structure is formed on the surface of the first conductive layer and the surface of the substrate, a first groove and a second groove are formed in the initial magnetic tunnel structure, the first groove has a first size along a first direction, and the second groove has a second size along a second direction. Because the first size is smaller than the second size, the first groove can be filled with a subsequently formed mask layer, and the second groove cannot be filled with the mask layer. And then, the mask layer is used as a mask to etch the initial magnetic tunnel structure until the surface of the substrate is exposed, the initial magnetic tunnel structure at the bottom of the first groove cannot be etched due to the protection of the mask layer in the first groove, and further the surface of the first conductive layer cannot be etched, so that the influence on the conductivity of the first conductive layer is avoided, and the performance of the formed semiconductor structure is improved.
Further, since an etching stop layer is formed on the surface of the logic region before the initial magnetic tunnel structure is formed, the etching stop layer exposes the surface of the storage region. Therefore, the first electrode film, the magnetic tunnel film and the second electrode film are etched by taking the first patterning layer as a mask until the surface of the etching stop layer is exposed, and the etching stop layer is taken as an etching indicating layer, so that part of the first electrode film can be reserved on the surface of the first conductive layer, and the surface of the first conductive layer is prevented from being etched; on the other hand, etching damage cannot be caused to the substrate surface of the logic area and the surface of the second conductive layer, and therefore the influence on the logic area is reduced. In summary, the method is advantageous for improving the performance of the formed semiconductor structure.
Drawings
FIGS. 1-6 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 7 to 20 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the semiconductor structures formed in the prior art have poor performance.
The reason for the poor performance of the semiconductor structure will be described in detail below with reference to the accompanying drawings, and fig. 1 to 6 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a storage area a and a logic area B, the storage area a has a first conductive layer 101 therein, the logic area B has a second conductive layer 102 therein, and the substrate 100 exposes a top surface of the first conductive layer 101 and a top surface of the second conductive layer 102.
Referring to fig. 2, a first electrode film 111, a magnetic tunnel film 112 on a surface of the first electrode film 111, and a second electrode film 113 on a surface of the magnetic tunnel film 112 are formed on the substrate 100.
Referring to fig. 3, a first patterned layer 120 is formed on the surface of the second electrode film 113, the first patterned layer 120 covers a portion of the surface of the second electrode film 113 on the first conductive layer 101, and the first patterned layer 120 exposes the surface of the second electrode film 113 in the logic region B.
Referring to fig. 4, the second electrode layer 113, the magnetic tunnel film 112 and the first electrode layer 111 are etched by using the first patterning layer 120 as a mask until the surface of the substrate 100 is exposed, and a first electrode layer 121, a magnetic tunnel junction 122 located on the surface of the first electrode layer 121 and a second electrode layer 113 located on the surface of the magnetic tunnel junction 122 are formed on the storage region a.
Referring to fig. 5, a dielectric layer 130 is formed on the substrate 100, and the dielectric layer 130 covers the sidewall surface of the first electrode layer 121, the sidewall surface of the magnetic tunnel junction 122, and the sidewall surface and the top surface of the second electrode layer 123.
Referring to fig. 6, a plug 141 and a third conductive layer 142 are formed in the dielectric layer 130, the third conductive layer 142 contacts with the surface of the second electrode layer 123, the third conductive layer 142 contacts with the top surface of the plug 141, and the plug 141 is located on the surface of the second conductive layer 102 in the logic region B.
In the above method, the first electrode layer 121, the magnetic tunnel junction 122, and the second electrode layer 123 collectively function as a memory cell. The method has fewer process steps for forming the storage unit and is beneficial to improving the production efficiency.
However, in the process of etching the second electrode film 113, the magnetic tunnel film 112, and the first electrode film 111 by using the first patterning layer 120 as a mask until the surface of the substrate 100 is exposed, a portion of the surface of the first conductive layer 101 is easily exposed, so as to etch the surface of the first conductive layer 101. On one hand, the crystal lattice of the material in the first conductive layer 101 is easily damaged to cause the decrease of the conductivity of the first conductive layer 101, and on the other hand, the etching by-product generated by the etching process easily covers the surface of the first conductive layer 101 to cause the decrease of the reliability of the first conductive layer 101, so that the performance of the formed semiconductor structure is poor.
To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming mask layers on the surface of the side wall and the bottom of the first groove and the surface of the side wall of the second groove, wherein the first groove is filled with the mask layers; and etching the initial magnetic tunnel structure at the bottom of the second groove by taking the mask layer as a mask until the surface of the substrate is exposed, and forming a magnetic tunnel structure on the surface of the first conductive layer. The mask layer is filled in the first groove, and the mask layer is not filled in the second groove, so that when the mask layer is used as the mask to etch the initial magnetic tunnel structure at the bottom of the second groove, the initial magnetic tunnel structure at the bottom of the first groove is not etched, the first conducting layer is prevented from being etched, and the formed semiconductor structure has good performance.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
Fig. 7 to 20 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 7 and 8, fig. 8 is a top view taken along a direction a in fig. 7, fig. 7 is a schematic cross-sectional view taken along a line M-N in fig. 8, a substrate 200 is provided, the substrate 200 includes a storage region a, a plurality of first conductive layers 201 are disposed in the storage region a, the substrate 200 exposes a top surface of the first conductive layers 201, the first conductive layers 201 extend along a first direction X, and the plurality of first conductive layers 201 are arranged along a second direction Y.
The substrate 200 further includes: and a logic region B having the second conductive layer 202 therein, wherein the substrate 200 exposes a top surface of the second conductive layer 202.
The substrate 200 includes: the substrate 203 and the second dielectric layer 204 are positioned on the surface of the substrate 203, and the first conducting layer 201 and the second conducting layer 202 are positioned in the second dielectric layer 204; the substrate 203 and the second dielectric layer 204 of the logic region B have logic devices (not shown).
The material of the substrate 203 is a semiconductor material. In this embodiment, the material of the substrate 203 is silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
The material of the second dielectric layer 204 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the second dielectric layer 204 is silicon oxide.
Referring to fig. 9, fig. 9 is a schematic view based on fig. 7, and an etching stop layer 211 is formed on the surface of the logic region B.
The etching stop layer 211 is used for protecting the surface of the logic region B and reducing the influence on the logic region B in the process of forming the first electrode layer, the magnetic tunnel junction and the second electrode layer by subsequent etching.
The material of the etch stop layer 211 is different from the material of the substrate 200, the first conductive layer 201, and the second conductive layer 202.
The forming method of the etching stop layer 211 comprises the following steps: forming a stop material layer (not shown in the figure) on the surfaces of the storage area A and the logic area B; forming a second patterned layer 220 on the surface of the stop material layer on the logic region B, wherein the second patterned layer 220 exposes the surface of the stop material layer on the storage region a; and etching the stop material layer by using the second patterning layer 220 as a mask until the surface of the substrate 200 is exposed, so as to form the etching stop layer 211.
In other embodiments, the etch stop layer may not be formed.
The material of the second patterned layer 220 includes: and (7) photoresist.
The process of forming the second patterned layer 220 includes: and (4) spin coating.
In this embodiment, after forming the etch stop layer 211, the method further includes: the second patterned layer 220 is removed.
The process of removing the second patterned layer 220 includes: an ashing process or a wet etching process.
Referring to fig. 10, an initial magnetic tunnel structure (not shown) is formed on the surface of the first conductive layer 201 and the surface of the substrate 200.
In this embodiment, the initial magnetic tunnel structure includes: a first electrode film 221 on the surface of the first conductive layer 201 and the surface of the substrate 200, a magnetic tunnel film 222 on the first electrode film 221, and a second electrode film 223 on the surface of the magnetic tunnel film 222.
The forming method of the initial magnetic tunnel structure comprises the following steps: forming a first electrode film 221 on the surface of the first conductive layer 201 and the surface of the substrate 200; forming a magnetic tunnel film 222 on a surface of the first electrode film 221; a second electrode film 223 is formed on the surface of the magnetic tunnel film 222.
In the present embodiment, the first electrode film 221 also covers the sidewall surface and the top surface of the etch stop layer 211 on the logic region B.
In other embodiments, the first electrode film 221 is located on the base surface of the logic region B and the surface of the second conductive layer.
The first electrode film 221 provides a material for a first electrode layer to be formed later, the magnetic tunnel film 222 provides a material for a magnetic tunnel junction to be formed later, and the second electrode film 223 provides a material for a second electrode layer to be formed later.
The material of the first electrode film 221 includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.
In this embodiment, the first electrode film 221 has a stacked structure, and the material of the first electrode film 221 is titanium nitride and tungsten. In other embodiments, the first electrode film is a stacked structure formed of other materials. In other embodiments, the first electrode film may also have a single-layer structure.
The material of the second electrode film 223 includes: one or more of copper, tungsten, aluminum, titanium nitride and tantalum.
In the present embodiment, the second electrode film 223 has a stacked structure, and the material of the second electrode film 223 is titanium nitride and tungsten. In other embodiments, the second electrode film is a stacked structure formed of other materials. In other embodiments, the second electrode film may also have a single-layer structure.
The magnetic tunnel film 222 includes: a lower electromagnetic film (not shown) on the surface of the first electrode film 221; an insulating film (not shown) on the surface of the lower electromagnetic film; an upper electromagnetic film (not shown) on the surface of the insulating film.
The lower electromagnetic film is used for forming a lower electromagnetic layer subsequently, the insulating film is used for forming an insulating layer subsequently, and the upper electromagnetic film is used for forming an upper electromagnetic layer subsequently.
Next, a first trench and a second trench are formed in the initial magnetic tunnel structure, the second trench extends along a first direction, the first trench is located between adjacent second trenches, the first trench extends along a second direction, the first trench is located on the first conductive layer, the second trench is located on the substrate, the first trench has a first size along the first direction, the second trench has a second size along the second direction, the first size is smaller than the second size, and please refer to fig. 11 to 13 for a specific process of forming the first trench and the second trench.
Referring to fig. 11, a first patterned layer 230 is formed on the surface of the second electrode film 223 on a portion of the storage region a, and the pattern in the first patterned layer 230 corresponds to the position and size of the first trench and the second trench.
The first patterning layer 230 is used as a mask for etching an initial magnetic tunnel structure to form a first trench and a second trench in the initial magnetic tunnel film.
In this embodiment, the first patterning layer 230 is used as a mask for etching the first electrode film 221 at the bottom of the second trench together with the mask layer, so as to form a magnetic tunnel structure.
The material and formation process of the first patterned layer 230 are the same as those of the second patterned layer 220, and are not described herein again.
Referring to fig. 12 and 13, fig. 12 is a schematic view based on fig. 11, the view directions of fig. 13 and 8 are the same, the first patterning layer 230 is used as a mask, a portion of the first electrode film 221, the magnetic tunnel film 222 and the second electrode film 223 are etched to expose the surface of the first electrode film 221, and a first trench 241 and a second trench 242 are formed in the initial tunnel structure.
The first trench 241 has a first dimension L1 along the first direction X, the second trench 242 has a second dimension L2 along the second direction Y, and the first dimension L1 is smaller than the second dimension L2.
In this embodiment, the first patterning layer 230 also exposes the surface of the second electrode film 223 on the logic region B.
Since the first patterning layer 230 exposes the second electrode film 223 on the logic region B, a first electrode layer, a magnetic tunnel structure on the surface of the first electrode layer, and a second electrode layer on the surface of the magnetic tunnel structure are formed on the surface of the storage region a, that is, a device with a storage function is formed on the surface of the storage region a.
In this embodiment, the first patterning layer 230 is used as a mask to etch a portion of the first electrode film 221, the magnetic tunnel film 222, and the second electrode film 223 until the surface of the etch stop layer 211 is exposed, and a first trench 241 and a second trench 242 are formed in the initial magnetic tunnel structure, where the bottom of the first trench 241 and the bottom of the second trench 242 are flush with the surface of the etch stop layer 211.
Because the etching stop layer 211 is located on the surface of the logic region B, and the etching stop layer 211 has a certain thickness, the first patterning layer 230 is used as a mask to etch the first electrode film 221, the magnetic tunnel film 222 and the second electrode film 223 until the surface of the etching stop layer 211 is exposed, so that a part of the first electrode film 221 can be reserved on the surface of the first conductive layer 201 in the process of forming the first trench 241 and the second trench 242 in the initial magnetic tunnel structure, thereby avoiding etching the surface of the first conductive layer 201; on the other hand, etching damage is not caused to the surface of the substrate 200 of the logic region B and the surface of the second conductive layer 202, so that the influence on the logic region B is reduced. In summary, the method is advantageous for improving the performance of the formed semiconductor structure.
Next, a mask layer is formed on the sidewall surface and the bottom surface of the first trench and the sidewall surface of the second trench, and the first trench is filled with the mask layer, specifically, refer to fig. 14 to 16 for a process of forming the mask layer.
Referring to fig. 14, fig. 14 is a schematic diagram based on fig. 12, wherein a masking material layer 250 is formed in the first trench 241 (shown in fig. 13), the sidewall surface and the bottom surface of the second trench 242 (shown in fig. 13), and the top surface of the initial magnetic tunnel structure.
The first trench 241 has a first dimension L1 along the first direction X, the second trench 242 has a second dimension L2 along the second direction Y, and the first dimension L1 is smaller than the second dimension L2, so that the mask material layer 240 can fill the first trench 241 while not filling the second trench 242.
The material of the mask material layer 250 is different from that of the initial magnetic tunnel structure, so that the etching loss of the initial magnetic tunnel structure is small in the process of subsequently etching the mask material layer 250 back to form a mask layer. And after a mask layer is formed subsequently, the mask layer is used as the mask, and etching loss of the mask layer is avoided in the process of etching the initial magnetic tunnel structure, so that the formed magnetic tunnel structure has good appearance, and the performance of the formed semiconductor structure is improved.
The material of the mask material layer 250 is different from the material of the etching stop layer 211, so that in the process of subsequently etching the mask material layer 250 to form a mask layer, etching loss on the etching stop layer 211 is avoided, the etching stop layer 211 can well protect the surface of the logic region B, and the performance of the formed semiconductor structure is improved.
The material of the masking material layer 250 includes: titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the mask material layer 250 is titanium nitride.
The process of forming the masking material layer 250 includes: and (5) an atomic layer deposition process.
The reason why the atomic layer deposition process is selected to form the mask material layer 250 is that: the atomic layer deposition process has good step coverage, so that the formed mask material layer 250 has uniform thickness, and the subsequent back etching of the mask material layer 250 is facilitated to form a mask layer with good thickness uniformity.
Referring to fig. 15 and 16, fig. 15 is a schematic view based on fig. 14, the view directions of fig. 16 and 8 are the same, the masking material layer 250 is etched back until the bottom surface of the second trench 242 and the top surface of the initial magnetic tunnel structure are exposed, and the masking layer 251 is formed in the first trench 241 and on the sidewall surface of the second trench 242.
The mask layer 251 is used for being used as a mask for etching the initial magnetic tunnel structure to form the magnetic tunnel structure.
In this embodiment, the mask layer 251 exposes the top surface of the first patterned layer 230.
The mask layer 251 fills the first trench 241, and the mask layer 251 is used as a mask to etch the initial magnetic tunnel structure until the surface of the substrate 200 is exposed, so that the initial magnetic tunnel structure at the bottom of the first trench 241 cannot be etched due to the protection of the mask layer 251 in the first trench 241, and further the surface of the first conductive layer 201 cannot be etched, thereby avoiding the influence on the conductivity of the first conductive layer 201, and being beneficial to improving the performance of the formed semiconductor structure.
The mask layer 251 is formed by etching back the mask material layer 250, and the material of the mask layer 251 includes: titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the mask layer 251 is titanium nitride.
Referring to fig. 17 and 18, fig. 17 is a schematic diagram based on fig. 15, the view directions of fig. 18 and 8 are the same, the mask layer 251 is used as a mask, the initial magnetic tunnel structure is etched until the surface of the substrate 200 is exposed, and a magnetic tunnel structure (not shown) is formed on the surface of the first conductive layer 201.
In this embodiment, the mask layer 251 and the first patterning layer 230 are used as masks, the first electrode film 221 at the bottom of the second trench 242 is etched until the surface of the substrate 200 is exposed, and the magnetic tunnel structure is formed on the surface of the first conductive layer 201.
The magnetic tunnel structure includes: a first electrode layer 261 on the surface of the first conductive layer 201; a magnetic tunnel junction 262 on a portion of the surface of the first electrode layer 261; a second electrode layer 263 located on a surface of the magnetic tunnel junction 262; the material of the first electrode layer 261 includes: one or a combination of more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum; the material of the second electrode layer 263 includes: one or a combination of more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum.
The magnetic tunnel junction 262 includes: a lower electromagnetic layer (not shown) on the surface of the first electrode layer 261, an insulating layer (not shown) on the surface of the lower electromagnetic layer (not shown), and an upper electromagnetic layer (not shown) on the surface of the insulating layer.
And etching the initial magnetic tunnel structure by taking the mask layer 251 as a mask until the surface of the substrate 200 is exposed, and continuing to perform over-etching by taking the mask layer 251 as a mask.
In this embodiment, the mask layer 251 and the first patterned layer 230 are used as masks to etch the first electrode film 221 at the bottom of the second trench 242, and after the surface of the substrate 200 is exposed, the mask layer 251 and the first patterned layer 230 are continuously used to perform over-etching.
Through the over-etching treatment, the first electrode layers 261 formed on the adjacent first conductive layers 201 can be fully isolated, so that the electric crosstalk between the adjacent memory devices is avoided, and the performance of the formed semiconductor structure is better. In this embodiment, after forming the magnetic tunnel structure, the method further includes: the first patterned layer 230 is removed.
In other embodiments, after forming the magnetic tunnel structure, the method further includes: and removing the second patterned layer and the mask layer.
Referring to fig. 19, fig. 19 is a schematic diagram based on fig. 17, after the magnetic tunnel structure is formed, a protective layer 270 is formed on the surface of the substrate 200 and the sidewall surface and the top surface of the magnetic tunnel structure.
In this embodiment, the protection layer 270 is formed on the surface of the substrate 200, the sidewall surface of the mask layer 261, and the top surface and the sidewall surface of the magnetic tunnel structure.
The material of the protective layer 270 is different from that of the first dielectric layer formed later; the material of the protective layer 270 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the protection layer 270 is silicon oxide.
In other embodiments, the protective layer may not be formed.
Referring to fig. 20, fig. 20 is a schematic view based on fig. 19, wherein a first dielectric layer 280 is formed on the substrate 200, and the first dielectric layer 280 covers the top surface and the sidewall surface of the magnetic tunnel structure; a plug 281 and a third conductive layer 282 are formed in the first dielectric layer 280, the third conductive layer 282 contacts with the surface of the second electrode layer 263, the third conductive layer 282 contacts with the top surface of the plug 281, and the plug 281 is located on the surface of the second conductive layer 202 in the logic region B.
In this embodiment, the first dielectric layer 280 is located on the surface of the protection layer 270.
The material of the plug 281 includes: one or more of copper, tungsten, aluminum, titanium and tantalum.
The material of the third conductive layer 282 includes: one or more of copper, tungsten, aluminum, titanium and tantalum.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a storage area, a plurality of first conductive layers are arranged in the storage area, the top surfaces of the first conductive layers are exposed out of the substrate, the first conductive layers extend along a first direction, and the first conductive layers are arranged along a second direction;
forming an initial magnetic tunnel structure on the surface of the first conductive layer and the surface of the substrate;
forming a first trench and a second trench in the initial magnetic tunnel structure, wherein the second trench extends along a first direction, the first trench is located between adjacent second trenches, the first trench extends along a second direction, the first trench is located on the first conductive layer, the second trench is located on the substrate, the first trench has a first size along the first direction, the second trench has a second size along the second direction, and the first size is smaller than the second size;
forming a mask layer on the surface of the side wall and the bottom of the first groove and the surface of the side wall of the second groove, wherein the mask layer is not filled in the second groove while filling the first groove;
and etching the initial magnetic tunnel structure by taking the mask layer as a mask until the surface of the substrate is exposed, and forming the magnetic tunnel structure on the surface of the first conductive layer.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises: the logic area is provided with a second conducting layer, and the substrate exposes the top surface of the second conducting layer; the initial magnetic tunnel structure exposes a logic region surface.
3. The method of forming a semiconductor structure of claim 1, wherein the method of forming the initial magnetic tunnel structure comprises: forming a first electrode film on the surface of the first conductive layer and the surface of the substrate; forming a magnetic tunnel film on the surface of the first electrode film; forming a second electrode film on the surface of the magnetic tunnel film; the first trench top surface and the second trench top surface are lower than a top surface of the first electrode film.
4. The method of forming a semiconductor structure of claim 3, wherein the method of forming the first trench and the second trench comprises: forming a first patterning layer on the surface of the second electrode film on part of the storage region, wherein the pattern in the first patterning layer corresponds to the positions and the sizes of the first groove and the second groove; and etching parts of the first electrode film, the magnetic tunnel film and the second electrode film by taking the first patterning layer as a mask to expose the surface of the first electrode film, and forming a first groove and a second groove in the initial magnetic tunnel structure.
5. The method of forming a semiconductor structure of claim 1, wherein the method of forming a mask layer comprises: forming a layer of masking material within the first trench and on the second trench sidewall and bottom surfaces and on the initial magnetic tunnel structure top surface; and etching the mask material layer back until the bottom surface of the second groove and the top surface of the initial magnetic tunnel structure are exposed, and forming the mask layer in the first groove and on the side wall surface of the second groove.
6. The method of forming a semiconductor structure of claim 5, wherein the process of forming the layer of masking material comprises: and (3) an atomic layer deposition process.
7. The method of forming a semiconductor structure according to claim 1, wherein a material of the mask layer is different from a material of the initial magnetic tunnel structure; the mask layer is made of materials including: titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
8. The method of forming a semiconductor structure of claim 4, further comprising: and forming an etching stop layer on the surface of the logic area before forming the initial magnetic tunnel structure.
9. The method of forming a semiconductor structure of claim 8, wherein the method of forming the etch stop layer comprises: forming a stop material layer on the surfaces of the storage area and the logic area; forming a second patterned layer on the surface of the stop material layer on the logic region, wherein the second patterned layer exposes the surface of the stop material layer on the storage region; and etching the stop material layer by taking the second patterning layer as a mask until the surface of the substrate is exposed to form the etching stop layer.
10. The method of forming a semiconductor structure of claim 8, wherein a material of the etch stop layer is different from a material of the mask layer; the material of the etching stop layer is different from the materials of the substrate, the first conducting layer and the second conducting layer; the material of the etching stop layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
11. The method of claim 8, wherein the first patterning layer is used as a mask to etch a portion of the first electrode film, the magnetic tunnel film, and the second electrode film until the surface of the etch stop layer is exposed, and wherein a first trench and a second trench are formed in the initial magnetic tunnel structure, wherein the bottom of the first trench and the bottom of the second trench are flush with the surface of the etch stop layer.
12. The method of forming a semiconductor structure of claim 2, further comprising: after the magnetic tunnel structure is formed, forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the top surface and the side wall surface of the magnetic tunnel structure; and forming a plug and a third conducting layer in the first dielectric layer, wherein the third conducting layer is contacted with the surface of the second electrode layer, the third conducting layer is contacted with the top surface of the plug, and the plug is positioned on the surface of the second conducting layer in the logic area.
13. The method for forming a semiconductor structure according to claim 1, wherein the initial magnetic tunnel structure is etched with the mask layer as a mask, and after the substrate surface is exposed, the overetching is performed with the mask layer as a mask.
14. The method of forming a semiconductor structure of claim 12, further comprising: and after the magnetic tunnel structure is formed and before the first dielectric layer is formed, protective layers are formed on the surface of the substrate, the surface of the side wall and the top surface of the mask layer and the surface of the top of the magnetic tunnel structure.
15. The method of forming a semiconductor structure of claim 14, wherein the protective layer and the first dielectric layer are different materials; the material of the protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
16. The method of forming a semiconductor structure according to claim 1, wherein a material of the first conductive layer comprises: one or a combination of more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum; the material of the second conductive layer includes: copper, cobalt, tungsten, aluminum, titanium nitride, tantalum.
17. The method of forming a semiconductor structure of claim 1, wherein the magnetic tunnel structure comprises: the first electrode layer is positioned on the surface of the first conductive layer; a magnetic tunnel junction located at a portion of the first electrode layer surface; a second electrode layer on a surface of the magnetic tunnel junction; the material of the first electrode layer includes: one or a combination of more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum; the material of the second electrode layer includes: one or more of copper, cobalt, tungsten, aluminum, titanium nitride and tantalum.
18. The method of forming a semiconductor structure of claim 17, wherein the magnetic tunnel junction comprises: the electromagnetic shielding film comprises a lower electromagnetic layer positioned on the surface of the first electrode layer, an insulating layer positioned on the surface of the lower electromagnetic layer and an upper electromagnetic layer positioned on the surface of the insulating layer.
19. The method of forming a semiconductor structure of claim 2, wherein the substrate comprises: the first conducting layer and the second conducting layer are positioned in the second dielectric layer; logic devices are arranged in the logic area and in the second medium layer on the surface of the logic area.
20. A semiconductor structure formed using the formation method of any one of claims 1 to 19.
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