CN110061048B - MOS field-controlled thyristor based on Schottky diode and manufacturing method thereof - Google Patents
MOS field-controlled thyristor based on Schottky diode and manufacturing method thereof Download PDFInfo
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42308—Gate electrodes for thyristors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66363—Thyristors
- H01L29/66371—Thyristors structurally associated with another device, e.g. built-in diode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
Abstract
The invention discloses an MOS field-controlled thyristor based on a Schottky diode, which comprises anode metal, a P + anode positioned on the anode metal, an N FS layer positioned on the P + anode, and an N-base area positioned on the N FS layer; a first type cathode metal, a second type cathode metal and a gate dielectric layer are distributed on the surface of the top layer of the N-base area; a polysilicon gate is arranged above the gate dielectric layer; the top end of the N-base area is provided with a P well area close to the left, the top end of the P well area is provided with an N well area close to the right, and the top end of the N well area is provided with a P + area close to the right; a portion of the N well and P + regions underlies the polysilicon gate. The invention can solve the problems of repeated charging and discharging in the off-FET in the MCT turn-off process, and reduce the turn-off time of the MCT in the pulse circuit; meanwhile, the current concentration at the metal edge of the MCT cathode is relieved, and the reliability of the device is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a Schottky diode-based MOS field-controlled thyristor and a manufacturing method thereof.
Background
The pulse power switch is a very critical link in the pulse power system, and the performance of the switch usually limits the performance of the pulse power system, such as peak power or repetition frequency. Compared with traditional switching devices such as a thyristor and the like, the semiconductor power device has the advantages of high efficiency, high repetition frequency, portability, low cost and the like. Among them, MOS field controlled thyristors (MCTs), such semiconductor power devices are receiving a great deal of attention in pulse power applications. The MCT includes a MOS portion for control and a thyristor portion for operation in a high voltage, high power environment. After MCT is turned on, the conductance modulation effect exists near the cathode and the anode, so the on-resistance is extremely small; meanwhile, the MCT has a thyristor structure as the working part and has no current saturation characteristic, so that the MCT can tolerate larger peak current and larger current rising rate, and therefore the MCT has obvious advantages in pulse power application.
The reliability of power semiconductor devices has always been an important indicator of how good a device is to be weighed. In pulsed power systems, the switching device is subjected to a large current pulse oscillation process. Fig. 1 is a schematic structural diagram of a conventional MCT device, an equivalent circuit diagram of which is shown in fig. 2, and in fig. 1, NFS represents an N-type field stop layer, also called an N-type buffer layer, whose concentration is higher than that of an N-base region, and mainly functions to improve the voltage endurance characteristics of the device. This structure is used in both conventional MCT and IGBT devices. Under the influence of the conductive modulation effect, a large number of holes are injected into the MCT device after the MCT device is turned on. These excess holes flow through the N-base region and are collected in the P well region. When the MCT device is turned off, the redundant holes are released through a field effect transistor (abbreviated as off-FET) consisting of a P well area, an N well area and a P + area, and then the MCT device can be recovered to the off state. But the off-FET undergoes repeated charging and discharging processes under the influence of the oscillating current in the pulsing circuit. The charging process reduces the efficiency of discharging excess holes and extends the time for the MCT to return to the off state. In addition, when the MCT is turned off, the current density flowing through the off-FET is two orders of magnitude higher than that when the MCT is in normal operation, the current distribution at the contact interface between the metal electrode and the semiconductor of the off-FET is not uniform, and particularly, the current concentration at the metal edge close to the channel is obvious, and the current density at the position can generate an extremely high peak value point. The MCT is not only influenced by pulse current in the turn-off process, but also has a current concentration phenomenon, so that the power loss has serious non-uniformity on the spatial distribution, and the fatigue damage of a device is easily caused.
Disclosure of Invention
In order to solve the technical problems, the invention provides the schottky diode-based MOS field-controlled thyristor with a simple structure and high reliability, and provides the manufacturing method thereof.
The technical scheme for solving the problems is as follows: a MOS field-controlled thyristor based on a Schottky diode comprises an anode metal, a P + anode positioned on the anode metal, an N FS layer positioned on the P + anode, and an N-base region positioned on the N FS layer; a first type cathode metal, a second type cathode metal and a gate dielectric layer are sequentially distributed on the surface of the top layer of the N-base area from left to right; the first type cathode metal and the second type cathode metal are separated by an insulating medium; a polysilicon gate is arranged above the gate dielectric layer; the top end of the N-base area is provided with a P well area close to the left, the top end of the P well area is provided with an N well area close to the left, and the top end of the N well area is provided with a P + area close to the right; and a part of the N well and the P + region are positioned below the polysilicon gate, the P + region is not contacted with the first type of cathode metal, and the contact width of the P + region and the second type of cathode metal is 0.5-40 mu m.
In the MOS field-controlled thyristor based on the Schottky diode, the work function of the second type of cathode metal is smaller than that of the P + region, so that Schottky contact is formed.
A manufacturing method of an MOS field control thyristor based on a Schottky diode comprises the following steps:
the first step is as follows: selecting a substrate, and epitaxially preparing an N-base region;
the second step is that: preparing a gate dielectric layer on the right side of the upper surface of the N-base region;
the third step: depositing polycrystalline silicon on the upper surface of the gate dielectric layer, and etching the polycrystalline silicon to form a polycrystalline silicon gate; then, an insulating medium expansion gate dielectric layer is deposited, so that the expanded gate dielectric layer surrounds the polysilicon gate;
the fourth step: forming a P well area on the left side of the upper layer of the N-base area by adopting an ion implantation and high-temperature diffusion junction pushing process;
the fifth step: forming an N well area in the P well area by adopting an ion implantation and high-temperature diffusion junction pushing process;
and a sixth step: forming a P + area on the upper surface of the N well area close to the right by adopting an ion implantation process;
the seventh step: forming an N FS layer on the lower layer of the N-base region by adopting an ion implantation and high-temperature diffusion knot pushing process;
eighth step: forming a P + anode on the lower layer of the N-base by adopting an ion implantation process;
the ninth step: back metallization, namely depositing a metal layer on the lower surface of the N-base to form anode metal;
the tenth step: depositing a metal layer on the left side of the upper surface of the N-base region, etching and annealing to form first type cathode metal, wherein the P + region is not in contact with the first type cathode metal;
the eleventh step: depositing an insulating medium on the upper surface area of the N-base region, and forming the insulating medium by etching;
the twelfth step: and depositing a metal layer on the upper surface of the N-base region to form a second type of cathode metal, wherein the insulating medium is positioned between the first type of cathode metal and the second type of cathode metal, the polysilicon gate is positioned on the right side of the second type of cathode metal, and the contact width between the P + region and the second type of cathode metal is 0.5-40 mu m.
In the fifth step of the manufacturing method of the MOS field-controlled thyristor based on the Schottky diode, the doping concentration of the part of the N well region, which is positioned below the polysilicon gate, is 2 orders of magnitude smaller than that of the rest part.
In the eighth step of the method for manufacturing the MOS field-controlled thyristor based on the Schottky diode, the junction depth of the P + anode is smaller than that of the N FS layer.
The invention has the beneficial effects that: the invention provides an MOS field-controlled thyristor based on a Schottky diode, which can solve the problems of repeated charging and discharging in an off-FET in the turn-off process of an MCT (metal-oxide-semiconductor transistor), and reduce the turn-off time of the MCT in a pulse circuit; meanwhile, the current concentration at the metal edge of the MCT cathode is relieved, and the reliability of the device is improved.
Drawings
Figure 1 is a schematic diagram of a conventional MCT structure.
Figure 2 is an equivalent circuit diagram of a conventional MCT.
Figure 3 is a schematic diagram of the structure of an MCT of the present invention.
Figure 4 is an equivalent circuit diagram of an MCT of the present invention.
Figure 5 is a schematic diagram of the structure of a conventional MCT used in simulations.
Figure 6 is a simulation graph of anode current for a conventional MCT during pulsed discharge and turn-off.
Figure 7 is a simulation graph of anode current for a MCT of the present invention during pulsed discharge and shutdown.
Figure 8 is a simulated comparison of the second cathode current at pulsed discharge and shutdown for a conventional MCT and the MCT structure proposed by the present invention.
FIG. 9 is a graph of the current distribution in the off-FETs during turn-off of a conventional MCT device.
FIG. 10 is a graph of the current distribution in the off-FETs during turn-off of the MCT device of the present invention.
Fig. 11 is a graph showing the distribution of electric field intensity in the horizontal direction of 0.02 μm below the second type of cathode metal of the conventional MCT device and the MCT device proposed by the present invention.
FIG. 12 shows the off-current density of a conventional MCT device and the MCT device of the present invention at 142A/cm2A comparative plot of the current density at 0.02 μm below the second type of cathode metal.
Detailed Description
The invention is further described below with reference to the figures and examples.
As shown in fig. 3, a schottky diode-based MOS field-controlled thyristor is characterized in that: the anode comprises an anode metal 600, a P + anode 101 positioned on the anode metal 600, an N FS layer 102 positioned on the P + anode 101, and an N-base area 103 positioned on the NFS layer 102; a first type cathode metal 400, a second type cathode metal 500 and a gate dielectric layer 301 are sequentially distributed on the surface of the top layer of the N-base region 103 from left to right; the first cathode metal 400 and the second cathode metal 500 are separated by an insulating medium 302; a polysilicon gate 200 is arranged above the gate dielectric layer 301; a P well area 104 is arranged close to the left at the top end of the N-base area 103, an N well area 105 is arranged close to the left at the top end of the P well area 104, and a P + area 106 is arranged close to the right at the top end of the N well area 105; a portion of the N well region 105 and the P + region 106 are located below the polysilicon gate 200.
The P + region 106 is not in contact with the first type of cathode metal 400. The contact width of the P + region 106 and the second type cathode metal 500 is 0.5 μm to 40 μm. The second type of cathode metal 500 has a work function less than the work function of the P + region 106, forming a schottky contact.
A manufacturing method of an MOS field control thyristor based on a Schottky diode is characterized in that: the method comprises the following steps:
the first step is as follows: the substrate is selected and the N-base region 103 is epitaxially fabricated.
The second step is that: and preparing a gate dielectric layer 301 on the right side of the upper surface of the N-base region 103.
The third step: depositing polysilicon on the upper surface of the gate dielectric layer 301, and etching the polysilicon to form a polysilicon gate 200; and then depositing an insulating medium to expand the gate dielectric layer 301, so that the expanded gate dielectric layer 301 surrounds the polysilicon gate 200.
The fourth step: and forming a P well area 104 on the left side of the upper layer of the N-base area 103 by adopting ion implantation and a high-temperature diffusion junction-pushing process.
The fifth step: forming an N well region 105 in the P well region 104 by adopting ion implantation and a high-temperature diffusion junction-pushing process; the N well region 105 has a doping concentration 2 orders of magnitude less in the portion below the polysilicon gate 200 than in the remaining portion.
And a sixth step: an ion implantation process is adopted to form a P + region 106 on the upper surface of the N well region 105 close to the right.
The seventh step: an N FS layer 102 is formed on the lower layer of the N-base region 103 by adopting ion implantation and a high-temperature diffusion junction-pushing process.
Eighth step: forming a P + anode 101 on the lower layer of the N-base103 by adopting an ion implantation process; the junction depth of the P + anode 101 is smaller than the junction depth of the N FS layer 102.
The ninth step: back metallization, a metal layer is deposited on the bottom surface of the N-base103 to form the anode metal 600.
The tenth step: a metal layer is deposited on the left side of the upper surface of the N-base region 103, the first type cathode metal 400 is formed through etching and annealing, and the P + region 106 is not in contact with the first type cathode metal 400.
The eleventh step: an insulating dielectric is deposited on the upper surface area of the N-base region 103 and etched to form an insulating dielectric 302.
The twelfth step: a metal layer is deposited on the upper surface of the N-base region 103 to form a second type cathode metal 500, the insulating medium 302 is positioned between the first type cathode metal 400 and the second type cathode metal 500, the polysilicon gate 200 is positioned on the right side of the second type cathode metal 500, and the contact width between the P + region 106 and the second type cathode metal 500 is 0.5-40 μm.
The cathode metal of the off-FET of the traditional MCT is made into Schottky contact, meanwhile, the cathode metal of the parasitic thyristor is kept to be ohmic contact, the structural schematic diagram is shown in figure 3, and the equivalent circuit diagram is shown in figure 4. Comparing fig. 4 and fig. 2, it can be seen that the MCT structure of the present invention forms a schottky diode between the off-FET and the cathode metal. The working principle of the structure is as follows:
conventional MCT devices turn off the gate voltage from a positive voltage to a negative voltage, turning on the off-FETs at the same time as turning off the on-FETs. At this time, when the MCT device is turned on in the forward direction, holes injected into the P well region 104 due to the minority injection effect flow out of the MCT via the off-FET composed of the P well region 104, the N well region 105, and the P + region 106, thereby returning the MCT to a voltage-resistant state. When the MCT is used as a switch of the pulse circuit, because the current excited after the pulse circuit is switched on has extremely high di/dt, the current does not disappear immediately but gradually decreases in the switching-off process of the MCT. This causes a periodically varying direction of current to flow through the off-FETs, which undergo repeated charging and discharging processes, prolonging the time to extract excess holes, i.e., prolonging the turn-off time of the MCT. In the MCT structure of the present invention, the P + region 106 is the anode region of the schottky diode because the work function of the second type cathode metal 500 is less than the work function of the P + region 106, causing the surface energy band of the P + region 106 to bend downward, forming a barrier for holes. The current is subject to the rectifying action of the schottky diode and can only flow from the off-FET to the second type cathode metal 500. The Schottky diode can prevent a circuit from charging an off-FET, promote redundant holes to flow out of the MCT in a single direction, and greatly shorten the turn-off time of the MCT device.
On the other hand, during turn-off of a conventional MCT device, its off-FET current flows out of the P + region 106 from the cathode metal termination location, at which point a significant current density peak occurs. Current concentration can accelerate device performance degradation and reduce device reliability. In the MCT structure of the present invention, the schottky junction affects the electric field distribution of the P + region 106. The new electric field can help holes flow out of P + region 106 beyond the cathode metal termination point, away from the cathode metal termination point. Thus, the current is uniform, and the current concentration intensity is well weakened.
Example (b):
the simulation comparison is carried out by taking a traditional MCT structure with the withstand voltage of 1200V and the MCT structure of the invention as an example, so as to intuitively show that the invention has well solved the problem of long circuit time of a conventional MCT turn-off pulse circuit, the MCT structure of the invention is schematically shown in FIG. 3, an equivalent circuit diagram is shown in FIG. 4, in order to eliminate some potential influencing factors, the traditional MCT structure shown in FIG. 5 and an equivalent circuit thereof are adopted in the simulation, the half-cell width of each MCT is 14 mu m, the doping concentration of a P + region is 4 × 19cm-3The remaining structural parameters are the same, except for the type of contact of the cathode metal. In the MCT of the present invention, the second cathode metal 500 in contact with the P + region has a work function of 4.8eV and a width of 1.4 μm, and the schottky diode formed has a barrier height of approximately 0.2V. Fig. 6 shows the variation of the anode current in the pulse circuit simulation of the conventional MCT device. The grid voltage is firstly changed from negative voltage to positive voltage, so that the circuit is conducted, and periodic pulse current is generated; the gate voltage then changes from a positive voltage to a negative voltage, starting to shut down the circuit, and the peak of the pulse current begins to fall rapidly. The anode current variation of the MCT structure of the present invention in the same simulation circuit is shown in figure 7. During the circuit conducting period, the anode current curve of the MCT of the invention is the same as the anode voltage curve of the traditional MCT, which shows that the MCT of the invention has the same forward conducting characteristic as the traditional MCT. In the process of turning off the circuit, the anode current peak value falling speed of the MCT is obviously higher than that of the traditional MCT; the anode current of the MCT of the present invention is reduced to 10% of the maximum current with only 550ns, while the conventional MCT requires 1440ns to reduce the same current. The MCT of the present invention and the conventional MCT second cathode current pair are shown in figure 8. The MCT second cathode of the invention is conducted in a half pulse period only, and the current dropping speed is faster than that of the traditional MCT second cathode, which shows that the MCT provided by the invention can turn off a pulse circuit more quickly just because of the rectifying action of a Schottky diode.
Current concentration occurs in the P + region 106 during turn-off, with the conventional MCT turn-off current profile shown in figure 9 and the MCT turn-off current profile of the present invention shown in figure 10. As is apparent from comparing fig. 9 and 10, the current distribution in the P + region 106 of the MCT of the present invention is more uniform. Fig. 11 shows the variation of the electric field strength with the leftmost end of the contact surface of the second type cathode metal 500 and the P + region 106 as the origin and the positive direction of the x axis horizontally to the left, where x ═ 1.4 μm corresponds to the right end point of the second type cathode metal 500. The MCT of the present invention has a more uniform electric field distribution under the entire second type cathode metal 500, i.e., in the range of x 0 to x 1.4 μm, but the electric field strength of the conventional MCT rapidly decays to 0. This electric field pointing in the negative x-axis direction helps holes to cross the right end point of the second type cathode metal 500, thereby reducing the current density near the right end point of the second type cathode metal 500. Fig. 12 shows the current density distribution of the P + region 106 for both devices. Compared with the conventional MCT device, the MCT of the present invention reduces the current density concentration rate near the right end point of the second type cathode metal 500 from 85.8% to 15.7%, so that the current is more uniformly distributed under the second type cathode metal 500. This means that the power dissipation becomes more evenly distributed over space and the reliability of the device is higher.
Claims (4)
1. The utility model provides a MOS field control thyristor based on schottky diode which characterized in that: comprises an anode metal (600), a P + anode (101) positioned on the anode metal (600), an N FS layer (102) positioned on the P + anode (101), and an N-base region (103) positioned on the NFS layer (102); a first type cathode metal (400), a second type cathode metal (500) and a gate dielectric layer (301) are sequentially distributed on the surface of the top layer of the N-base region (103) from left to right; the first type cathode metal (400) and the second type cathode metal (500) are separated by an insulating medium (302); a polysilicon gate (200) is arranged above the gate dielectric layer (301); a P well area (104) is arranged close to the left at the top end of the N-base area (103), an N well area (105) is arranged close to the left at the top end of the P well area (104), and a P + area (106) is arranged close to the right at the top end of the N well area (105); a part of the N well (105) and the P + region (106) is positioned below the polysilicon gate (200); the P + region (106) and the first type of cathode metal (400) are not in contact; the contact width of the P + region (106) and the second type cathode metal (500) is 0.5-40 mu m; the second type of cathode metal (500) has a work function less than the work function of the P + region (106), forming a schottky contact.
2. A method for manufacturing a schottky diode-based MOS field-controlled thyristor according to claim 1, characterized in that: the method comprises the following steps:
the first step is as follows: selecting a substrate, and epitaxially preparing an N-base region (103);
the second step is that: preparing a gate dielectric layer (301) on the right side of the upper surface of the N-base region (103);
the third step: depositing polysilicon on the upper surface of the gate dielectric layer (301), and etching the polysilicon to form a polysilicon gate (200); then, an insulating medium is deposited to expand the gate dielectric layer (301), so that the expanded gate dielectric layer (301) surrounds the polysilicon gate (200);
the fourth step: forming a P well area (104) on the left side of the upper layer of the N-base area (103) by adopting an ion implantation and high-temperature diffusion junction pushing process;
the fifth step: forming an N well region (105) in the P well region (104) by adopting an ion implantation and high-temperature diffusion junction pushing process;
and a sixth step: forming a P + region (106) on the upper surface of the N well region (105) close to the right by adopting an ion implantation process;
the seventh step: forming an N FS layer (102) on the lower layer of the N-base region (103) by adopting an ion implantation and high-temperature diffusion knot pushing process;
eighth step: forming a P + anode (101) on the lower layer of the N-base (103) by adopting an ion implantation process;
the ninth step: back metallization, namely depositing a metal layer on the lower surface of the N-base (103) to form an anode metal (600);
the tenth step: depositing a metal layer on the left side of the upper surface of the N-base region (103), etching and annealing to form a first type cathode metal (400), wherein the P + region (106) is not in contact with the first type cathode metal (400);
the eleventh step: depositing an insulating medium on the upper surface area of the N-base region (103), and forming an insulating medium (302) through etching;
the twelfth step: a metal layer is deposited on the upper surface of the N-base region (103) to form a second type of cathode metal (500), the insulating medium (302) is located between the first type of cathode metal (400) and the second type of cathode metal (500), the polysilicon gate (200) is located on the right side of the second type of cathode metal (500), the contact width of the P + region (106) and the second type of cathode metal (500) is 0.5-40 mu m, and the work function of the second type of cathode metal (500) is smaller than that of the P + region (106) to form Schottky contact.
3. The method for manufacturing the schottky diode-based MOS field-controlled thyristor according to claim 2, wherein: in the fifth step, the doping concentration of the part of the N well region (105) below the polysilicon gate (200) is 2 orders of magnitude smaller than that of the rest part.
4. The method for manufacturing the schottky diode-based MOS field-controlled thyristor according to claim 2, wherein: in the eighth step, the junction depth of the P + anode (101) is smaller than the junction depth of the N FS layer (102).
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