CN108899364B - MOS (metal oxide semiconductor) grid-controlled thyristor integrated with Schottky diode and preparation method thereof - Google Patents
MOS (metal oxide semiconductor) grid-controlled thyristor integrated with Schottky diode and preparation method thereof Download PDFInfo
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- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
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Abstract
The invention belongs to the technical field of power semiconductor devices, and relates to an MOS (metal oxide semiconductor) grid-controlled thyristor integrated with a Schottky diode. The invention forms a Schottky diode between a P well region and a cathode by designing the cathode of the device as a Schottky contact, wherein P is+The region can accelerate the extraction of carriers during turn-off, but does not influence the pulse performance of the device, and whether P is reserved or not can be selected according to requirements during manufacturing+And (4) a zone. The two structures can ensure that the current distribution is more uniform when the device works, the minimum current required by the latch of the device is reduced, the pulse peak current of the device is further improved under the low current, the current rise rate (di/dt) is improved, the time of the device working under the IGBT mode is shortened, the lattice temperature of the device working under the IGBT mode at the pulse discharge initial stage is effectively reduced, and the pulse characteristic of the device is further improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to a Schottky diode integrated MOS gate-controlled thyristor (SD-MCT) and a preparation method thereof.
Background
The pulse power technology is an emerging scientific technology developed in the early 60 th 20 th century due to the needs of national defense scientific research. Briefly, pulsed power technology is an electro-physical technology that rapidly compresses slowly stored energy, releasing it in pulses to a load. With the development of nuclear physics, electron beam accelerator physics, laser and plasma physics research, the pulse power technology is rapidly developed, becomes one of the most active leading-edge technologies in the world at present, has wide application prospects in the military field and the civil field, and is applied to the nuclear fusion technology, the fuse system of defense and military, and the like in the military field; the method is applied to food processing, medical treatment, wastewater treatment, waste gas treatment, ozone preparation, generator ignition, ion injection, material processing and the like in the civil field. (Yunmiwei LCC resonant pulse current source design [ D ]. Harbin university of industry 2015.)
With the expansion of the pulse application field, the pulse power switch plays a significant role as a key device of a pulse power supply. Currently, commonly used semiconductor pulse power switches include power MOSFETs, thyristors (SCRs), Insulated Gate Bipolar Transistors (IGBTs), MOS Controlled Thyristors (MCTs), and newly developed cathode-shorted gated thyristors (CS-MCTs). Each of these semiconductor pulse power switches described above has advantages and disadvantages. The bipolar power device has a conductance modulation effect inside, so that the bipolar power device has smaller conduction power consumption compared with a conventional unipolar device, but the conductance modulation degrees of different types of bipolar devices are different. The thyristor has the advantages that the conductivity modulation degree is higher and the conduction power consumption is smaller due to the positive feedback effect of the NPN tube and the PNP tube. But the thyristor has a poor di/dt capability due to the current concentration effect during turn-on. In addition, thyristors are current-controlled devices, and their driving circuits are more complex than voltage-controlled devices. The IGBT is mainly applied to a high-frequency medium pulse power supply, belongs to a voltage-controlled device and is relatively simple to drive, but the conductance modulation degree of the IGBT is limited by a reverse bias PN junction of a drift region and a P-type base region, so that the conduction power consumption of the device is relatively large; in addition, the turn-on of the IGBT is controlled by the gate voltage, and the maximum current is also limited by the saturation current. Grid-controlled thyristor (MOS-ControlledTThe thyristor-like low resistance characteristic, high di/dt capability and voltage control characteristic, but the device needs gate control signals with different signs in the switching process, resulting in more complex driving circuit (simple V a k. mos controlled thyristors (MCT's) [ C)]Electron Devices Meeting,1984International IEEE,1984: 282-285). And CS-MCT solves the contradiction, belongs to a voltage-controlled device, and has a thyristor structure with a short cathode in the interior, so that the device can be blocked when a grid is in zero bias while the device has smaller on-resistance and larger di/dt capacity, and a grid driving circuit is greatly simplified; when the working mode of the power supply is triggered by the initial IGBT mode and latched into the thyristor mode, the power supply is conducted without being controlled by grid voltage and limited by saturation current, and the current level can be improved to a greater extent; simultaneously, the current concentration phenomenon at the position of a cathode contact hole is relieved, and the lattice temperature (CS-MCT) for single-order reactive pulse applications [ C-W, et al].ISPSD,201628th International Symposiumon.IEEE,2016:311-314.)。
Disclosure of Invention
Aiming at the CS-MCT structure, the invention provides a novel MOS gate-controlled thyristor structure integrated with a Schottky diode, which is named as SD-MCT. The cathode of the device is designed to be in Schottky contact, so that a Schottky diode is formed between the P well region and the cathode, the structure can enable the current distribution of the device to be more uniform during working, the minimum current required by latching of the device is reduced, the pulse peak current of the device is further improved under the small current, the current rise rate (di/dt) is improved, the time of the device working under an IGBT mode is shortened, the lattice temperature of the device working under the IGBT mode at the initial pulse discharge stage is effectively reduced, and the pulse characteristic of the device is further improved.
The technical scheme of the invention is as follows:
a first MOS grid-controlled thyristor integrated with a Schottky diode has a cellular structure comprising an anode 1, a P + anode region 2 and a drift region 3 which are sequentially stacked from bottom to top; the upper layer of the drift region 3 is provided with a P well region 4, the upper layer of the P well region 4 is provided with 2N well regions 5 which are symmetrically arranged along the vertical centerline of the device and a P which is positioned on the upper layer of the N well region 5+ Region 6, and P+Region 6 is near the device gate; two ends of the upper surface of the drift region 3 are respectively provided with a gate oxide layer 7, and the gate oxide layers 7 extend to cover parts of the upper surfaces of the N well region 5 and the P + region 6 along the upper surface of the P well region 4; the gate oxide layer 7 is provided with a polysilicon gate 8 and gate oxides at two sidesThe layer 7 and the polysilicon gate 8 are symmetrically distributed along the vertical central line of the device; the surface of the device between the gate oxide layers 7 on two sides is covered with cathode metal 9 of Schottky contact, and the upper surface of the polysilicon gate 8 and the cathode metal 9 are filled with an isolation medium for isolation.
Further, by setting the doping concentration of the P-well region 4, a schottky diode is formed between the P-well region 4 and the cathode 9.
In the above scheme, wherein P+The region 6 can accelerate the extraction of carriers during the turn-off process, but does not influence the pulse performance of the device, and whether P is reserved or not can be selected according to the requirement during the manufacture process+And a zone 6. If P+And the region 6 is removed, so that the MOS gate-controlled thyristor of the second integrated Schottky diode is obtained.
Further, the gate structure may be a planar gate or a trench gate.
Compared with the existing CS-MCT structure, the current distribution of the device during working is more uniform, so that the minimum current required by the device latch is reduced, the time of the device working in an IGBT mode is shortened, the device is latched into a thyristor mode more quickly, the conductance modulation effect is enhanced, the on resistance of the device is reduced, the current rise rate (di/dt) is improved, the pulse peak current of the device is further improved under low current, the maximum lattice temperature of the device during pulse discharge is reduced, and the pulse characteristic of the device is comprehensively improved.
Drawings
FIG. 1 is a schematic two-dimensional structure of a conventional CS-MCT;
FIG. 2 is an equivalent circuit diagram of a prior art CS-MCT;
FIG. 3 is a schematic two-dimensional structure of a first SD-MCT according to the present invention;
FIG. 4 is an equivalent circuit diagram of a first SD-MCT according to the present invention;
FIG. 5 is a schematic two-dimensional structure of a second SD-MCT according to the present invention;
FIG. 6 is an equivalent circuit diagram of a second SD-MCT according to the present invention;
FIG. 7 is a schematic diagram of the structure after the fabrication of the N-drift region in the fabrication process flow of the present invention;
FIG. 8 is a schematic diagram of a structure after a gate oxide layer is formed in a fabrication process flow of the present invention;
FIG. 9 is a schematic structural diagram of a gate electrode formed by depositing a polysilicon/metal layer on a gate oxide layer and etching the polysilicon/metal layer in the process flow of the present invention;
FIG. 10 is a schematic structural diagram of a P-well region formed by injecting P-type impurities through ion implantation in the process flow of the present invention;
FIG. 11 is a schematic structural diagram of an N-well region formed by ion implantation of N-type impurity push-junction in the process flow of the present invention;
FIG. 12 shows P-type impurity push junction formation by ion implantation in the process flow of the present invention+A schematic of the structure of the region;
FIG. 13 is a schematic structural diagram of a process flow of the present invention in which a BPSG insulating dielectric layer is deposited on the front surface and a contact hole is etched;
FIG. 14 is a schematic view of a front side metallization structure of a fabrication process flow of the present invention;
FIG. 15 is a schematic structural diagram of an anode region formed by P-type impurity implantation after back thinning in the manufacturing process flow of the present invention;
FIG. 16 is a schematic view of a back side metalized structure in a process flow of the present invention;
FIG. 17 shows the second SD-MCT device of the present invention after latch-up (current density 600A/cm)2) A hole current vector distribution diagram and a hole density distribution diagram of (a);
FIG. 18 shows the prior art CS-MCT device after latching (current density 600A/cm)2) A hole current vector distribution diagram and a hole density distribution diagram of (a);
FIG. 19 shows a second SD-MCT structure according to the present invention and a conventional CS-MCT structure at a current density of 600A/cm2Comparing hole concentration distribution at PN junctions of the N well region and the P well region;
FIG. 20 shows the latch trigger current J of the second SD-MCT structure and the existing CS-MCT structure under different cell widthstrA simulation comparison graph of (1);
FIG. 21 is a graph showing a comparison of simulation of anode current during pulse discharge at a low current for the second SD-MCT structure according to the present invention and the conventional CS-MCT structure;
FIG. 22 is a simulated comparison graph of the maximum lattice temperature of the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure in a pulsed discharge at a small current.
Detailed Description
The invention is described in detail below with reference to the attached drawing
Fig. 1 is a schematic diagram of a cell structure of a conventional CS-MCT device, and an equivalent circuit diagram thereof is shown in fig. 2. The cathode in the existing CS-MCT structure is made into a Schottky contact, the structure schematic diagram of the unit cell is shown in figure 3, and the equivalent circuit diagram is shown in figure 4. Compared with the equivalent circuit of the CS-MCT structure (see figure 2), the first SD-MCT removes P at a contact hole on the basis of the existing CS-MCT+Doping to form Schottky contact between the P well region and the cathode, namely integrating a Schottky diode between the P well region and the cathode, wherein the structure has the working principle that:
applying a forward bias voltage ON the anode, injecting holes into the drift region from the anode, turning ON the ON-FET along with the increase of the gate voltage when the gate voltage reaches a threshold voltage, allowing electrons to flow into the drift region from the cathode, and reducing the potential of the drift region, thereby promoting the injection of the holes into the drift region from the anode and flowing through the P-well region to enter the cathode electrode, wherein the device works in an IGBT mode at the stage; because the P well region is wider and not very high in concentration, the equivalent resistance of the P well region is larger, and a voltage drop is generated in the P well region when holes flow through the P well region, theoretically, when the voltage drop exceeds the starting voltage of a PN junction between the P well region and the N well region by 0.7V, the P well region and the N well region are conducted, so that a thyristor is started, at the moment, the device works in a thyristor mode, the conductance modulation effect is enhanced, and the on-resistance of the device is effectively reduced. The cathode is made into Schottky contact, because the cathode material is aluminum, the doping concentration of the N well region is 1E20 magnitude order, the work function of the aluminum is larger than that of the N well region, electrons flow to the N well region from metal, a negative space charge region is formed on the surface of the N well region, the direction of an electric field points to the inside of the body from the surface, so that potential difference is generated between the surface and the inside of the body, the energy band on the surface of the N well region is bent downwards, the concentration of the electrons is much higher than that in the body, and a high-conductivity anti-blocking layer is formed, namely ohmic contact is formed; the doping concentration of the P well region is 1E17 magnitude, the work function of aluminum is smaller than that of a P well region semiconductor, so that the surface energy band of the P well region bends downwards to cause a hole barrier to form a P type blocking layer, namely, a Schottky diode is formed between the P well region and cathode metal, the Schottky diode has conduction voltage drop about 0.3V, and the PN junction between the P well region and the N well region can be opened only when hole current flows through the P well region to form voltage drop about 0.4V, so that the current required by the device entering a thyristor mode is greatly reduced, and the time of the device working in an IGBT mode is effectively shortened.
FIG. 5 shows a second SD-MCT, i.e. with P removed on the basis of the first SD-MCT+And a region 6, an equivalent circuit diagram is shown in fig. 6. The working principle is basically the same as that of the first SD-MCT, but the carriers are extracted slightly slowly when the device is turned off, but the pulse performance of the device is not influenced.
Taking the first SD-MCT cell structure shown in fig. 3 as an example, the manufacturing steps are as follows:
the first step is as follows: selecting a silicon wafer with proper resistivity as a substrate to form an N-type drift region 3 as shown in FIG. 7;
the second step is that: forming a gate oxide layer 7 on the upper surface of the N-type drift region 3 by thermal oxidation, as shown in fig. 8;
the third step: depositing polycrystalline silicon 8 on the upper surface of the gate oxide layer 7, and etching off redundant polycrystalline silicon and the gate oxide layer according to a polycrystalline silicon mask to form a gate electrode, as shown in FIG. 9;
the fourth step: injecting P-type impurities into the upper layer of the N-type drift region 3, and forming a P-well region 4 by utilizing a self-alignment process of a polysilicon gate, as shown in fig. 10;
the fifth step: injecting N-type impurities into the upper layer of the N-type drift region 3, and forming an N-well region 5 by utilizing a self-alignment process of a polysilicon gate and a mask of the N-well region; the N-well region 5 is located in the P-well region 4, as shown in fig. 11;
furthermore, the left N well region and the right N well region can be pulled through to form a part of N well region which is combined into a whole, and a part of N well region which is separated from the left and the right can ensure that the withstand voltage is not reduced by adjusting the proportion between the two N well regions;
and a sixth step: injecting P-type impurities into the upper layer of the N-type drift region 3, and forming P by utilizing a self-alignment process of a polysilicon gate and a mask plate of the Pdeep region+Zone 6; p+Region 6 is located in nwell region 5, as shown in fig. 12;
further, in the preparation step of the second SD-MCT, the step six is omitted;
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching a contact hole, as shown in figure 13;
eighth step: depositing metal on the upper surface of the device to respectively form a cathode 9; as shown in fig. 14;
the ninth step: depositing a passivation layer;
the tenth step: thinning and polishing the lower surface of the N-type semiconductor drift region 3, injecting P-type impurities and carrying out ion activation to form P+ An anode region 2, as shown in fig. 15;
the eleventh step: back gold at P+The bottom of the anode 2 is deposited with metal to form the anode 1, as shown in fig. 16.
Example (b):
taking the cell width of 50 μm as an example, after the second SD-MCT device of the present invention and the existing CS-MCT device are latched in FIG. 17 and FIG. 18, respectively, the current density is 600A/cm2A hole current vector distribution diagram and a hole density distribution diagram. Wherein the direction of the arrows represents the direction of movement of the hole current. By contrast, the part of the SD-MCT which is not latched is obviously smaller than that of the CS-MCT, so that the SD-MCT device has more uniform current distribution, and the area entering a thyristor mode is obviously larger than that of the CS-MCT under the same current density, and the current concentration effect is relieved.
FIG. 19 shows a second SD-MCT structure according to the present invention and a conventional CS-MCT structure at a current density of 600A/cm2And comparing the hole concentration distribution at the PN junction of the N well region and the P well region. Further proves that the SD-MCT device of the inventionThe distribution of holes is more uniform, the conduction area entering a thyristor mode is larger, the position of lateral diffusion of a P well and an N well close to a grid is the initial latching position, and the current concentration effect at the position is also relieved by the SD-MCT structure.
FIG. 20 shows the latch trigger current J of the second SD-MCT structure and the existing CS-MCT structure under different cell widthstrA simulation comparison graph of (c). It can be seen that the J of SD-MCT is different in cell widthtrAre all smaller than J of CS-MCTtrAnd is relatively less affected by the width of the cells.
The SD-MCT device of the present invention is mainly applied to the pulse domain, and fig. 21 and 22 show simulated contrast graphs of anode current and maximum lattice temperature at the time of pulse discharge at a small current for the second SD-MCT structure proposed by the present invention and the existing CS-MCT structure, respectively. Simulation shows that the peak current is improved by 6.89%, the current rise rate (di/dt) is improved by 16.97%, the time of the device in the IGBT mode is shortened by 80%, the pulse discharge response is faster, the calorific value of the device working in the IGBT mode is greatly reduced, and the lattice temperature in the discharge process is reduced by 25.64%.
It should be noted that the core invention of the present invention is to propose two kinds of MOS-gated thyristors (SD-MCT) integrating schottky diodes and to briefly explain the preparation steps thereof. The simulation results shown in the specification are only used for more clearly illustrating the advantages of the invention and do not represent that the optimal values are achieved, and the skilled person can obtain better results by optimizing the parameters of the invention. The preparation process of the invention is a process carried out after the whole structure of the device is finished, and has various changes and various forming processes. The invention cannot be used and need not be stepped, but those skilled in the art will appreciate that various layout or process changes may be made without departing from the scope of the invention.
Claims (2)
1. A MOS-gated thyristor integrated with Schottky diode has a cell structure including a bottom gateAn anode (1) and a P sequentially laminated on the anode+An anode region (2) and a drift region (3); the upper layer of the drift region (3) is provided with a P well region (4), the upper layer of the P well region (4) is provided with 2N well regions (5) which are symmetrically arranged along the vertical centerline of the device and a P well region positioned on the upper layer of the N well region (5)+Region (6), and P+The region (6) is close to the device gate; the two ends of the upper surface of the drift region (3) are respectively provided with a gate oxide layer (7), and the gate oxide layers (7) extend to cover parts of the N well region (5) and the P well region (4) along the upper surface of the P well region (4)+The upper surface of the zone (6); the gate oxide layer (7) is provided with a polysilicon gate (8), and the gate oxide layer (7) and the polysilicon gate (8) on two sides are symmetrically distributed along the vertical central line of the device; the surface of the device between the gate oxide layers (7) on the two sides is covered with cathode metal (9) in Schottky contact, namely the Schottky contact is formed between the P well region (4) and the cathode metal (9) by setting the doping concentration of the P well region (4), a Schottky diode is formed, and an isolation medium is filled between the upper surface of the polysilicon gate (8) and the cathode metal (9) for isolation.
2. A manufacturing method of an MOS grid-controlled thyristor integrated with a Schottky diode is characterized by comprising the following steps:
the first step is as follows: selecting a silicon wafer as a substrate according to the required resistivity to form an N-type drift region (3);
the second step is that: forming a gate oxide layer (7) on the upper surface of the N-type drift region (3) through thermal oxidation;
the third step: depositing polycrystalline silicon (8) on the upper surface of the gate oxide layer (7), and etching off redundant polycrystalline silicon and the gate oxide layer according to a mask of the polycrystalline silicon to form a gate electrode;
the fourth step: injecting P-type impurities into the upper layer of the N-type drift region (3), and forming a P well region (4) by utilizing a self-alignment process of a polysilicon grid;
the fifth step: injecting N-type impurities into the upper layer of the N-type drift region (3), and forming 2N well regions (5) by utilizing a self-alignment process of a polysilicon gate and a mask of the N well regions; the N well regions (5) are positioned in the P well region (4), and the N well regions (5) on two sides are symmetrically distributed along the vertical central line of the device;
and a sixth step: p-type impurities are implanted into the upper layer of the N-type drift region (3) by utilizing the majorityForming P by self-alignment process of the crystalline silicon grid and mask of the Pdeep area+A zone (6); p+The region (6) is located in the N well region (5);
the seventh step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching a contact hole;
eighth step: depositing cathode metal (9) on the upper surface of the device to form a cathode, and setting the doping concentration of the P well region (4) to enable Schottky contact to be formed between the P well region (4) and the cathode metal (9) so as to form a Schottky diode;
the ninth step: depositing a passivation layer;
the tenth step: thinning and polishing the lower surface of the N-type semiconductor drift region (3), injecting P-type impurities and carrying out ion activation to form P+An anode region (2);
the eleventh step: back gold at P+And depositing metal at the bottom of the anode (2) to form the anode (1).
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| EP1420457A1 (en) * | 2002-11-14 | 2004-05-19 | STMicroelectronics S.r.l. | Insulated gate power semiconductor device with Schottky diode and manufacturing method thereof |
| CN103022089A (en) * | 2012-06-19 | 2013-04-03 | 电子科技大学 | Reverse conducting type insulated gate bipolar transistor without snapback effect |
| CN104022149B (en) * | 2014-06-19 | 2016-07-27 | 电子科技大学 | A kind of MOS field controlled thyristor of integrated reverse PIN pipe and preparation method thereof |
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| EP1420457A1 (en) * | 2002-11-14 | 2004-05-19 | STMicroelectronics S.r.l. | Insulated gate power semiconductor device with Schottky diode and manufacturing method thereof |
| CN103022089A (en) * | 2012-06-19 | 2013-04-03 | 电子科技大学 | Reverse conducting type insulated gate bipolar transistor without snapback effect |
| CN104022149B (en) * | 2014-06-19 | 2016-07-27 | 电子科技大学 | A kind of MOS field controlled thyristor of integrated reverse PIN pipe and preparation method thereof |
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