CN110047870A - Address wire contains the longitudinal multiple programmable memory of three-dimensional of different metal material - Google Patents

Address wire contains the longitudinal multiple programmable memory of three-dimensional of different metal material Download PDF

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Publication number
CN110047870A
CN110047870A CN201810045965.0A CN201810045965A CN110047870A CN 110047870 A CN110047870 A CN 110047870A CN 201810045965 A CN201810045965 A CN 201810045965A CN 110047870 A CN110047870 A CN 110047870A
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Prior art keywords
address wire
mtp
metal material
further characterized
vertical
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CN201810045965.0A
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Chinese (zh)
Inventor
张国飙
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Chengdu Haicun IP Technology LLC
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Chengdu Haicun IP Technology LLC
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Priority to CN201810045965.0A priority Critical patent/CN110047870A/en
Publication of CN110047870A publication Critical patent/CN110047870A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor

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Abstract

The present invention proposes the longitudinal repeatedly programmable memory (3D-MTP of three-dimensional that a kind of address wire contains different metal materialV).It contains multiple horizontal address wires for being mutually perpendicular to stack, multiple storage wells for penetrating horizontally location line, the programming film of one layer of covering storage well abutment wall, a plurality of vertical address wire being formed in storage well.Horizontal address wire and vertical address wire contain different metal material.

Description

Address wire contains the longitudinal multiple programmable memory of three-dimensional of different metal material
Technical field
The present invention relates to integrated circuit memory fields, more precisely, being related to multiple programmable memory (multiple- Time programmable memory, referred to as MTP；Also referred to as overprogram memory).
Background technique
Three-dimensional repeatedly programmable memory (3D-MTP) is a kind of monomer (monolithic) semiconductor memory, it contains more The MTP of a vertical stacking stores member.The storage member of 3D-MTP is distributed in three dimensions, and the storage of traditional plane MTP Member is distributed on two-dimensional surface.Have the advantages that storage density is big, carrying cost is low etc. relative to traditional MTP, 3D-MTP.
2017/0148851 A1(applicant of U.S. Patent application US: Hsu；The applying date: on November 23rd, 2016) it proposes A kind of three-dimensional longitudinal repeatedly programmable memory (3D-MTPV).It contains the horizontal address wire of multiple vertical stackings, multiple through-falls The storage well of flat address wire, cover storage well abutment wall programming film and diode film (also referred to as selector selector, select to The titles such as device steering element, quasi- conductive membrane) and a plurality of vertical address wire being formed in storage well.It is special at this In benefit application, in order to realize the programming of storage member and avoid the interference between storage member, each storage member is containing individual Program film and individual diode film.The thickness of diode film is generally large.By taking P-N thin film diode as an example, have well just The thickness of P-N thin film diode of the counter current selection than (rectifying ratio) is in 100nm or more.So thick diode Film is such as formed in storage well, and it is very big to will lead to storage well size, and storage density reduces.
Summary of the invention
The main object of the present invention is to improve the storage density of three-dimensional repeatedly programmable memory (3D-MTP).
It is another object of the present invention to keep the fill process of storage well simpler.
It is another object of the present invention to make the smaller of storage well.
It is another object of the present invention to guarantee the normal work of 3D-MTP in the case where storing the biggish situation of first leakage current.
In order to realize that these and other purpose, the present invention propose that the three-dimensional that a kind of address wire contains different metal material is vertical To multiple programmable memory (3D-MTPV).It contains the MTP storage string of multiple side by side arrangement in substrate circuitry, and each MTP is deposited Vertically the MTP with substrate and containing multiple vertical stackings stores member to storage string.Particularly, 3D-MTPVContain a plurality of vertical stacking Horizontal address wire (wordline).After etching multiple storage wells for penetrating these horizontal address wires, covered in the abutment wall of storage well One layer of programming film of lid, and conductor material is filled to form vertical address wire (bit line).Horizontal address wire and vertical address wire contain Different metal material.MTP storage member is formed in the infall of wordline and bit line.
In order to avoid storage well is oversized, the MTP storage member in the present invention contains only individually programming film, and does not contain Individual diode film, diode are the self-assembling formations between horizontal address wire, programming film and vertical address wire.Due to It is not required to form diode film on the abutment wall of storage well, the filling of storage well becomes easy, this is by simplification of flowsheet.In addition, This design can also reduce the size of storage well, increase storage density.
Diode (i.e. self-built diode) performance of this self-assembling formation is generally bad, and leakage current is larger.In order to avoid Cause to interfere with each other between storage member since leakage current is excessive in read procedure, the present invention also proposes a kind of " full-time course " mode: one The information for all MTP storage member storage being electrically coupled with a wordline is read in a read cycle.Read cycle is in two stages: preliminary filling Electric stage and read phase.All address wires (including all wordline and all bit lines) are pre- in pre-charging stage, MTP array It is charged to a predeterminated voltage.In read phase, when the voltage in a selected word line rises to read voltage VRAfterwards, it passes through coupled thereto MTP storage member to all bit lines charge.Pass through the voltage change on measurement bit line, it may be determined that corresponding MTP storage member is stored Information.
Correspondingly, the present invention proposes the longitudinal multiple programmable memory of three-dimensional that a kind of address wire contains different metal material (3D-MTPV), it is characterised in that contain: one contains the semiconductor substrate (0) of a substrate circuitry (0K)；Multilayer is in substrate electricity On road (0K) and the horizontal address wire (8a-8h) of vertical stacking, the horizontal address wire (8a-8h) contain the first metal material；It is more A storage well (2a) for penetrating the multiple-layer horizontal address wire (8a-8h)；The volume of one layer of multiple storage well (2a) abutment wall of covering Journey film (6a), in programming, its resistance can be changed into low resistance from high-resistance state or be transformed into high resistance from low resistance；A plurality of shape At the vertical address wire (4a) in multiple storage well (2a), which contains the second metal material；It is multiple The MTP for being formed in the horizontal address wire (8a-8h) and vertical address wire (4a) infall stores first (1aa-1ha)；Described One and second metal material be different metal material.
Detailed description of the invention
Figure 1A is the 3D-MTP that the first is free of independent diode filmVZ-x sectional view；Figure 1B is that it cuts along the x-y of AA ' Face figure；Fig. 1 C is a kind of sectional view of the MTP that address wire contains different metal material storage member.
Fig. 2A-Fig. 2 C is the 3D-MTPVThe sectional view of three processing steps.
Fig. 3 A indicates the symbol and its meaning of MTP storage member；Fig. 3 B is that the first MTP array uses " full-time course mode " to read The circuit diagram of circuit out；Fig. 3 C is its timing diagram；Fig. 3 D is the I-V curve of diode.
Fig. 4 A is second of 3D-MTP for being free of independent diode filmVZ-x sectional view；Fig. 4 B is that it cuts along the x-y of CC ' Face figure；Fig. 4 C is the circuit diagram for the reading circuit that second of MTP array uses.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar Structure."/" indicates the relationship of "and" or "or"." in substrate " refers to that function element (active devices) is both formed in lining In bottom (including on substrate surface), and interconnection line be formed in above substrate, not with substrate contact." on substrate " refers to function element Be formed in above substrate, not with substrate contact.
Specific embodiment
Figure 1A is the longitudinal repeatedly programmable memory (3D-MTP of the first three-dimensional without independent diode filmV) z-x cut Face figure.It contain it is multiple be located at substrate circuitry 0K on and vertical MTP storage string (referred to as MTP storage string) 1A of side by side arrangement, 1B….Each MTP storage string 1A is vertical with substrate 0, it contains the MTP storage member 1aa-1ha of multiple vertical stackings.
Embodiment in this figure is a MTP array 10.MTP array 10 is all shared storages for having at least one address wire The set of member.It contains horizontal address wire (wordline) 8a-8h of a plurality of vertical stacking.Multiple these are penetrated horizontally etching After the storage well 2a-2d of location line 8a-8h, one layer of programming film 6a-6d is covered in the abutment wall of storage well 2a-2d, and fill conductor material Material is to form vertical address wire 4a-4d(bit line).
MTP storage member 1aa-1ha is formed in the infall of wordline 8a-8h Yu bit line 4a.In MTP storage member 1aa, programming Film 6a contains a programming material, and resistance is changed into low resistance in programming Shi Kecong high-resistance state or is transformed into height from low resistance Resistance.As an example, programming film 6a contains phase transformation (phase-change material, referred to as PCM) material or resistance Become the programming material such as (resistive RAM, referred to as RRAM) material.
Figure 1B is the 3D-MTPVAlong the x-y sectional view of AA '.Horizontal address wire 8a be a conductor plate, it can with two rows or Vertical address wires more than two rows (is herein eight vertical address wire 4a-4h) coupling, stores member 1aa- to form eight MTP 1ah.These MTP storage member (all MTP storage member being electrically coupled with a horizontal address wire 8a) 1aa-1ah constitutes a MTP and deposits Storage group 1a.Since horizontal address wire 8a is very wide, it can use low accurate lithographic technology (such as characteristic line breadth > 60 nm photoetching skill Art) it is formed.
Cause storage well size larger in order to avoid thicker due to diode film, the present invention in MTP storage member containing only There is individually programming film.As shown in Figure 1 C, MTP stores member 1aa and contains only individually programming film 6a, and does not contain individual two pole Periosteum, diode are the self-assembling formations between horizontal address wire 8a, programming film 6a and vertical address wire 4a.Due to only need to be Programming film 6a is formed on the abutment wall of storage well 2a, without forming diode film, the filling of storage well 2a is become easy, this will Simplification of flowsheet.In addition, this design can also reduce the size of storage well 2a, increase storage density.
In fig. 1 c, the diode of self-assembling formation is one self-built two between horizontal address wire 8a and vertical address wire 4a Pole pipe.In the self-built diode, horizontal address wire 8a contains the first metal material, and vertical address wire 4a contains the second metal material Material.In the first embodiment, since the work function of the first and second metal materials is different, the first metal material 8a- programming is flowed through The electric current of the second metal material of film 6a- 4a has the electrical characteristic of diode.In a second embodiment, due to the first metal material Interface (interface) between 8a and programming film 6a is different from the second metal material 4a and programs the interface between film 6a, stream The electric current for crossing the first metal material 8a- programming the second metal material of film 6a- 4a has the electrical characteristic of diode.
Fig. 2A-Fig. 2 C indicates the 3D-MTPVThree processing steps.All horizontal address layer 12a-12h are formed continuously (Fig. 2A).Particularly, after by substrate circuitry 0K planarization, first level conductor layer 12a is formed.This horizontal conductor layer 12a does not contain any figure.The first insulating layer 5a is formed on first level conductor layer 12a.Similarly, the first insulating layer 5a Any figure is not contained yet.The second horizontal conductor layer 12b is re-formed on the first insulating layer 5a.So analogize, until forming institute Some horizontal conductor layers (totally eight layers herein).In the forming process of Fig. 2A, without image conversion step (such as lithography step).By Keep good in the planarization of each horizontal conductor layer, 3D-MTPVTens of a horizontal conductor layers up to a hundred can be contained.It is foring After all horizontal conductor layer 12a-12h, all horizontal conductor layer 12a-12h are etched disposably to be formed by the first etching Horizontal address wire 8a-8h(Fig. 2 B of a plurality of vertical stacking).Later, by second etching disposably formed it is multiple penetrate it is all Storage well 2a-2d(Fig. 2 C of horizontal address wire 8a-8h).The covering programming film 6a-6d on its side wall, and conductor material is filled, To form a plurality of vertical address wire 4a-4d.
Fig. 3 A is the symbol of MTP storage member 1.MTP storage member 1 contains wordline (anode) 8 and bit line (cathode) 4, in wordline 8 Contain programming film 12 and diode 14 between bit line 4.The resistance of programming film 12 is changed into low in programming Shi Kecong high-resistance state Resistance is transformed into high resistance from low resistance；When alive numerical value is less than read voltage or direction opposite with read voltage outside, two The resistance of pole pipe 14, which is greater than, reads resistance.As previously mentioned, individually programming film is contained only in MTP storage member 1, and without containing individual Diode film.Diode 14 is the self-assembling formation between wordline (horizontal address wire) 8 and bit line (vertical address wire) 4.It is this 14 performance of diode of self-assembling formation is generally bad, and leakage current is larger.In order to avoid being led in read procedure since leakage current is excessive It causes to interfere with each other between storage member, the present invention proposes a kind of " full-time course " mode: in a read cycle, read and a wordline electricity The information of all MTP storage member storage of coupling.
Fig. 3 B indicates " full-time course mode " reading circuit that the first MTP array 10 uses.MTP array 10 contains wordline (water Flat address wire) 8a-8h, bit line (vertical address wire) 4a-4h and MTP storage member 1aa-1ad....The periphery of MTP array 10 Circuit contains a multiplexer (MUX) 40 and a sense amplifier 30.In this embodiment, MUX 40 is 4-to-1 MUX.Fig. 3 C is its timing diagram.Read cycle T contains a pre-charging stage tpreWith a read phase tR: in precharge tpreStage, MTP All address wires (8a-8h, 4a-4h) are all charged to a predeterminated voltage (such as input offset voltage of amplifying circuit 30 in array 10 Vi).In read phase tR, all bit line 4a-4h suspend, and the voltage of selected wordline 8a rises to read voltage VR, and deposited by MTP Storage member 1aa-1ah charges to all bit line 4a-4h.Voltage on every bit line is sent to sense amplifier 30 by MUX 40 respectively. If the voltage is greater than the turnover voltage V of sense amplifier 30t, then V is exportedOOverturning.At the end of read cycle T, in storage group 1a The digital information of all storage member 1aa-1ah storages is read.
Fig. 3 D is the I-V curve of diode 14.Due to the threshold voltage V of sense amplifier 30tSmaller (~ 0.1V), is reading Voltage change on stage all bit line 4a-4h is smaller, and the not selected backward voltage stored on first (such as 1ca) is about-Vt.Only Electrical (I-V) characteristic of diode 14 is wanted to meet condition I (VR)>>n*I(-Vt), 3D-MTP would not be influencedVNormal work. Here, n is the number of all MTP storage members on a bit line (such as 4a).It is noted that due to forward voltage VRValue be far longer than Backward voltage-VtValue.Even if the leakage current of diode 14 is larger, due to backward voltage-VtValue very little (~ 0.1V), above-mentioned item Part is easily met.
For convenience of address decoding, the present invention also forms multiple vertical transistors using the side wall of storage well.Fig. 4 A- Fig. 4 C table Show second of 3D-MTP for being free of independent diode filmV..It contains vertical transistor 3aa-3ad.Wherein, vertical transistor 3aa It is a transmission transistor (pass transistor), it contains grid 7a, gate medium 6a and channel 9a(Fig. 4 A).Channel 9a by It is filled in semiconductor material in storage well 2a to constitute, doping can, concentration identical as vertical address wire 4a be lower or class Type is opposite.Grid 7a surrounds storage well 2a, 2e, and controls transmission transistor 3aa, 3ae(Fig. 4 B)；Grid 7b is surrounded storage well 2b, 2f, and control transmission transistor 3ab, 3af；Grid 7c surround storage well 2c, 2g, and control transmission transistor 3ac, 3ag；Grid 7d surrounds storage well 2d, 2h, and controls transmission transistor 3ad, 3ah.Transmission transistor 3aa-3ah forms at least one Decoder stage (Fig. 4 C).In one embodiment, it when the voltage on grid 7a is height, and the voltage on grid 7b-7d is low, only passes Defeated transistor 3aa and 3ae conducting, other transmission transistors disconnect.At this moment, the MUX 40` in substrate circuitry layer is in bit line 4a With one signal of selection in 4e, send to sense amplifier 30.By forming multiple vertical transistor 3aa- in storage well 2a-2d 3ad, the present embodiment can simplify the design of decoder.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to form and details of the invention It is modified, this does not interfere them using spirit of the invention.Therefore, in addition to the spirit according to appended claims, The present invention should not be any way limited.

Claims (10)

1. a kind of three-dimensional longitudinal repeatedly programmable memory (3D-MTPV), it is further characterized in that containing:
One contains the semiconductor substrate (0) of a substrate circuitry (0K)；
Multilayer is in the substrate circuitry (0K) and the horizontal address wire (8a-8h) of vertical stacking, the horizontal address wire (8a-8h) Contain the first metal material；
Multiple storage wells (2a) for penetrating the multiple-layer horizontal address wire (8a-8h)；
The programming film (6a) of one layer of multiple storage well (2a) abutment wall of covering, in programming, its resistance can be changed into from high-resistance state Low resistance is transformed into high resistance from low resistance；
The a plurality of vertical address wire (4a) being formed in multiple storage well (2a), the vertical address wire (4a) contain the second metal Material；
Multiple MTP storage member (1aa- for being formed in the horizontal address wire (8a-8h) and vertical address wire (4a) infall 1ha)；
First and second metal material is different metal material.
2. memory according to claim 1, it is further characterized in that: the first and second metal material (8a, 4a) tool There are different work functions.
3. memory according to claim 1, it is further characterized in that: first metal material (8a) and the programming film Interface (7) between (6a) is different from interface (5) between second metal material (4a) and programming film (6a).
4. memory according to claim 1, it is further characterized in that: the programming film (6a) contains phase transformation (PCM) material.
5. memory according to claim 1, it is further characterized in that: the programming film (6a) contains resistive (RRAM) material Material.
6. memory according to claim 1, it is further characterized in that: the horizontal address wire (8a), the programming film (6a) and the vertical address wire (4a) constitute a diode (14).
7. memory according to claim 6, it is further characterized in that: it is read and selected water in a read cycle (T) All MTP that flat address wire (8a) is electrically coupled store the information of first (1aa-1ah) storage.
8. memory according to claim 7, it is further characterized in that: in the read cycle (T), it is selected horizontal address Voltage on line (8a) is read voltage (VR)；When bit-line voltage is greater than turnover voltage (Vt) when, output switching activity；The diode (14) electrical characteristic meets condition I (VR)>>n*I(-Vt), wherein n is all MTP storages on the vertical address wire (4a) The number of member.
9. memory according to claim 1, it is further characterized in that: the multiple MTP stores first (1aa-1ha) and constitutes one Vertical storage string (1A).
10. memory according to claim 9, it is further characterized in that: the vertical storage string (1A) and a longitudinal crystal Pipe (7a) is electrically coupled.
CN201810045965.0A 2018-01-17 2018-01-17 Address wire contains the longitudinal multiple programmable memory of three-dimensional of different metal material Pending CN110047870A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114913894A (en) * 2021-02-10 2022-08-16 美光科技公司 Vertical access line multiplexer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114913894A (en) * 2021-02-10 2022-08-16 美光科技公司 Vertical access line multiplexer

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