JP2011090758A - Non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a high-integrated non-volatile semiconductor memory device with low power consumption, in which a nonlinear element having sufficient current driving performance and insulation property is provided in a memory cell. <P>SOLUTION: The non-volatile semiconductor memory device has a memory cell array in which a plurality of memory cells C are arranged in matrix in row and column directions, and in each of the memory cells C, a variable resistive element R and a nonlinear element S configured with an insulating body put between a first conductor and a second conductor are connected in series, and the nonlinear element is configured to satisfy ϕ>0.5V<SB>SL</SB>/d+0.1 and ϕ<V<SB>SL</SB>/d+0.1 when an absolute value of a rewriting voltage applied to a selective memory cell is V<SB>SL</SB>[V], and a film thickness of the insulating body is d [nm] and a height of a barrier of the nonlinear element is ϕ [eV]. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention provides a memory cell that includes a first variable electrode, a second variable electrode, and a variable resistance element formed between the two electrodes, and includes a nonvolatile variable resistance element that stores information by a change in electrical resistance. The present invention relates to a semiconductor memory device having a memory cell array that is arranged in a plurality of rows and columns, and more particularly to a highly integrated and power-saving memory cell array.

  In recent years, as a next-generation non-volatile random access memory (NVRAM) capable of high-speed operation instead of flash memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), PCRAM (Phase Change RAM), RRAM (Resistance) Various device structures such as (RAM) (registered trademark) have been proposed, and intense development competition has been conducted from the viewpoint of high performance, high reliability, low cost, and process consistency. Among these non-volatile memories, RRAM can be rewritten at high speed, and since simple binary metal oxides can be used as materials, it is easy to fabricate and has high compatibility with existing CMOS processes. There are advantages.

In terms of low cost, a simple two-terminal nonvolatile memory is advantageous in that a memory cell array with a memory cell area of 4F ² can be realized. Examples of the two-terminal nonvolatile memory include RRAM, PCRAM, and spin injection MRAM.

The simplest configuration of a memory cell array having a cross-point structure is a 1R type memory cell having no selection element in the memory cell. 14 and 15 show an example (circuit configuration diagram) of a 1R type memory cell array including 1R type memory cells, together with applied voltages at the time of rewriting and reading. A bit array (B1 to B3), word lines (W1 to W3), and variable resistance elements R (R _{11 to} R ₃₃ ) are arranged in a matrix on the intersections thereof, thereby forming a memory cell array. Yes. As shown in FIG. 14, the simplest method for rewriting and reading the variable resistance element of the selected memory cell is to apply the voltage V only between the bit line and the word line connected to the selected memory cell (for example, R ₂₂ ). _{Although SL} is applied, current (leakage current) also flows through unselected memory cells, which causes a problem that current consumption increases and reading becomes difficult. As a driving method for reducing this problem, there is a method of applying a voltage to unselected bit lines and unselected word lines, for example, a 1/2 bias method.

In the 1/2 bias method, as shown in FIG. 15, rewriting in which only one of the rows or columns of the selected memory cell (for example, R ₂₂ ) is applied to the same half-selected memory cell is applied to the selected memory cell. A voltage or half of the read voltage is applied. However, even with this method, when the array size is increased, problems such as disturbance due to the half-selected voltage and increase in current consumption due to current (leakage current) flowing through the half-selected memory cell may occur. The total current flowing through the half-selected memory cells increases in proportion to the array size, and accordingly, it is necessary to increase the current driving capability of the driving circuit, and as a result, the driving circuit needs to be enlarged. Further, when the total current flowing through the half-selected memory cells increases, the voltage drop at the bit line and word line increases to a level that cannot be ignored. In the ½ bias method, ideally, current flows only in the selected memory cell and the half-selected memory cell. However, when the voltage drop occurs, the ideal potential distribution is disrupted, and current flows in the unselected memory cell. Will begin to flow. Even a small amount of current flowing through each unselected memory cell cannot be ignored in the entire array, resulting in an increase in current consumption. In order to suppress this, it is necessary to limit the size of the array block to a small size. However, the area utilization efficiency is deteriorated, resulting in high cost.

  As a configuration for avoiding the above problem, a 1D1R type memory cell array has been proposed. This is a memory cell in which a non-linear element and a variable resistance element are connected in series. As the nonlinear element, for example, a pn diode of Patent Documents 1 and 2, a varistor of Patent Document 3, an MIM (Metal-Insulator-Metal) element of Patent Document 4, a silicon nitride film of Patent Document 5, and the like are used. it can.

JP 2006-140489 A JP 2007-165873 A JP 2006-203098 A US Pat. No. 6,753,561 JP 2008-235637 A

  In order to realize a low bit cost nonvolatile memory, the size of the memory cell must be reduced and the array scale must be increased. In order to reduce the memory cell, it is necessary to reduce both the variable resistance element and the non-linear element, and a non-linear element capable of flowing a current at a high current density is required.

  On the other hand, when the array scale increases, the total current flowing through the half-selected memory cells increases in proportion to the array scale, and thus power consumption increases. In order to realize a low power consumption nonvolatile memory, the non-linear element has a current-voltage characteristic in which the current is sharply cut off when the applied voltage is lowered so that the leakage current flowing through the half-selected memory cell can be efficiently suppressed. It is necessary to have.

  In each of the above-mentioned Patent Documents 1 to 5, the current drive capability of the nonlinear element is insufficient, or the device structure for realizing the realistic current drive capability is not clear, and the memory cell array having a cross-point structure It is not clarified about the necessary shut-off characteristics when using it.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a low power consumption and highly integrated nonvolatile semiconductor memory device including a memory cell having a nonlinear element having sufficient current drive capability and cutoff characteristics. Is to provide.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a first electrode, a second electrode, and a variable resistor that is directly connected to the first electrode and the second electrode. A variable resistance element in which a resistance state transitions between two or more different states by applying a voltage between an electrode and the second electrode, and the first resistance state after the transition is held in a nonvolatile manner; A non-linear element having an insulator sandwiched between a conductor and a second conductor, and the variable resistance element and the non-linear element are connected in series by connecting the second electrode and the first conductor. A non-volatile semiconductor memory device having a memory cell array in which a plurality of connected memory cells are arranged in a matrix in the row and column directions, respectively, and a selected memory to be rewritten from among the memory cells in the memory cell array Cell When rewriting information stored in the selected memory cell, a predetermined reference potential is applied to either the first electrode or the second conductor of the memory cell selected in the row direction. V _SL / 2 [V] on the basis of the reference potential is applied to either the first electrode or the second conductor of the memory cell that is not selected in the row direction.
V _SL [V] is applied to either the first electrode or the second conductor of the memory cell selected in the column direction with reference to the reference potential, and the memory cell that is not selected in the column direction. V _SL / 2 [V] is applied to either the first electrode or the second conductor with the reference potential as a reference, and between the first electrode and the second conductor of the selected memory cell. Of the absolute value V _SL of the rewrite voltage applied to, the ratio of the voltage applied to the variable resistance element is x, the film thickness of the insulator is d [nm], and y = 10 × V _SL / d Then, the energy difference [eV] between the energy at the bottom of the conduction band of the insulator and the Fermi level of at least one of the first conductor and the second conductor is a ₁ y ² + b ₁ y + c ₁ or less and a ₂ y ² + b ₂ y + c ₂ or more, where a ₁ = −3.09 × 10 ⁻³ (1-x) ² , b ₁ = 1.32 × 10 ⁻¹ (1-x), c ₁ = 4.10 × 10 ⁻² , a ₂ = −8.83 × 10 ⁻³ x ³ + 1.70 × 10 ⁻⁵ x ² + 5.94 × 10 ⁻⁴ x−2.31 × 10 ⁻³ , b ₂ = 4.94 × 10 ⁻¹ x ³ + 3.53 × 10 ⁻² x ² + 5.87 × 10 ⁻² x + 7.54 × 10 ⁻² , c ₂ = 7.62 × 10 ⁻¹ x ³ + 5.03 × 10 ⁻² x ² +9 The first characteristic is .24 × 10 ⁻² x + 4.97 × 10 ⁻² .

According to the nonvolatile semiconductor memory device of the first feature, the rewrite voltage V _SL , the insulator film thickness d, the ratio x of the rewrite voltage V _SL divided by the variable resistance element, and the energy by the difference satisfies the relational expression described above, 30 nm × 30 nm to 100 nm × the size of the fine variable resistive element ^{100nm, 0.1MA / cm 2 ~10MA /} cm 2 through a comparable size of the non-linear element In the rewriting of the memory cell array of 1 Kbit or more of about 32 × 32 or more by the 1/2 bias method, the sum of the currents flowing in the half-selected memory cells flows in the selected memory cells. It can be less than or equal to the current. As a result, a leak current flowing through the half-selected memory cells is suppressed, and a highly integrated nonvolatile memory with low power consumption can be realized. Further, since the nonlinear element can have the same nonlinear characteristic regardless of the direction of current, it can be used for MRAM, RRAM, etc. that use currents in opposite directions for writing and erasing.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a first electrode, a second electrode, a variable that is directly connected to the first electrode and indirectly connected to the second electrode via an insulator. A resistor is provided, and by applying a voltage between the first electrode and the second electrode, the resistance state transitions between two or more different states, and one resistance state after the transition is held in a nonvolatile manner A non-volatile semiconductor memory device having a memory cell array in which a plurality of memory cells each having a variable resistance element are arranged in a matrix in the row and column directions, and is a target of rewriting from among the memory cells in the memory cell array. When selecting the selected memory cell and rewriting the information stored in the selected memory cell, either the first electrode or the second electrode of the memory cell selected in the row direction , A predetermined reference potential, either one of the first electrode or the second electrode of said memory cells in unselected in the row direction, the V _{SL / 2} [V] as the basis of the reference potential, in the column direction V _SL [V] is applied to either the first electrode or the second electrode of the selected memory cell with reference to the reference potential, and the first electrode of the memory cell that is not selected in the column direction or Rewriting is performed between the first electrode of the selected memory cell and the second conductor by applying V _SL / 2 [V] to the other of the second electrodes with reference to the reference potential. The ratio of the voltage applied to the variable resistance element in the absolute value V _SL of the voltage is x, the film thickness of the insulator is d [nm], and y = 10 × V _SL / d. The energy of the bottom of the conduction band of the body and the ferrule of the second electrode At least one of the energy difference [eV] from the mi level or the energy difference [eV] between the bottom of the conduction band of the insulator and the bottom of the conduction band of the variable resistor is a ₁ y ² + b ₁ y + c ₁ or less and a ₂ y ² + b ₂ y + c ₂ or more, where a ₁ = −3.09 × 10 ⁻³ (1-x) ² , b ₁ = 1.32 × 10 ^{− 1} (1-x), c ₁ = 4.10 × 10 ⁻² , a ₂ = −8.83 × 10 ⁻³ x ³ + 1.70 × 10 ⁻⁵ x ² + 5.94 × 10 ⁻⁴ x-2 .31 × 10 ⁻³ , b ₂ = 4.94 × 10 ⁻¹ x ³ + 3.53 × 10 ⁻² x ² + 5.87 × 10 ⁻² x + 7.54 × 10 ⁻² , c ₂ = 7.62 × 10 ^-1 x ³ + 5.03 second being a ^{× 10 -2 x 2 + 9.24 ×} 10 -2 x + 4.97 × 10 -2 To.

The nonvolatile semiconductor memory device according to the second feature uses an element in which an insulator is inserted between a variable resistor and a second electrode as a memory cell, and the element has a resistance state when a rewrite voltage is applied. It is configured to change in a nonvolatile manner so that a memory operation as a variable resistance element can be performed, and at the same time, a function as a non-linear element is exhibited. That is, the variable resistor and the second electrode each serve as a conductor that sandwiches the insulator. Similar to the nonvolatile semiconductor memory device of the first feature, the rewrite voltage V _SL , the thickness d of the insulator, the ratio x of the rewrite voltage V _SL divided by the variable resistance element, and the energy difference However, if the above relational expression is satisfied, the leakage current flowing through the half-selected memory cells can be suppressed, and a low power consumption and highly integrated nonvolatile memory can be realized.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a first electrode, a second electrode, and a variable resistor that is directly connected to the first electrode and the second electrode. A variable resistance element in which a resistance state transitions between two or more different states by applying a voltage between an electrode and the second electrode, and the first resistance state after the transition is held in a nonvolatile manner; A non-linear element having an insulator sandwiched between a conductor and a second conductor, and the variable resistance element and the non-linear element are connected in series by connecting the second electrode and the first conductor. A non-volatile semiconductor memory device having a memory cell array in which a plurality of connected memory cells are arranged in a matrix in the row and column directions, respectively, and a selected memory to be rewritten from among the memory cells in the memory cell array Cell When rewriting information stored in the selected memory cell, a predetermined reference potential is applied to either the first electrode or the second conductor of the memory cell selected in the row direction. V _SL × 2/3 [V] is selected in the column direction on the basis of the reference potential for either the first electrode or the second conductor of the memory cell that is not selected in the row direction. V _SL [V] is applied to either the first electrode or the second conductor of the memory cell with reference to the reference potential, and the first electrode of the memory cell that is not selected in the column direction or the second conductor. Rewriting applied between the first electrode and the second conductor of the selected memory cell by applying V _SL / 3 [V] to the other of the second conductors with the reference potential as a reference. among the absolute value V _SL of the voltage, the variable resistor The ratio of the voltage applied to the child as x, and the thickness of the insulator and d [nm], and _{y = 10 × V SL / d} , and the bottom energy of the conduction band of the insulator, the first The energy difference [eV] between one conductor and at least one of the second conductors is not more than a ₁ y ² + b ₁ y + c _{1 and not} less than a ₃ y ² + b ₃ y + c ₃ Yes, where a ₁ = −3.09 × 10 ⁻³ (1-x) ² , b ₁ = 1.32 × 10 ⁻¹ (1-x), c ₁ = 4.10 × 10 ⁻² , a ₃ = −1.84 × 10 ⁻³ x ³ + 6.81 × 10 ⁻⁴ x ² + 4.99 × 10 ⁻⁴ x−1.20 × 10 ⁻³ , b ₃ = 2.26 × 10 ⁻¹ x ^{3 -7.02 × 10 -2 x 2 +} 3.20 × 10 -2 x + 3.89 × 10 -2, c 3 = 5.23 × 10 -1 x 3 A third feature is that −1.48 × 10 ⁻¹ x ² + 6.40 × 10 ⁻² x + 2.54 × 10 ⁻² .

According to the nonvolatile semiconductor memory device of the third feature, the rewrite voltage V _SL , the insulator film thickness d, the ratio x of the rewrite voltage V _SL divided by the variable resistance element, and the energy by the difference satisfies the relational expression described above, 30 nm × 30 nm to 100 nm × the size of the fine variable resistive element ^{100nm, 0.1MA / cm 2 ~10MA /} cm 2 through a comparable size of the non-linear element In the rewrite of the memory cell array of 1 Kbit or more of about 32 × 32 or more by the 1/3 bias method, the total current flowing in the half-selected memory cell flows to the selected memory cell. It can be less than or equal to the current. As a result, a leak current flowing through the half-selected memory cells is suppressed, and a highly integrated nonvolatile memory with low power consumption can be realized. Further, since the nonlinear element can have the same nonlinear characteristic regardless of the direction of current, it can be used for MRAM, RRAM, etc. that use currents in opposite directions for writing and erasing.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a first electrode, a second electrode, a variable that is directly connected to the first electrode and indirectly connected to the second electrode via an insulator. A resistor is provided, and by applying a voltage between the first electrode and the second electrode, the resistance state transitions between two or more different states, and one resistance state after the transition is held in a nonvolatile manner A non-volatile semiconductor memory device having a memory cell array in which a plurality of memory cells each having a variable resistance element are arranged in a matrix in the row and column directions, and is a target of rewriting from among the memory cells in the memory cell array. When selecting the selected memory cell and rewriting the information stored in the selected memory cell, either the first electrode or the second electrode of the memory cell selected in the row direction , A predetermined reference potential, either one of the first electrode or the second electrode of said memory cells in unselected in the row direction, the _{V SL × 2/3 [V} ] as the basis of the reference potential, the column V _SL [V] is applied to either the first electrode or the second electrode of the memory cell selected in the direction with reference to the reference potential, and the first of the memory cells not selected in the column direction. V _SL / 3 [V] is applied to either the electrode or the second electrode with reference to the reference potential, and is applied between the first electrode and the second conductor of the selected memory cell. In the absolute value V _SL of the rewrite voltage, x is the ratio of the voltage applied to the variable resistance element, the film thickness of the insulator is d [nm], and y = 10 × V _SL / d. The energy at the bottom of the conduction band of the insulator and the flow of the second electrode. The energy difference between the Rumi level [eV], or at least one of the energy difference [eV] between the bottom of the bottom and the conduction band of the variable resistor of the conduction band of the insulator, a 1 _y 2 ⁺ b ₁ y + c ₁ or less and a ₃ y ² + b ₃ y + c ₃ or more, where a ₁ = −3.09 × 10 ⁻³ (1-x) ² , b ₁ = 1.32 × 10 ^{− 1} (1-x), c ₁ = 4.10 × 10 ⁻² , a ₃ = −1.84 × 10 ⁻³ x ³ + 6.81 × 10 ⁻⁴ x ² + 4.99 × 10 ⁻⁴ x−1 20 × 10 ⁻³ , b ₃ = 2.26 × 10 ⁻¹ x ³ −7.02 × 10 ⁻² x ² + 3.20 × 10 ⁻² x + 3.89 × 10 ⁻² , c ₃ = 5.23 ^{× 10 -1 x 3 -1.48 × 10} -1 x 2 + 6.40 × 10 -2 x + 2.54 × 10 that is ^-2 fourth And butterflies.

The nonvolatile semiconductor memory device according to the fourth feature uses an element in which an insulator is inserted between a variable resistor and a second electrode as a memory cell, and the element has a resistance state when a rewrite voltage is applied. It is configured to change in a nonvolatile manner so that a memory operation as a variable resistance element can be performed, and at the same time, a function as a non-linear element is exhibited. That is, the variable resistor and the second electrode each serve as a conductor that sandwiches the insulator. Similar to the nonvolatile semiconductor memory device of the third feature, the rewrite voltage V _SL , the insulator film thickness d, the ratio x of the rewrite voltage V _SL divided by the variable resistance element, and the energy difference However, if the above relational expression is satisfied, the leakage current flowing through the half-selected memory cells can be suppressed, and a low power consumption and highly integrated nonvolatile memory can be realized.

The nonvolatile semiconductor memory device according to the present invention is further characterized in that (1-x) V _SL / d is 1 or less in addition to any of the first to fourth characteristics. .

  According to the nonvolatile semiconductor memory device having the fifth feature, the electric field applied to the nonlinear element can be suppressed to about 10 MV / cm or less, so that highly reliable operation is possible.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a first electrode, a second electrode, and a variable resistor that is directly connected to the first electrode and the second electrode. A variable resistance element in which a resistance state transitions between two or more different states by applying a voltage between an electrode and the second electrode, and the first resistance state after the transition is held in a nonvolatile manner; A non-linear element having an insulator sandwiched between a conductor and a second conductor, and a plurality of memory cells connected in series by connecting the second electrode and the first conductor, respectively, A nonvolatile semiconductor memory device having a memory cell array arranged in a matrix in a column direction, wherein a selected memory cell to be rewritten is selected from the memory cells in the memory cell array and stored in the selected memory cell Has been When rewriting of information, V _{SL [V]} the absolute value of the writing voltage applied between said first electrode and the second conductor of the selected memory cell, the thickness of the insulator d [nm ], The energy difference [eV] between the bottom energy of the conduction band of the insulator and the Fermi level of at least one of the first conductor and the second conductor is (0.5 V _SL /D+0.1) and (V _SL /d+0.1) or less is a sixth feature.

According to the nonvolatile semiconductor memory device of the sixth feature, the rewrite voltage V _SL , the film thickness d of the insulator, and the energy difference satisfy the above relational expression, so that 30 nm × 30 nm to 100 nm A rewrite current of 0.1 MA / cm ^{2 to} 10 MA / cm ² can be passed through a fine variable resistance element having a size of 100 nm through a non-linear element of the same size, and about 32 × 32 or more In the memory cell array of 1 Kbit or more, the sum of the currents flowing through the half-selected memory cells can be made equal to or less than the current flowing through the selected memory cells. As a result, a leak current flowing through the half-selected memory cells is suppressed, and a highly integrated nonvolatile memory with low power consumption can be realized. Further, since the nonlinear element can have the same nonlinear characteristic regardless of the direction of current, it can be used for MRAM, RRAM, etc. that use currents in opposite directions for writing and erasing.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a first electrode, a second electrode, a variable that is directly connected to the first electrode and indirectly connected to the second electrode via an insulator. A resistor is provided, and by applying a voltage between the first electrode and the second electrode, the resistance state transitions between two or more different states, and one resistance state after the transition is held in a nonvolatile manner A non-volatile semiconductor memory device having a memory cell array in which a plurality of memory cells each having a variable resistance element are arranged in a matrix in the row and column directions, and is a target of rewriting from among the memory cells in the memory cell array. When a selected memory cell is selected and information stored in the selected memory cell is rewritten, the rewrite voltage applied between the first electrode and the second electrode of the selected memory cell is completely interrupted. The value _{V SL [V],} wherein the thickness of the insulator and d [nm], the energy difference between the Fermi level of energy and the second electrode at the bottom of the conduction band of the insulator [eV], or , At least one of the energy difference [eV] between the bottom of the conduction band of the insulator and the bottom of the conductor of the variable resistor is (0.5 V _SL /d+0.1) or more and (V _{SL /} d + 0.1) or less is a seventh feature.

The nonvolatile semiconductor memory device according to the seventh feature uses an element in which an insulator is inserted between a variable resistor and a second electrode as a memory cell, and the element has a resistance state when a rewrite voltage is applied. It is configured to change in a nonvolatile manner so that a memory operation as a variable resistance element can be performed, and at the same time, a function as a non-linear element is exhibited. That is, the variable resistor and the second electrode each serve as a conductor that sandwiches the insulator. Similar to the nonvolatile semiconductor memory device having the first feature, the rewrite voltage V _SL , the film thickness d of the insulator, and the leakage of the current flowing in the half-selected memory cell when the energy difference satisfies the above relational expression. A highly integrated nonvolatile memory with low current consumption and low power consumption can be realized.

Furthermore, the nonvolatile semiconductor memory device according to the present invention has an eighth characteristic that V _SL / d is 1 or less in addition to any of the sixth or seventh characteristics.

  According to the nonvolatile semiconductor memory device having the eighth feature, the electric field applied to the nonlinear element is suppressed to about 10 MV / cm or less, and a highly reliable operation is possible.

  Furthermore, the nonvolatile semiconductor memory device according to the present invention has, in addition to any of the first to eighth features, a ninth feature that the film thickness d of the insulator is 5 nm or less.

  According to the nonvolatile semiconductor memory device of the ninth feature, the on-voltage of the nonlinear element becomes a low voltage of about 5 V or less, so that the memory cell array can be driven at a low voltage and the power consumption can be further reduced.

  Furthermore, in addition to any of the first to ninth features, the nonvolatile semiconductor memory device according to the present invention is characterized in that the first conductor and the second conductor are made of the same material. Ten features.

  According to the nonvolatile semiconductor memory device of the tenth feature, even when currents flowing in opposite directions are passed through the variable resistance element, the on-voltage of the nonlinear element can be made the same for each current direction, Driving can be facilitated.

  Furthermore, in addition to any one of the first to tenth features, the nonvolatile semiconductor memory device according to the present invention has an eleventh feature that the band gap of the insulator is 5 eV or more.

  According to the nonvolatile semiconductor memory device having the eleventh feature, the breakdown voltage of the nonlinear element can be increased, and a highly reliable operation is possible.

  Therefore, according to the present invention, it is possible to realize a low power consumption and highly integrated nonvolatile semiconductor memory device including a memory cell having a non-linear element having sufficient current driving capability and cutoff characteristics.

1 is a schematic configuration block diagram of a nonvolatile semiconductor device (device of the present invention) according to the present invention. The figure which shows the circuit structure of the memory cell array of this invention apparatus, and the applied voltage at the time of memory operation | movement in a 1/2 bias method. The figure which shows typically the electronic state at the time of the voltage application of a MIM element. 4 shows a configuration example of a memory cell array of the device of the present invention. 6 shows another configuration example of the memory cell array of the device of the present invention. 6 shows another configuration example of the memory cell array of the device of the present invention. 6 shows another configuration example of the memory cell array of the device of the present invention. 6 shows another configuration example of the memory cell array of the device of the present invention. 6 shows another configuration example of the memory cell array of the device of the present invention. The figure which shows the calculation result of the current density of a nonlinear element. The figure which shows the relationship between the electric field E applied to the nonlinear element for obtaining a required current density, and barrier height (phi). The figure which shows the relationship between the electric field E applied to the nonlinear element for obtaining a required cut-off ratio, and barrier height (phi). The figure which shows the relationship between the electric field E applied to the nonlinear element which should satisfy the nonlinear element used by this invention apparatus, and barrier height (phi). The figure which shows the circuit structure of the conventional 1R type memory cell array, and the applied voltage at the time of memory operation. The figure which shows the circuit structure of the conventional 1R type memory cell array, and the applied voltage at the time of memory operation. The figure which shows x dependence of the coefficient at the time of fitting the relational expression of _VSL / d and barrier height (phi) which should be satisfied with the nonlinear element used by the apparatus of this invention with a quadratic curve in 2nd Embodiment. The figure which illustrates the relational expression of _VSL / d which should be satisfied with the nonlinear element used with the apparatus of the present invention and the barrier height φ in the second embodiment when x = 0.1. The figure which shows the circuit structure of the memory cell array of this invention apparatus, and the applied voltage at the time of memory operation | movement in the 1/3 bias method. The figure which shows x dependence of the coefficient at the time of fitting the relational expression of _VSL / d and barrier height (phi) which should be satisfied with the nonlinear element used by the apparatus of this invention with a quadratic curve in 3rd Embodiment. In 3rd Embodiment, the figure which illustrates the relationship between _VSL / d which should be satisfied with the nonlinear element used by this invention apparatus, and barrier height (phi) in the case of x = 0.1.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention (hereinafter, appropriately referred to as “present invention device 100”) will be described with reference to the drawings. Note that, in the drawings shown below, the main parts are appropriately emphasized, and the dimensional ratio on the drawings does not necessarily match the actual dimensional ratio.

  A schematic configuration block diagram of the device 100 of the present invention is shown in FIG. As shown in FIG. 1, a device 100 according to the present invention includes a bit line decoder around a memory cell array 101 in which a plurality of memory cells each having a variable resistance element and a nonlinear element are arranged in a matrix in the row direction and the column direction. 102, a word line decoder 103, a read circuit 104, a voltage switch circuit 105, a voltage generation circuit 106, and a control circuit 107.

As shown in the circuit diagram of FIG. 2, the memory cell array 101 extends in the column direction and m bit lines (column selection lines) B1 to Bm for selecting memory cells in the row direction, and extends in the row direction. This is a memory cell array having a cross-point structure composed of m × n memory cells arranged at intersections of n word lines (row selection lines) W1 to Wn for selecting memory cells in the column direction. More specifically, in the memory cell array 101, for example, the first electrodes of the variable resistance elements of the memory cells in the same column are connected and extended in the column direction to form the bit lines B1 to Bm. The second conductors of the non-linear elements are connected to each other and extended in the row direction to form word lines W1 to Wn. The memory cell array 101 may be configured by a set of a plurality of subarrays, and a part of the address may be used for selecting the subarray. On the intersection of the m bit lines and the n word lines, a memory cell C (a variable resistance element R (R _{11 to} R _mn ) and a non-linear element S (S _{11 to} S _mn ) are connected in series. C _{11 to} C _mn ) are arranged in an m × n matrix, so that the memory cell array 101 is configured.

The variable resistance element R (R _{11 to} R _mn ) is a two-terminal element in which a variable resistor is sandwiched between a first electrode and a second electrode, and the first electrode and the second electrode are connected to both terminals. By applying a voltage between the two terminals, the resistance state transitions between two or more different states, and the resistance state after the transition is held in a nonvolatile manner, so that the two or more resistance states are stored as information. Can be used.

The nonlinear element S (S _{11 to} S _mn ) is a two-terminal MIM element in which an insulator is sandwiched between a first conductor and a second conductor, and the second electrode of the variable resistance element R. By connecting the first conductor of the non-linear element S to the variable resistance element R and the non-linear element S in series, a memory cell is configured.

FIG. 3 schematically shows the electronic state of the nonlinear element when the voltage V _SL is applied to the nonlinear element. By applying the voltage _VSL , electrons tunnel from the first conductor to the second conductor over the triangular potential type tunnel barrier in the insulator, and current flows. Here, the non-linear element, (energy difference between the bottom of the conduction band of the conductor Fermi level E _F and the insulator) barrier height phi, the applied voltage V _SL, the relationship between the thickness d of the insulator, It is comprised so that the following number 1 and number 2 may be satisfied.

[Equation 1]
φ ≧ 0.5V _SL /d+0.1
[Equation 2]
φ ≦ V _SL /d+0.1

As a result, although the reason will be described later, a rewrite current of 0.1 MA / cm ^{2 to} 10 MA / cm ² can be passed, and the array size is about 32 × 32 or more, that is, the memory capacity is small. In a memory cell array of 1 Kbit or more, the leakage current flowing through the half-selected memory cell is suppressed to the same level or less as the current flowing through the selected memory cell, and the inventive device 100 with low power consumption and high integration is realized.

  The bit line decoder 102 and the word line decoder 103 function as a memory cell selection circuit that selects memory cells in the memory cell array 101 in units of rows, columns, or memory cells, and are input from the address lines 109 to the control circuit 107. The memory cell corresponding to the address signal thus selected is selected as a memory cell to be read or rewritten. That is, the word line decoder 103 selects the word line of the memory cell array 101 corresponding to the address signal input to the address line 109, and the bit line decoder 102 selects the memory cell array corresponding to the address signal input to the address line 109. 101 bit lines are selected.

  The read circuit 104 converts the read current flowing through the selected bit line selected by the bit line decoder 102 out of the read current flowing between the word line connected to the selected memory cell and each bit line, and reads the memory to be read. The state of data stored in the cell is determined, and the result is transferred to the control circuit 107 and output to the data line 110.

  The voltage switch circuit 105 generates a voltage generated by the voltage generation circuit 106 to be applied to the word line and the bit line during each memory operation of reading, writing, and erasing of the memory cell array 101 according to each memory operation. It functions as a voltage supply circuit for switching and supplying to the memory cell array 101.

  The control circuit 107 performs each control in the rewrite operation (write operation and erase operation) and read operation of the memory cell array 101. In addition, the control circuit 107 is based on the address signal input from the address line 109, the data input input from the data line 110 (during writing), and the control input signal input from the control signal line 108. The read, write, and erase operations of the bit line decoder 102, voltage switch circuit 105, and memory cell array 101 are controlled. In the example shown in FIG. 1, the control circuit 107 has functions as a general address buffer circuit, data input / output buffer circuit, and control input buffer circuit (not shown).

  Various known configurations can be used as specific configurations of the bit line decoder 102, the word line decoder 103, the read circuit 104, the voltage switch circuit 105, the voltage generation circuit 106, and the control circuit 107. Since it is not the gist of the present invention, the description is omitted.

  A configuration example of the memory cell array of the device of the present invention is shown in FIG. The memory cell array 101a shown in FIG. 4 includes a variable resistance element including a first electrode 10, a variable resistor 11, a second electrode 12, and a first conductor 13, on each intersection of the word line 20 and the bit line 21. The nonlinear element which consists of the insulator 14 and the 2nd conductor 15 becomes a structure laminated | stacked in order. As the variable resistance element, in addition to a resistance change memory (RRAM), a two-terminal nonvolatile memory such as a spin injection MRAM, a phase change memory (PCRAM), a solid electrolyte memory, or the like can be used.

  Another configuration example of the memory cell array of the device of the present invention is shown in FIG. The memory cell array 101b shown in FIG. 5 has a configuration in which the first conductor 13 as a nonlinear element and the second electrode 12 as a variable resistance element are shared in the configuration of FIG.

  Another configuration example of the memory cell array of the device of the present invention is shown in FIG. A memory cell array 101c shown in FIG. 6 is obtained by further simplifying the configuration of FIG. 5 and has a configuration in which the second conductor 15 of the nonlinear element and the word line 20 are shared.

  FIG. 7 shows another configuration example of the memory cell array of the device of the present invention. A memory cell array 101d shown in FIG. 7 is obtained by further simplifying the configuration of FIG. 6, and has a configuration in which the first electrode 10 of the variable resistance element and the bit line 21 are shared.

  In the memory cell array shown in FIGS. 4 to 7, the barrier height calculated from the energy difference between the bottom energy of the conductor of the insulator 14 and the Fermi level of the second conductor 15 (word line 20). φ or at least one of the barrier height φ calculated from the energy difference between the energy of the bottom of the conduction band of the insulator 14 and the Fermi level of the first conductor 13 (second electrode 12 of the variable resistor) One of the insulator material, the variable resistor material, the first conductor material (second electrode material), and the second conductor material (word line material) so that one of the above-described equations 1 and 2 is satisfied. Is selected, a memory cell array with low power consumption and high integration, which is composed of memory cells having nonlinear elements having sufficient current drive capability and cutoff characteristics, is configured.

  FIG. 8 shows another configuration example of the memory cell array of the device of the present invention. A memory cell array 101e shown in FIG. 8 is obtained by further simplifying the configuration of FIG. 7, omitting the second electrode 12 of the variable resistance element, and the variable resistance body 11 of the variable resistance element and the first conductivity of the nonlinear element. It is the structure which made the body 13 common. From another point of view, in this configuration example, an element in which the insulator 14 is inserted between the variable resistor and the second electrode (word line 20) is arranged on the intersection of the word line 20 and the bit line 21, respectively. The device has a configuration in which the resistance state is changed in a non-volatile manner by applying a rewrite voltage so that a memory operation as a variable resistance element can be performed, and at the same time, a function as a non-linear element is exhibited. . The barrier height φ calculated from the energy difference between the energy of the bottom of the conduction band of the insulator 14 and the Fermi level of the word line 20, or the bottom of the conduction band of the insulator 14 and the conduction band of the variable resistor 11. An insulator material, a variable resistor material, and a word line material are selected so that at least one of the barrier heights φ calculated from the energy difference from the bottom satisfies the above-described Equations 1 and 2. Thus, the element has a sufficient current driving capability and a cutoff characteristic, and a highly integrated memory cell array with low power consumption is configured.

  Furthermore, another configuration example of the memory cell array of the device of the present invention is shown in FIG. In the memory cell array 101f shown in FIG. 9, a cylindrical insulator 31 is stacked so as to be orthogonal to the planar word line 30 that also serves as the second conductor of the nonlinear element, and further, the first layer of the nonlinear element is disposed inside thereof. The variable resistor 32 that also serves as one conductor has a structure in which the bit line 33 that also serves as the first electrode of the variable resistance element is disposed inside the variable resistor 32 and can be highly integrated three-dimensionally. In the memory cell array 101f, insulating films and word lines 30 on the surface are alternately stacked in the vertical direction, holes are formed perpendicular to the word lines on the surface by photolithography and etching, and CVD is performed on the inner walls of the holes. The insulator 31, the variable resistor 32, and the bit line 33 can be formed in this order by a method or the like.

  Similarly to the memory cell array shown in FIG. 8, the memory cell shown in FIG. 9 changes its resistance state in a non-volatile manner by applying a rewrite voltage and can perform a memory operation as a variable resistance element. At the same time, it is configured to exhibit a function as a nonlinear element. The barrier height φ calculated from the energy difference between the bottom energy of the insulator conduction band and the Fermi level of the word line on the surface, or the bottom of the conduction band of the insulator and the bottom of the variable resistor conduction band By selecting an insulator material, a variable resistor material, and a word line material so that at least one of the barrier heights φ calculated from the energy difference with the above satisfies the above formulas 1 and 2. A memory cell having sufficient current driving capability and cutoff characteristics is configured, and a highly integrated memory cell array with low power consumption is configured.

  Next, the current drive capability required for the nonlinear element in the memory cell array of the device 100 of the present invention will be described.

In the MIM element, the voltage V _SL is applied between the conductors, the thickness of the insulator sandwiched between the conductors is d, and the tunnel barrier by the insulator is a triangular potential (see the electronic state diagram in FIG. 3). FIG. 10 shows an example in which the current density is calculated. A large current density can be obtained by reducing the thickness d of the insulator or reducing the barrier height φ.

  FIG. 11 shows the calculated relationship between the applied electric field E and the barrier height φ to obtain the required current density J. It can be seen that higher current density can be achieved with higher applied electric field and lower barrier height.

  Next, conditions for driving the memory cell array in a current saving manner will be described.

At the time of rewriting, when the memory cell array is driven by the ½ bias method, a voltage that is approximately half the voltage applied to the nonlinear element of the selected memory cell is applied to the nonlinear element of the half-selected memory cell. That is, when the voltage V _SL is applied to the selected memory cell, 1/2 V _SL is applied to the (m + n−2) half-selected memory cells, and a leak current is generated. Here, it is assumed that the current flowing through the nonlinear element of the selected memory cell during writing is I _SL , and the current flowing through the nonlinear element of each half-selected memory cell is I _HS . The amount of leakage current flowing through each half-selected memory cell depends on the resistance state of the variable resistance element of the memory cell, but the current flowing through the half-selected memory cell whose resistance state is the low resistance state is I _HS ^(L) Then, the total leakage current is (m + n−2) I _HS ^{(L) in} the worst case.

The total leakage current is desirably as small as possible, and should be at least about the current _ISL flowing through the selection element. That is, it is necessary to satisfy the following relational expression (3).

[Equation 3]
( ^M + n-2) I _HS ^(L) <I _SL

When the leakage current is large, not only is the current consumed unnecessarily, but it is necessary to increase the current driving capability of the driving circuit due to the leakage current, and the driving circuit becomes large. For example, FIG. 2 shows an example in which the memory cell C ₂₂ including the non-linear element S ₂₂ and the variable resistance element R ₂₂ is selected as the memory cell to be rewritten, but is supplied from the word line W2 to each bit line. The maximum total current is I _SL + I _HS ^(L) (m−1), and a capacity sufficient to supply this current is required for the drive circuit on the word line side. The same applies to the current supplied from the bit line B2 to each word line. In order to reduce the total leakage current, I _HS can be reduced or m and n can be reduced. However, if m and n are reduced, the memory cell array can be configured with a large number of small subarrays in order to realize a desired storage capacity. As a result, the area of the peripheral circuit portion is increased, and the bit cost is increased. Therefore, it is necessary to make _IHS sufficiently small.

From the above formula 3, it can be seen that increasing I _SL / I _HS is essential for power saving driving. When the memory cell array is driven by the ½ bias method during the write operation, a voltage that is approximately half of the voltage applied to the nonlinear element of the selected memory cell is applied to the nonlinear element of the half-selected memory cell. That is, regardless of the resistance state of the variable resistance element, the voltage V _SL applied to the selected memory cell during a write _operation, and, most of the voltage V _{SL / 2} that is applied to half-selected memory cell is applied to the non-linear element Then, since the current density J of the current flowing through the nonlinear element is expressed by a function of the electric field E, the following formula 4 is derived from the formula 3. Here, J (E) / J (0.5E) is referred to as a cutoff ratio.

[Equation 4]
J (E) / J (0.5E)> m + n-2

In the MIM element, the tunnel current density is calculated with the thickness of the insulator sandwiched between the conductors d and the tunnel barrier by the insulator as a triangular potential (see the electronic state diagram in FIG. 3), and the necessary cut FIG. 12 shows the calculated relationship between the applied electric field E (= V _SL / d) and the barrier height φ to obtain the off ratio. Higher cutoff ratio can be realized with lower applied electric field and higher barrier height.

  Therefore, it is necessary to increase the electric field applied to the nonlinear element and reduce the barrier height in order to realize a nonlinear element with a high current density. To realize a nonlinear element with a high cut-off ratio, it is applied to the nonlinear element. It is necessary to reduce the electric field and increase the barrier height. That is, a high current density and a high cut-off ratio are in a trade-off relationship.

As a writing current to a practical variable resistance element, 10 μA or more is necessary, and more preferably 100 μA or less from the viewpoint of low power consumption. When the area of the non-linear element and 30nm angle ~100nm angle, approximately 0.1 MA / cm ² or more current density is required, approximately 10 MA / cm ² or less of the current density is more desirable. On the other hand, in order to realize a memory cell array with a sub-array size of 1 Kbit, it is necessary to arrange memory cells in a 32 × 32 matrix, and a nonlinear element having a cut-off ratio of about 100 is required according to Equation 4 above. .

However, in the region where the upper limit is the curve indicated by the current density of 0.1 MA / cm ² in FIG. 11 and the lower limit is the curve indicated by the cut-off ratio 100 in FIG. A nonlinear element having a current density of ¹ MA / cm ² or more and a cutoff ratio of 100 or more can be realized. This region is a region sandwiched between two straight lines φ = 0.05E + 0.1 and φ = 0.1E + 0.1. The unit of the barrier height φ is eV, and the unit of the applied electric field E is MV / cm. When the voltage applied to the selected memory cell at the time of writing is V _SL [V], most of the voltage is applied to the nonlinear element. When the thickness of the insulator is d [nm], the applied electric field E (= V _SL / d) after unit conversion is 10 V _SL / d [MV / cm], and thus the above region has a straight line φ = 0 .5 V _SL /d+0.1 and a straight line φ = V _SL /d+0.1. This is a region satisfying both the relational expressions (1) and (2).

Therefore, by selecting the rewrite voltage V _SL , the film thickness d of the insulator used for the nonlinear element, and the barrier height φ so that the relationship between the barrier height φ and the applied electric field E is within the above region, sufficient It becomes possible to design a memory cell array with low power consumption and high integration, which is composed of memory cells having non-linear elements having current drive capability and cutoff characteristics.

One design example is shown below. For _example, changing the _{V SL} 4 _[V], by setting the d and 5 [nm], from 13, the barrier height phi, within the 0.5～0.9EV, the resistance state of the variable resistance element It can be set in accordance with the current density required to make it. For example, if the current density is 1 MA / cm ² , the diameter may be about 0.7 eV. The film thickness d of the insulator of the nonlinear element is more preferably about 5 nm or less in order to make the ON voltage of the nonlinear element a low voltage that is easy to use.

  Next, a conductor material and an insulator material used for the nonlinear element are selected. As a specific insulator material, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, yttrium oxide, or the like can be used. The band gap of the insulator (the energy difference between the energy at the bottom of the conduction band and the energy at the top of the valence band) and the electric field resistance are approximately correlated, and the electric field resistance increases as the band gap increases. For use in a high electric field of about several MV / cm as shown in FIG. 13, it is more preferable to select a material having a band gap of about 5 eV or more.

In order to ensure reliability, the electric field applied to the nonlinear element is preferably designed to be 10 MV / cm or less, and V _SL / d is preferably 1 or less.

  On the other hand, as the conductor material, a conductor material is selected so that the energy difference between the Fermi level of the conductor and the bottom of the conduction band of the insulator falls within the above-described range of the barrier height φ. To do.

  In the above insulator material, the energy at the bottom of the conduction band varies in the range from -1 to -4 eV from the vacuum level, but most is about 2.5 eV or less. From FIG. 13, when the barrier height φ is selected within a range of about 0.5 eV to 0.9 eV, the work function of the conductive material is required to be relatively small, about 3.4 eV or less. The work functions of simple metals are summarized in, for example, HB Michaelson, "The work function of the elements and its periodicity", Journal of Applied Physics, Vol. 48, pp. 4729, 1977, etc. Choose the right metal. Materials other than a single metal having a low work function include alkaline earths such as thorium tungsten (2.6 eV), barium tungsten (1.6 eV), barium oxide (1 eV), and strontium oxide (1.3 eV). Oxides, borides of rare earth elements such as lanthanum boride (2.5 eV), cerium boride (2.5 eV), thorium oxide (2.7 eV), and the like can be given. The work function value is shown in parentheses.

  Of the above insulator materials, those having a large difference between the energy at the bottom of the conduction band and the vacuum level (about 4 eV), such as tantalum oxide, are generally easy to use as a conductor material. 4-5 eV of metals and compounds can be used.

  If the above condition is satisfied for at least one of the first conductor and the second conductor sandwiching the insulator, electrons tunnel from one conductor satisfying the condition to the other conductor, and the necessary current described above A current that satisfies the density and the cutoff ratio flows. In addition, when a bidirectional current is passed during rewriting and reading, if the required current density differs depending on the direction of each current, the materials used for the first conductor and the second conductor are different, and no voltage is applied. The Fermi levels of the first conductor and the second conductor may be different. In the case of using a semiconductor for the conductor, the energy at the bottom of the conduction band of the semiconductor may be read as the Fermi level for convenience, and the nonlinear element may be configured according to the above guidelines. Here, tantalum oxide (the energy at the bottom of the conductor from the vacuum level −4 eV) is used as the insulator material, and tungsten (work function 4.5 eV) and cobalt (the work function is 4.5 eV) as the materials of the first conductor and the second conductor, respectively. When the work function 5 eV) is selected, the on-current when tungsten is positively biased can be made smaller than that when the cobalt electrode is positively biased.

As described above, the rewrite voltage V _SL and the film thickness d of the insulator of the nonlinear element are set, the required range of the barrier height φ is obtained, and the required range of the barrier height φ is satisfied. By selecting an insulator material and a conductor material, it is possible to design a memory cell array with low power consumption and high integration, which includes memory cells having nonlinear elements having sufficient current drive capability and cutoff characteristics.

Second Embodiment
In the first embodiment described above, when the rewrite voltage is applied by the ½ bias method, the majority of the voltage V _SL applied to the selected memory cell is applied to the nonlinear element, and is defined by Equations 1 and 2. The relationship between the desired barrier height φ of the non-linear element and the applied electric field E (the shaded area in FIG. 13) is derived. More preferably, a part of V _SL is also applied to the variable resistance element. Therefore, it is desirable to more accurately obtain the relationship between the barrier height φ of the nonlinear element and the applied electric field E.

Here, a voltage applied to the variable resistance element of the writing voltage _{V SL} and _{V R,} and _x = _V R _/ V _SL. V _SL −V _R = (1−x) V _SL is applied to the non-linear element of the selected memory cell, and the electric field applied to the non-linear element thereby becomes y = V _SL / d. ) Y.

For this reason, the relationship between the barrier height φ of the nonlinear element and the applied electric field E is equal to that obtained by replacing E with (1-x) y in FIG. That is, assuming that the formula representing the barrier height φ of the nonlinear element and the applied electric field E when the current density is 0.1 MA / cm ² is φ _A (E), φ _A (E) is the first embodiment ( When x = 0), it is a function of V _SL / d (= E), and more accurately becomes φ _A ((1−x) y).

Therefore, when φ _A (E) at x = 0 is a quadratic function and approximated by φ _A (E) = a ₀ E ² + b ₀ E + c ₀ , a part of the rewrite voltage is also applied to the variable resistance element. Φ _A (y, x) is expressed by the following formula 5.

[Equation 5]
φ _A (y, x) = a ₁ (x) y ² + b ₁ (x) y + c ₁ (x),
a ₁ (x) = a ₀ (1-x) ² ,
b ₁ (x) = b ₀ (1-x),
c ₁ (x) = c ₀

The equation representing the barrier height φ of the nonlinear element and the applied electric field E when the current density in FIG. 11 is 0.1 MA / cm ² is fitted with a quadratic curve, and the parameters (a ₀ , b ₀ , When c ₀ ) was obtained, a ₀ = −3.09 × 10 ⁻³ , b ₀ = 1.32 × 10 ⁻¹ , and c ₀ = 4.10 × 10 ⁻² were obtained. Here, the unit of barrier height phi _A is [eV], the unit of the applied electric field E is [MV / cm]. When the unit of the voltage V _SL is [V], the unit of the thickness d of the insulator is [nm], and y (= V _SL / d) [V / nm] is converted into a unit, y = 10 V _SL / d [MV] / Cm].

Next, the relationship between the barrier height φ and V _SL / d of a nonlinear element that satisfies a cutoff ratio of 100 or more when a part of the rewrite voltage is also applied to the variable resistance element will be described. The non-linear element of the selected memory cell is applied _V SL -V _R, because most of the half-selected memory cell _{V SL} / 2 is applied, placing a y _{= V SL} / d, cut-off ratio , J ((1-x) y) / J (y / 2).

The cut-off ratio is calculated for a plurality of different x, and the equation representing the barrier heights φ [eV] and y [MV / cm] of the nonlinear element with a cut-off ratio of 100 is expressed as φ _B (y, x) as each fitting parameter when the phi _B was fitted by the least square method as a secondary curve ^{_{(φ B = a 2 (x}} ) y 2 + b 2 (x) y + c 2) for _{y (a 2, b 2,} c 2 FIG. 16 shows the calculation of how () changes with respect to x. The fitting parameters obtained for six different x correspond to the markers (squares) in the figure, and the result of fitting them with a cubic function is shown by a solid line. In either case, the fitting could be performed with a cubic function with high accuracy. Each function form of the parameters (a ₂ , b ₂ , c ₂ ) footed as the cubic function is shown in Equation 6. In the range of x> 0.23, there is no solution of the barrier height φ and y that satisfies the cutoff ratio of 100 or more and the current density of 0.1 MA / cm ² or more. In order to increase, fitting is performed in the range of 0 ≦ x ≦ 0.23.

[Equation 6]
φ _B (y, x) = a ₂ (x) y ² + b ₂ (x) y + c ₂ (x),
a ₂ (x) = − 8.83 × 10 ⁻³ x ³ + 1.70 × 10 ⁻⁵ x ² + 5.94 × 10 ⁻⁴ x−2.31 × 10 ⁻³ ,
b ₂ (x) = 4.94 × 10 ⁻¹ x ³ + 3.53 × 10 ⁻² x ² + 5.87 × 10 ⁻² x + 7.54 × 10 ⁻² ,
c ₂ (x) = 7.62 × 10 ⁻¹ x ³ + 5.03 × 10 ⁻² x ² + 9.24 × 10 ⁻² x + 4.97 × 10 ⁻²

If x is determined from Equations 5 and 6, each parameter (a ₁ , b ₁ , c ₁ , a ₂ , b ₂ , c ₂ ) is determined, the current density is 0.1 MA / cm ² or more, and cut Since the off ratio is 100 or more, a relationship in which the barrier height φ [eV] and y [MV / cm] should be satisfied is obtained. For example, when x = 0.1, the barrier density φ and y of the non-linear element should be satisfied because the current density is 0.1 MA / cm ² or more and the cutoff ratio is 100 or more. The relationship is indicated by the hatched portion in FIG. Area of the shaded portion in FIG. 17 is a region where the current density is made the upper limit curve phi _A which satisfies 0.1 MA / cm ^2, the lower limit curve phi _B cutoff ratio satisfies 100. Shows the curve phi _A by a thin solid line shows the result of fitting it as a secondary curve ^{_{(φ A = a 1 y 2}} + b 1 y + c 1) by the thick dotted line. Also shows curve phi _B by a thin solid line shows the result of fitting it as a secondary curve ^{_{(φ B = a 2 y 2}} + b 2 y + c 2) by a bold dotted line. It can be seen that both curves φ _A and φ _B can be sufficiently reproduced by a quadratic curve.

Therefore, the ratio x to be divided to the variable resistance element of the writing voltage V _SL, it is possible to obtain the relationship between the barrier height satisfactory φ and V _{SL / d,} the barrier height φ and V _SL / By selecting the rewrite voltage V _SL , the film thickness d of the insulator used for the non-linear element, and the barrier height φ so as to satisfy the relationship with d, sufficient current drive capability and cutoff are achieved as in the first embodiment. It becomes possible to design a highly integrated memory cell array having low power consumption and comprising memory cells having nonlinear elements having characteristics.

<Third Embodiment>
In the first and second embodiments described above, the case where the rewrite voltage is applied by the ½ bias method has been described. However, the same applies to the case where the rewrite voltage is applied by the ３ bias method.

FIG. 18 shows voltage application conditions of the memory cell in the 1/3 bias method. In the 1/3 bias method, as shown in FIG. 18, a predetermined reference potential (0 V) is applied to a memory cell selected in the row direction via a selected bit line (here, B2) in the row direction. V _SL × 2/3 is applied to unselected memory cells via unselected bit lines, respectively. On the other hand, the memory cell selected in the column direction, the selected word line (here, W2) and V _SL via the memory cell of the non-selected in the column direction, V via the unselected word lines _SL / 3 is applied. As a result, in the half-selected memory cell in which only one of the rows or columns of the selected memory cell (for example, R ₂₂ ) is the same, the absolute value is 1/3 of the rewrite voltage V _SL applied to the selected memory cell. A voltage is applied. Therefore, when a voltage is applied to _{V SL} to the selected memory cell, (m + n-2) is the number of half-selected memory cell is applied 1 / _{3V SL,} a leakage current occurs. When the array size is increased, problems such as disturbance due to the half-selected voltage and increase in current consumption due to current (leakage current) flowing through the half-selected memory cell may occur.

Since it is desirable to make the leakage current as small as possible, the current I _SL flowing through the non-linear element of the selected memory cell and the current I _HS flowing through the non-linear element of each half-selected memory cell at the time of writing are also expressed by the above equation 3. The relational expression should be satisfied, and increasing I _SL / I _HS is essential for power saving driving. Since V _SL −V _R = (1−x) V _SL is applied to the non-linear element of the selected memory cell, and most of V _SL / 3 is applied to the half-selected memory cell, y = V _SL / d Then, instead of the above equation 4, the following equation 7 is derived from the equation 3.

[Equation 7]
J ((1-x) y) / J (y / 3)> m + n-2

  Here, the left side J ((1-x) y) / J (y / 3) in Equation 7 corresponds to the cut-off ratio in the 1/3 bias method. As in the first embodiment, in order to realize a memory cell array having a sub-array size of 1 Kbit, it is necessary to arrange memory cells in a 32 × 32 matrix. A non-linear element is required.

For a plurality of different x, the cut-off ratio in the 1/3 bias method is calculated, and an equation representing the barrier height φ [eV] and y [MV / cm] of the nonlinear element with a cut-off ratio of 100 is represented by φ _{As C} (y, x), each fitting parameter (a ₃ ) when φ _C is fitted with a quadratic curve (φ _C = a ₃ (x) y ² + b ₃ (x) y + c ₃ ) with respect to y by the least square method , B ₃ , c ₃ ) calculated how x changes with respect to x is shown in FIG. The fitting parameters obtained for each different x correspond to the markers (squares) in the figure, and the result of fitting them with a cubic function is shown by a solid line. In either case, the fitting could be performed with a cubic function with high accuracy. The respective function forms of the parameters (a ₃ , b ₃ , c ₃ ) footed as the cubic function are shown in Equation 8. In the range of x> 0.48, there is no solution of the barrier height φ and y that satisfies the cutoff ratio of 100 or more and the current density of 0.1 MA / cm ² or more. In order to increase, fitting is performed in the range of 0 ≦ x ≦ 0.48.

[Equation 8]
φ _C (y, x) = a ₃ (x) y ² + b ₃ (x) y + c ₃ (x),
a ₃ (x) = − 1.84 × 10 ⁻³ x ³ + 6.81 × 10 ⁻⁴ x ² + 4.99 × 10 ⁻⁴ x−1.20 × 10 ⁻³ ,
b ₃ (x) = 2.26 × 10 ⁻¹ x ³ −7.02 × 10 ⁻² x ² + 3.20 × 10 ⁻² x + 3.89 × 10 ⁻² ,
c ₃ (x) = 5.23 × 10 ⁻¹ x ³ −1.48 × 10 ⁻¹ x ² + 6.40 × 10 ⁻² x + 2.54 × 10 ⁻²

On the other hand, the relational expression φ _A (y, x) between the barrier height φ of the nonlinear element having a current density of 0.1 MA / cm ² and V _SL / d (= y) is that the voltage application condition at the time of rewriting is Regardless of the ½ bias method or the ３ bias method, it is expressed by the above formula 5.

If x is determined from Equations 5 and 8, each parameter (a ₁ , b ₁ , c ₁ , a ₃ , b ₃ , c ₃ ) is determined. In the 1/3 bias method, the current density is 0.1 MA / Since it is cm ² or more and the cut-off ratio is 100 or more, the relationship that the barrier height φ [eV] and y [MV / cm] should be satisfied is obtained. For example, when x = 0.1, the barrier density φ and y of the non-linear element should be satisfied because the current density is 0.1 MA / cm ² or more and the cutoff ratio is 100 or more. The relationship is indicated by the hatched portion in FIG. Area of the shaded portion in FIG. 20 is a region where the current density is made the upper limit curve phi _A which satisfies 0.1 MA / cm ^2, the lower limit curve phi _C cutoff ratio satisfies 100. Shows the curve phi _A by a thin solid line shows the result of fitting it as a secondary curve ^{_{(φ A = a 1 y 2}} + b 1 y + c 1) by the thick dotted line. Further, the curve φ _C is shown by a thin solid line, and the result of fitting it as a quadratic curve (φ _C = a ₃ y ² + b ₃ y + c ₃ ) is shown by a thick dotted line. It can be seen that both curves φ _A and φ _C can be sufficiently reproduced by a quadratic curve.

Therefore, even in rewriting by the 1/3 bias method, the relationship between the satisfactory barrier height φ and V _SL / d can be obtained from the ratio x of the rewriting voltage V _SL divided by the variable resistance element. By selecting the rewrite voltage V _SL , the film thickness d of the insulator used for the nonlinear element, and the barrier height φ so as to satisfy the relationship between the barrier height φ and V _SL / d, the first embodiment Similarly to the above, it is possible to design a highly integrated memory cell array with low power consumption, which is composed of memory cells having nonlinear elements having sufficient current driving capability and cutoff characteristics.

  The above-described embodiment is an example of a preferred embodiment of the present invention. The embodiment of the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention.

  INDUSTRIAL APPLICABILITY The present invention can be used for a nonvolatile semiconductor memory device, and in particular, includes a variable resistance element in which a resistance state transitions due to voltage application and the resistance state after the transition is held in a nonvolatile manner. Is available.

10: first electrode 11, 32: variable resistor 12: second electrode 13: first conductor 14, 31: insulator 15: second conductor 20, 30: word line 21, 33: bit line 100: book Nonvolatile semiconductor memory device according to invention (device of the present invention)
101, 101a to 101f: Memory cell array 102: Bit line decoder 103: Word line decoder 104: Read circuit 105: Voltage switch circuit 106: Voltage generation circuit 107: Control circuit 108: Control signal line 109: Address line 110: Data line a ₁ , b ₁ , c ₁ , a ₂ , b ₂ , c ₂ , a ₃ , b ₃ , c ₃ : fitting parameters B 1 to Bm: bit lines C _{11 to} C _mn : memory cells d: film thickness E of insulator _F: Fermi level _R 11 _{to R mn:} variable resistive element _S 11 _{to S mn:} nonlinear element _{V SL:} voltage applied to the selected memory cell W1 through Wn: word line x: voltage V applied to the selected memory cell of _SL, percentage is divided to the variable resistance element _{y: V} SL / d
φ: Barrier height

Claims (11)

A first electrode; a second electrode; and a variable resistor directly connected to the first electrode and the second electrode, wherein a resistance state is obtained by applying a voltage between the first electrode and the second electrode. A variable resistance element that transitions between two or more different states, and one resistance state after the transition is held in a nonvolatile manner;
A non-linear element comprising an insulator sandwiched between a first conductor and a second conductor,
A memory cell array in which a plurality of memory cells in which the variable resistance element and the nonlinear element are connected in series by connecting the second electrode and the first conductor are arranged in a matrix in the row and column directions, respectively. A non-volatile semiconductor memory device comprising:
When selecting a selected memory cell to be rewritten from among the memory cells in the memory cell array, and rewriting information stored in the selected memory cell,
A predetermined reference potential is applied to either the first electrode or the second conductor of the memory cell selected in the row direction.
V _SL / 2 [V] with respect to the reference potential is applied to either the first electrode or the second conductor of the memory cell that is not selected in the row direction.
V _SL [V] with reference to the reference potential is applied to either the first electrode or the second conductor of the memory cell selected in the column direction.
V _SL / 2 [V] is applied to either the first electrode or the second conductor of the memory cell that is not selected in the column direction with respect to the reference potential,
Of the absolute value V _SL of the rewrite voltage applied between the first electrode and the second conductor of the selected memory cell, the ratio of the voltage applied to the variable resistance element is x,
The insulator film thickness is d [nm],
If y = 10 × V _SL / d,
The energy difference [eV] between the energy at the bottom of the conduction band of the insulator and the Fermi level of at least one of the first conductor and the second conductor is a ₁ y ² + b ₁ y + c ₁ or less. And a ₂ y ² + b ₂ y + c ₂ or more,
a ₁ = −3.09 × 10 ⁻³ (1-x) ² ,
b ₁ = 1.32 × 10 ⁻¹ (1-x),
c ₁ = 4.10 × 10 ⁻² ,
a ₂ = −8.83 × 10 ⁻³ x ³ + 1.70 × 10 ⁻⁵ x ² + 5.94 × 10 ⁻⁴ x−2.31 × 10 ⁻³ ,
b ₂ = 4.94 × 10 ⁻¹ x ³ + 3.53 × 10 ⁻² x ² + 5.87 × 10 ⁻² x + 7.54 × 10 ⁻² ,
c ₂ = 7.62 × 10 ⁻¹ x ³ + 5.03 × 10 ⁻² x ² + 9.24 × 10 ⁻² x + 4.97 × 10 ⁻² ,
A non-volatile semiconductor memory device characterized by the above. A variable resistor that is directly connected to the first electrode, the second electrode, and the first electrode and indirectly to the second electrode via an insulator, and a voltage is applied between the first electrode and the second electrode; When applied, the resistance state transitions between two or more different states, and a plurality of memory cells having variable resistance elements in which one resistance state after the transition is held in a non-volatile manner, respectively in a row and column direction. A non-volatile semiconductor memory device having a memory cell array arranged in
When selecting a selected memory cell to be rewritten from among the memory cells in the memory cell array, and rewriting information stored in the selected memory cell,
A predetermined reference potential is applied to either the first electrode or the second electrode of the memory cell selected in the row direction.
V _SL / 2 [V] with respect to the reference potential is applied to either the first electrode or the second electrode of the memory cell that is not selected in the row direction.
V _SL [V] with respect to the reference potential is applied to either the first electrode or the second electrode of the memory cell selected in the column direction.
V _SL / 2 [V] is applied to either the first electrode or the second electrode of the memory cell that is not selected in the column direction with reference to the reference potential,
Of the absolute value V _SL of the rewrite voltage applied between the first electrode and the second conductor of the selected memory cell, the ratio of the voltage applied to the variable resistance element is x,
The insulator film thickness is d [nm],
If y = 10 × V _SL / d,
Energy difference [eV] between the energy of the bottom of the conduction band of the insulator and the Fermi level of the second electrode, or the energy of the bottom of the conduction band of the insulator and the bottom of the conduction band of the variable resistor At least one of the differences [eV] is a ₁ y ² + b ₁ y + c ₁ or less and a ₂ y ² + b ₂ y + c ₂ or more,
a ₁ = −3.09 × 10 ⁻³ (1-x) ² ,
b ₁ = 1.32 × 10 ⁻¹ (1-x),
c ₁ = 4.10 × 10 ⁻² ,
a ₂ = −8.83 × 10 ⁻³ x ³ + 1.70 × 10 ⁻⁵ x ² + 5.94 × 10 ⁻⁴ x−2.31 × 10 ⁻³ ,
b ₂ = 4.94 × 10 ⁻¹ x ³ + 3.53 × 10 ⁻² x ² + 5.87 × 10 ⁻² x + 7.54 × 10 ⁻² ,
c ₂ = 7.62 × 10 ⁻¹ x ³ + 5.03 × 10 ⁻² x ² + 9.24 × 10 ⁻² x + 4.97 × 10 ⁻² ,
A non-volatile semiconductor memory device characterized by the above. A first electrode; a second electrode; and a variable resistor directly connected to the first electrode and the second electrode, wherein a resistance state is obtained by applying a voltage between the first electrode and the second electrode. A variable resistance element that transitions between two or more different states, and one resistance state after the transition is held in a nonvolatile manner;
A non-linear element comprising an insulator sandwiched between a first conductor and a second conductor,
A memory cell array in which a plurality of memory cells in which the variable resistance element and the nonlinear element are connected in series by connecting the second electrode and the first conductor are arranged in a matrix in the row and column directions, respectively. A non-volatile semiconductor memory device comprising:
When selecting a selected memory cell to be rewritten from among the memory cells in the memory cell array, and rewriting information stored in the selected memory cell,
A predetermined reference potential is applied to either the first electrode or the second conductor of the memory cell selected in the row direction.
V _SL × 2/3 [V] is applied to either the first electrode or the second conductor of the memory cell that is not selected in the row direction with reference to the reference potential.
V _SL [V] with reference to the reference potential is applied to either the first electrode or the second conductor of the memory cell selected in the column direction.
V _SL / 3 [V] is applied to either the first electrode or the second conductor of the memory cell that is not selected in the column direction with reference to the reference potential,
Of the absolute value V _SL of the rewrite voltage applied between the first electrode and the second conductor of the selected memory cell, the ratio of the voltage applied to the variable resistance element is x,
The insulator film thickness is d [nm],
If y = 10 × V _SL / d,
The energy difference [eV] between the energy at the bottom of the conduction band of the insulator and the Fermi level of at least one of the first conductor and the second conductor is a ₁ y ² + b ₁ y + c ₁ or less. And a ₃ y ² + b ₃ y + c ₃ or more,
a ₁ = −3.09 × 10 ⁻³ (1-x) ² ,
b ₁ = 1.32 × 10 ⁻¹ (1-x),
c ₁ = 4.10 × 10 ⁻² ,
a ₃ = −1.84 × 10 ⁻³ x ³ + 6.81 × 10 ⁻⁴ x ² + 4.99 × 10 ⁻⁴ x−1.20 × 10 ⁻³ ,
b ₃ = 2.26 × 10 ⁻¹ x ³ −7.02 × 10 ⁻² x ² + 3.20 × 10 ⁻² x + 3.89 × 10 ⁻² ,
c ₃ = 5.23 × 10 ⁻¹ x ³ −1.48 × 10 ⁻¹ x ² + 6.40 × 10 ⁻² x + 2.54 × 10 ⁻² ,
A non-volatile semiconductor memory device characterized by the above. A variable resistor that is directly connected to the first electrode, the second electrode, and the first electrode and indirectly to the second electrode via an insulator, and a voltage is applied between the first electrode and the second electrode; When applied, the resistance state transitions between two or more different states, and a plurality of memory cells having variable resistance elements in which one resistance state after the transition is held in a non-volatile manner, respectively in a row and column direction. A non-volatile semiconductor memory device having a memory cell array arranged in
When selecting a selected memory cell to be rewritten from among the memory cells in the memory cell array, and rewriting information stored in the selected memory cell,
A predetermined reference potential is applied to either the first electrode or the second electrode of the memory cell selected in the row direction.
V _SL × 2/3 [V] is applied to either the first electrode or the second electrode of the memory cell that is not selected in the row direction with reference to the reference potential.
V _SL [V] with respect to the reference potential is applied to either the first electrode or the second electrode of the memory cell selected in the column direction.
V _SL / 3 [V] is applied to either the first electrode or the second electrode of the memory cell that is not selected in the column direction with reference to the reference potential,
Of the absolute value V _SL of the rewrite voltage applied between the first electrode and the second conductor of the selected memory cell, the ratio of the voltage applied to the variable resistance element is x,
The insulator film thickness is d [nm],
If y = 10 × V _SL / d,
Energy difference [eV] between the energy of the bottom of the conduction band of the insulator and the Fermi level of the second electrode, or the energy of the bottom of the conduction band of the insulator and the bottom of the conduction band of the variable resistor At least one of the differences [eV] is a ₁ y ² + b ₁ y + c ₁ or less and a ₃ y ² + b ₃ y + c ₃ or more,
a ₁ = −3.09 × 10 ⁻³ (1-x) ² ,
b ₁ = 1.32 × 10 ⁻¹ (1-x),
c ₁ = 4.10 × 10 ⁻² ,
a ₃ = −1.84 × 10 ⁻³ x ³ + 6.81 × 10 ⁻⁴ x ² + 4.99 × 10 ⁻⁴ x−1.20 × 10 ⁻³ ,
b ₃ = 2.26 × 10 ⁻¹ x ³ −7.02 × 10 ⁻² x ² + 3.20 × 10 ⁻² x + 3.89 × 10 ⁻² ,
c ₃ = 5.23 × 10 ⁻¹ x ³ −1.48 × 10 ⁻¹ x ² + 6.40 × 10 ⁻² x + 2.54 × 10 ⁻² ,
A non-volatile semiconductor memory device characterized by the above. (1-x) _VSL / d is 1 or less, The non-volatile semiconductor memory device as described in any one of Claims 1-4 characterized by the above-mentioned. A first electrode; a second electrode; and a variable resistor directly connected to the first electrode and the second electrode, wherein a resistance state is obtained by applying a voltage between the first electrode and the second electrode. A variable resistance element that transitions between two or more different states, and one resistance state after the transition is held in a nonvolatile manner;
A plurality of memory cells, each of which is connected in series by connecting the second electrode and the first conductor, and a non-linear element having an insulator sandwiched between the first conductor and the second conductor. A non-volatile semiconductor memory device having a memory cell array arranged in a matrix in the row and column directions,
When selecting a selected memory cell to be rewritten from among the memory cells in the memory cell array, and rewriting information stored in the selected memory cell,
An absolute value of a rewrite voltage applied between the first electrode and the second conductor of the selected memory cell is expressed as V _SL [V],
When the film thickness of the insulator is d [nm],
The energy difference [eV] between the energy at the bottom of the conduction band of the insulator and the Fermi level of at least one of the first conductor and the second conductor is (0.5 V _SL /d+0.1 A non-volatile semiconductor memory device characterized in that it is not less than (V _SL /d+0.1). A variable resistor that is directly connected to the first electrode, the second electrode, and the first electrode and indirectly to the second electrode via an insulator, and a voltage is applied between the first electrode and the second electrode; When applied, the resistance state transitions between two or more different states, and a plurality of memory cells having variable resistance elements in which one resistance state after the transition is held in a non-volatile manner, respectively in a row and column direction. A non-volatile semiconductor memory device having a memory cell array arranged in
When selecting a selected memory cell to be rewritten from among the memory cells in the memory cell array, and rewriting information stored in the selected memory cell,
The absolute value of the rewrite voltage applied between the first electrode and the second electrode of the selected memory cell is expressed as V _SL [V],
When the film thickness of the insulator is d [nm],
Energy difference [eV] between the energy of the bottom of the conduction band of the insulator and the Fermi level of the second electrode, or the energy of the bottom of the conduction band of the insulator and the bottom of the conduction band of the variable resistor A nonvolatile semiconductor memory device, wherein at least one of the differences [eV] is not less than (0.5 V _SL /d+0.1) and not more than (V _SL /d+0.1). _8. The nonvolatile semiconductor memory device according to claim 6, wherein V _SL / d is 1 or less.   The nonvolatile semiconductor memory device according to claim 1, wherein a thickness d of the insulator is 5 nm or less.   The nonvolatile semiconductor memory device according to claim 1, wherein the first conductor and the second conductor are made of the same material. The nonvolatile semiconductor memory device according to claim 1, wherein a band gap of the insulator is 5 eV or more.

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