CN110045793B

CN110045793B - Computing device and computing system

Info

Publication number: CN110045793B
Application number: CN201910460108.1A
Authority: CN
Inventors: 邬江; 张楠赓
Original assignee: Hangzhou Canaan Creative Information Technology Ltd
Current assignee: Hangzhou Canaan Creative Information Technology Ltd
Priority date: 2019-05-29
Filing date: 2019-05-29
Publication date: 2025-08-19
Anticipated expiration: 2039-05-29
Also published as: CN110045793A

Abstract

The present invention provides a computing device and computing system, comprising: multiple computing chips connected in series; and multiple LDO modules, each connected to the multiple computing chips; wherein the signal input terminal of each computing chip is connected to the output terminal of an LDO module. The computing device and computing system of the present invention utilize the LDO modules to supply power to the input signals of the computing chips, thereby improving signal transmission quality and transmission rate, and avoiding degradation of signal transmission quality caused by uneven voltage division between the computing chips.

Description

Computing device and computing system

Technical Field

The invention belongs to the technical field of computing, and particularly relates to a computing device and a computing system.

Background

At present, with the development of computing technology, the computing demands of large data volume and high complexity are increased, and the chip core voltage required for completing the complex computing is correspondingly increased. Since the computing chips are usually connected in series, the core voltage of the former stage chip is the reference ground voltage of the latter stage chip, and since the core voltage of the chip is increased, the reference ground voltage of the latter stage chip is increased, which causes signal interference and affects the signal transmission quality and transmission efficiency. If the signal is not disturbed, the amplitude of the signal needs to be increased. However, increasing the amplitude of the signal results in a significant increase in the cost of the system, and the amount of heat generated is also significantly increased, affecting the performance of the system.

In general, the existing computing device and computing system mainly have the technical defects that the partial voltage of a computing chip core is uneven, the signal transmission quality is affected, the transmission rate is low, and the use requirement cannot be met well.

Therefore, there is a need to provide a computing device and a computing system with good signal transmission quality and high transmission rate.

Disclosure of Invention

First, the technical problem to be solved

The present invention provides a computing device and a computing system to at least partially solve the above-mentioned technical problems.

(II) technical scheme

According to one aspect of the present invention, there is provided a computing device comprising:

a plurality of computing chips connected in series, and

The LDO modules are respectively connected with the computing chips;

The signal input end of each computing chip is connected with the output end of one LDO module.

In some embodiments, the plurality of computing chips are respectively a1 st computing chip to an n-th computing chip, wherein an input end of the k-th computing chip is connected with an output end of the k-1 st computing chip;

The plurality of LDO modules are respectively a1 st LDO module to an nth LDO module, wherein the signal input end of a kth computing chip is connected with the output end of the kth LDO module, n is more than or equal to 2, and k is more than or equal to 1 and less than or equal to n;

the LDO module has a reference ground input and a power supply input.

In some embodiments, the reference ground input of the kth LDO module is connected to the input of the kth computing chip, where k takes a value of 1.

In some embodiments, the reference ground input of the kth LDO module is connected to the output of the kth-1 computing chip, and k takes a value of 2~n.

In some embodiments, the computing device further includes a power module coupled to the power input of the LDO module.

In some embodiments, the power input voltage of the kth LDO module is 3-4 times the core voltage of the kth computing chip.

A computing system comprising one or more of the computing devices, further comprising:

an input data device connected with the computing device for receiving cloud data and transmitting the cloud data to the computing device, and

And the output data device is connected with the computing device and is used for transmitting the computing result of the computing device to the cloud.

In some embodiments, the computing system further comprises a heat sink comprising a liquid cooled heat sink unit and/or an air cooled heat sink unit.

In some embodiments, the computing device is a pluggable computing device.

In some embodiments, the pluggable computing device has a pluggable connector and/or a pluggable interface.

(III) beneficial effects

As can be seen from the technical scheme, the computing device and the computing system have at least one of the following advantages:

(1) The input signal of the calculation chip is supplied with power through the LDO module, the reference ground voltage of the LDO module is the same as the reference ground voltage of the calculation chip, and therefore, no difference of core voltage exists between the signal power supply of the calculation chip and the calculation chip, and the signal voltage of the calculation chip is not influenced even if the core voltage of the calculation chip is uneven, so that the signal transmission quality and the transmission rate are improved, the signal transmission quality is prevented from being reduced due to uneven voltage division of the calculation chip, and signal transmission interruption caused by serious uneven voltage division of the chip after the calculation chip is increased is also prevented.

(2) According to the computing device and the computing system, the voltage value of signal power supply is increased, and the nuclear voltage of the computing chip is increased, so that the computing device and the computing system can be used for replacing the increase of the power supply amplitude of LDO.

(3) The invention adopts the pluggable computing device which is provided with the pluggable connector or the interface, the computing device can be added according to the computing amount requirement, and the computing chip is correspondingly added, so that the overall computing force and the capability density can be improved, the replacement and the maintenance of the computing device are convenient, and the machine is conveniently upgraded according to the progress of the chip technology.

(4) The computing devices in the computing system can work independently, and can be assembled freely according to different power density requirements to form the computing system, so that the operation is convenient, and the use requirements of users are comprehensively met.

Drawings

FIG. 1 is a schematic diagram of a computing device according to the present invention.

FIG. 2 is a schematic diagram of a computing device according to an embodiment of the invention.

FIG. 3 is a schematic diagram of another embodiment of a computing device.

FIG. 4 is a schematic diagram of a computing device according to another embodiment of the invention.

FIG. 5 is a schematic diagram of another embodiment of a computing device.

FIG. 6 is a schematic diagram of a computing device according to another embodiment of the invention.

FIG. 7 is a schematic diagram of a computing system according to an embodiment of the invention.

FIG. 8 is a schematic diagram of a computing system according to another embodiment of the invention.

Fig. 9 is a schematic diagram of a heat sink according to another embodiment of the invention.

Fig. 10 is a schematic diagram of another structure of a heat sink according to another embodiment of the invention.

Fig. 11 is a schematic view of a heat sink according to another embodiment of the invention.

Fig. 12 is a schematic view of a heat sink according to another embodiment of the invention.

Fig. 13 is a schematic view of another structure of a heat sink according to another embodiment of the invention.

Fig. 14 is a schematic view of a heat sink according to another embodiment of the invention.

Detailed Description

The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.

As shown in FIG. 1, a computing device includes three computing chips A1, A2, A3 and three LDO modules M1, M2, M3. The three computing chips A1, A2 and A3 are connected in series, specifically, the output end of the computing chip A1 is connected with the input end of the computing chip A2, the output end of the computing chip A2 is connected with the input end of the computing chip A3, the output ends of the computing chips A1, A2 and A3 are all voltage output ends, and the input ends of the computing chips A1, A2 and A3 are all voltage input ends and can be marked as output ends or input ends of first voltage. The three LDO modules M1, M2, M3 are respectively connected with the three computing chips A1, A2, A3, specifically, the output end of the LDO module M1 is connected with the signal output end of the computing chip A1, the output end of the LDO module M2 is connected with the signal output end of the computing chip A2, the output end of the LDO module M3 is connected with the signal output end of the computing chip A3, the signal output ends of the computing chips A1, A2, A3 are output signal supply ends, i.e. input ends for respectively supplying voltage to the computing chips A1, A2, A3, are respectively used for supplying power to the output signals LDO of the computing chips A1, A2, A3, and can be recorded as input ends of second voltage, and the output ends of the LDO module M1, M2, M3 are voltage output ends, i.e. are respectively used for outputting the second voltage supplied to the computing chips A1, A2, A3. Among them, LDOs are low dropout regulators, which regulate the regulated output voltage generated by regulating the higher voltage input (subtracting the excess voltage from the applied input voltage). LDO devices have many different characteristics, such as low noise, wide input voltage, small size, low Iq, and processor connections, etc.

The signal power supply mode of the computing device shown in fig. 1 is to supply power to the output signal, that is, the output of the LDO module of this stage is used to supply power to the output signal of the computing chip of this stage. By adopting an output signal power supply mode, the reference ground of the LDO module powered by the signal is the ground of the signal of the previous stage, and the reference ground of the signal is the nuclear voltage of the signal of the previous stage when the signal is transmitted to the next stage, so that a nuclear voltage difference exists between the voltage of the input signal and the voltage of the calculation chip. For example, the signal transmission direction is from the output end of the computing chip A1 to the input end of the computing chip A2, and then from the output end of the computing chip A2 to the input end of the computing chip A3, and the chips are connected in series, so that the voltage output voltage Vcc of the computing chip A1 is the reference ground voltage of the A2 chip, the IO of the computing chip A1 is supplied by the LDO module, after the signal is transmitted to the computing chip A2, the voltage range of the signal is reduced from 0V to 1.8V (LDO supply voltage is 1.8V) to the threshold value of Vcc to 1.8V, if the voltage division of the chips is uneven, the Vcc voltage value is increased, and the signal is mistakenly considered to be low because the output high level cannot meet the high level threshold value of the input end of the next chip, and the signal transmission error is possibly caused.

The input power supply method of the second voltages of the calculation chips A1, A2, and A3 is any power supply method that can be conceived by those skilled in the art.

In view of this, the present invention provides a computing device, in which a signal power supply mode is used to supply power to an input signal, and by changing a signal power supply mode of a computing chip, degradation of signal transmission quality caused by uneven voltage division of the chip is avoided.

In one embodiment, as shown in FIG. 2, the computing device includes three computing chips A1, A2, A3 and three LDO modules M1, M2, M3. The three computing chips A1, A2 and A3 are connected in series, specifically, the output end of the computing chip A1 is connected with the input end of the computing chip A2, the output end of the computing chip A2 is connected with the input end of the computing chip A3, the output ends of the computing chips A1, A2 and A3 are all voltage output ends, and the input ends of the computing chips A1, A2 and A3 are all voltage input ends and can be marked as output ends or input ends of first voltage. The three LDO modules M1, M2, M3 are respectively connected with the three computing chips A1, A2, A3, specifically, the output end of the LDO module M1 is connected with the signal input end of the computing chip A1, the output end of the LDO module M2 is connected with the signal input end of the computing chip A2, the output end of the LDO module M3 is connected with the signal input end of the computing chip A3, the signal output ends of the computing chips A1, A2, A3 are output signal supply ends, i.e. input ends for respectively supplying voltage to the computing chips A1, A2, A3, are respectively used for supplying power to the output signals LDO of the computing chips A1, A2, A3, and can be denoted as input ends of second voltage, and the output ends of the LDO module M1, M2, M3 are voltage output ends, i.e. are respectively used for outputting the second voltage supplied to the computing chips A1, A2, A3.

The input signal of the calculation chip is supplied with power through the LDO module, the reference ground voltage of the LDO is the same as the reference ground voltage of the chip, so that the power supply of the chip signal and the chip have no difference of core voltage, the chip signal voltage is not influenced even if the core voltage of the chip is unevenly divided, and the signal transmission quality and the transmission rate are improved.

Further, as shown in fig. 3, the LDO module further has a reference ground input terminal and a power supply input terminal. Specifically, the reference ground input end of the LDO module M1 is connected to the input end of the computing chip A1, the reference ground input end of the LDO module M2 is connected to the input end (Al output end) of the computing chip A2, and the reference ground input end of the LDO module M3 is connected to the input end (A2 output end) of the computing chip A3.

In another implementation, as shown in FIG. 4, the computing device includes n computing chips A1, A2, A3, A.sub.A., an-1, an and n LDO modules M1, M2, M3, A.sub.A., mn-1, mn. The n computing chips A1, A2, A3, an-1 are connected in series, an-1 output end is connected with a computing chip A2 input end, a computing chip A2 output end is connected with a computing chip A3 input end, an-1 output end is connected with a computing chip An input end, an-1 output ends are voltage output ends, and computing chips A1, A2, an 3 output ends are voltage input ends, an-1, an input ends are voltage input ends and can be recorded as output ends or input ends of a first voltage. The n LDO modules M1, M2, M3, mn-1, mn are respectively connected to the n computing chips A1, A2, A3, an-1, specifically, the output end of the LDO module M1 is connected to the signal input end of the computing chip A1, the output end of the LDO module M2 is connected to the signal input end of the computing chip A2, the output end of the LDO module M3 is connected to the signal input end of the computing chip A3, the output end of the LDO module Mn-1 is connected to the signal input end of the computing chip An-1, the output end of the LDO module Mn is connected with the signal input end of the computing chip An, the signal output ends of the computing chips A1, A2 and A3 are output signal power supply ends, namely input ends for providing voltage for the computing chips A1, A2 and A3 respectively, the output signals of the computing chips A1, A2 and A3 respectively supply power and can be recorded as input ends of second voltage, and the output ends of the LDO module M1, M2 and M3 are voltage output ends, namely the second voltage provided for the computing chips A1, A2 and A3 respectively.

Further, as shown in fig. 5, the reference ground input terminal of the LDO module M1 is connected to the input terminal of the computing chip A1, the reference ground input terminal of the LDO module M2 is connected to the input terminal (A1 output terminal) of the computing chip A2, the reference ground input terminal of the LDO module M3 is connected to the input terminal (A2 output terminal) of the computing chip A3, the reference ground input terminal of the LDO module Mn-1 is connected to the input terminal (An-2 output terminal) of the computing chip An-1, and the reference ground input terminal of the LDO module Mn is connected to the input terminal (An-1 output terminal) of the computing chip An.

Referring to fig. 4-5, in summary, in the 1 st to n-th computing chips, the input end of any k-th computing chip is connected to the output end of the k-1 st computing chip, the signal input end of the k-th computing chip is connected to the output end of the k-th LDO module, n is greater than or equal to 2,1 is less than or equal to k < n, and when k takes a value of 1, the reference ground input end of the k-th LDO module is connected to the input end of the k-th computing chip. When the value of k is 2~n, the reference ground input end of the k LDO module is connected with the output end of the k-1 computing chip.

Of course, the number of the computing chips and the number of the LDO modules of the present invention are not limited to the numbers given in the foregoing embodiments, and may be appropriately adjusted by those skilled in the art according to the operation requirements.

In yet another embodiment, as shown in FIG. 6, the computing device further includes a plurality of power supply modules connected to the power supply inputs of the plurality of LDO modules. And the power supply input voltage of the LDO module is 3-4 times of the core voltage of the computing chip.

The invention also provides a computing system which comprises one or more computing devices, wherein the signal power supply mode of the one or more computing devices supplies power for input signals.

In an embodiment, the computing system further includes an input data device for receiving cloud data and transmitting to the computing device.

Specifically, as shown in fig. 7, the computing system includes P computing devices, which are a1 st computing device, a 2 nd computing device, and a 3 rd computing device, respectively, a P-1 st computing device, and a P-th computing device, wherein the 1 st to the P-th computing devices are sequentially connected, that is, the 1 st computing device is connected to the 2 nd computing device, the 2 nd computing device is connected to the 3 rd computing device, the P-1 st computing device is connected to the P-th computing device, and the input data device is connected to the 1 st computing device. The input data device transmits a plurality of input data to the 1 st computing device, the 1 st computing device extracts first data from the plurality of input data and transmits data other than the first data from the plurality of data to the 2 nd computing device, the 2 nd computing device extracts second data from the received data and transmits the remaining data to the 3 rd computing device, and so on, the P-1 st computing device extracts P-1 st data from the received data and transmits the remaining data to the P-th computing device.

In another embodiment, the computing system further includes an output data device connected to the computing device for transmitting the computing result of the computing device to the cloud.

Specifically, as shown in fig. 8, the computing system includes P computing devices, which are a1 st computing device, a2 nd computing device, and a3 rd computing device, respectively, a P-1 st computing device, and a P-th computing device, wherein the 1 st to P-th computing devices are sequentially connected, that is, the 1 st computing device is connected with the 2 nd computing device, the 2 nd computing device is connected with the 3 rd computing device, the P-1 st computing device is connected with the P-th computing device, and the output data device is connected with the P-th computing device. The 1 st computing device transmits the calculation result to the 2 nd computing device, the 2 nd computing device transmits the calculation result and the calculation result of the 1 st computing device to the 3 rd computing device, and so on, the P-1 st computing device transmits the calculation results of the 1 st to P-1 st computing devices to the P-th computing device, and the P-th computing device transmits the calculation results of the 1 st to P-th computing devices to the output data device, and the output data device transmits the calculation results to the cloud.

In yet another embodiment, the computing system further includes one or more heat sinks, which may be disposed external to the computing device or may be disposed internal to the computing device, that is, may dissipate heat individually for each computing device or may dissipate heat entirely by the entire system. Specifically, as shown in fig. 9, the radiator may include a liquid-cooled heat radiating unit. Alternatively, as shown in fig. 10, the radiator may include an air-cooled radiating unit. Still alternatively, as shown in fig. 11, the radiator may include both a liquid cooling heat dissipating unit and an air cooling heat dissipating unit.

In yet another embodiment, as shown in fig. 12, the computing system further comprises a control device coupled to the computing device for controlling the operation of the computing device. The number of control devices and computing devices included in the computing system may be suitably adjusted as desired.

Further, as shown in fig. 13, the computing device in the computing system is a pluggable computing device having a pluggable connector, and the control device has a pluggable interface that mates with the pluggable connector. Alternatively, as shown in fig. 14, the pluggable computing device has a pluggable interface and the control device has a pluggable connector that mates with the pluggable interface. The pluggable connector is connected with the pluggable interface in a golden finger-socket mode, a flat cable-socket mode, a plug-socket mode and the like.

The computing device and the control device are connected with the pluggable interface through the pluggable connector, so that the number of the connected pluggable computing devices can be conveniently adjusted according to the operation amount, the pluggable computing devices can be conveniently maintained and replaced, and the computing system can be conveniently upgraded according to the progress of chip technology.

The computing devices in the computing system can work independently, and can be assembled freely according to different power density requirements to form the computing system, so that the operation is convenient, and the use requirements of users are comprehensively met.

In summary, the computing device and the computing system provided by the invention avoid the reduction of signal transmission quality caused by uneven voltage division of the computing chip core, improve the signal transmission rate and better meet the use requirement.

Thus, the computing device and computing system of embodiments of the present invention have been described in detail with reference to the accompanying drawings. The present invention should be clearly recognized by those skilled in the art in light of the above description.

It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.

Of course, according to actual needs, the computing device and the computing system of the present invention may further include other parts, which are not described herein because they are irrelevant to the innovations of the present invention.

Similarly, it should be appreciated that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination may be employed to combine all features of the invention in this specification (including the accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so invented, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature of the invention in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in a related device according to embodiments of the present invention may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present invention can also be implemented as an apparatus or device program (e.g., a computer program and a computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present invention may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.

Moreover, the use of ordinal numbers such as "1," "2," "3," etc., in the description and the claims to modify a corresponding element does not by itself connote or indicate any ordinal number of elements, nor does it indicate the order in which an element is ordered from another element, or the method of manufacture, but rather the ordinal numbers are used merely to distinguish one element having a certain name from another element having a same name.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.

Claims

1. A computing device, comprising:

the LDO module is connected with the plurality of computing chips respectively;

The signal input end of each computing chip is connected with the output end of one LDO module, and the computing chips are respectively from a1 st computing chip to an n th computing chip, wherein the input end of the k+1 th computing chip is connected with the output end of the k computing chip;

the plurality of LDO modules are respectively from a 1 st LDO th module to an nth LDO module, wherein the signal input end of a kth computing chip is connected with the output end of the kth LDO module, n is more than or equal to 2, and k is more than or equal to 1 and less than or equal to n;

The reference ground input end of the kth LDO module is connected with the input end of the kth computing chip;

The k+1-th computing chip input end is a voltage input end, and the k-th computing chip output end is a voltage output end;

the reference ground input end of the k+ LDO module is connected with the output end of the k computing chip.

2. The computing device of claim 1, further comprising a power module coupled to the power input of the LDO module.

3. The computing device of claim 2, wherein a power input voltage of the kth LDO module is 3-4 times a core voltage of the kth computing chip.

4. A computing system comprising one or more computing devices as recited in any of claims 1-3, further comprising:

The cloud computing device comprises a computing device, an input data device and an output data device, wherein the computing device is used for receiving cloud data and transmitting the cloud data to the computing device, and the output data device is connected with the computing device and is used for transmitting a computing result of the computing device to the cloud.

5. The computing system of claim 4, further comprising a heat sink comprising a liquid cooled heat sink unit and/or an air cooled heat sink unit.

6. The computing system of claim 4, wherein the computing device is a pluggable computing device.

7. The computing system of claim 6, wherein the pluggable computing device has pluggable connectors and/or pluggable interfaces.