CN106774767A - Series-fed chip and system, virtual digit coin dig ore deposit machine and server - Google Patents
Series-fed chip and system, virtual digit coin dig ore deposit machine and server Download PDFInfo
- Publication number
- CN106774767A CN106774767A CN201611169618.6A CN201611169618A CN106774767A CN 106774767 A CN106774767 A CN 106774767A CN 201611169618 A CN201611169618 A CN 201611169618A CN 106774767 A CN106774767 A CN 106774767A
- Authority
- CN
- China
- Prior art keywords
- series
- chip
- unit
- powered
- fed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/189—Power distribution
Abstract
Ore deposit machine and server are dug the embodiment of the invention discloses a kind of series-fed chip and system, virtual digit coin, wherein, series-fed chip includes the n unit to be powered of serial connection, the n unit to be powered is powered using series system, form a voltage domain respectively on each unit to be powered, the supply voltage of the series-fed chip forms the n grades of voltage domain of series connection, wherein, n is the integer more than 1；A signal level converting unit is connected in series between adjacent unit to be powered, the level conversion for carrying out signal of communication between the unit two neighboring to be powered of connection.The embodiment of the present invention improves the service behaviour of unit to be powered, improves the integral working of chip, reduces whole production cost.
Description
Technical field
The present invention relates to power supply power supply technique, more particularly to a kind of series-fed chip and system, virtual digit coin dig
Ore deposit machine and server.
Background technology
Bit coin ore deposit machine in the market is substantially and digs ore deposit using the parallel connection type of DC/DC (DC-DC) chip
Machine, because DC/DC has that transformation efficiency is low, causes the waste of power supply energy, meanwhile, the circuit of DC/DC chips sets
Meter is harsher, increased the cost of requirement and the production design of design.
As the development of semiconductor technology, the working power voltage of chip are more and more lower, operating current is increasing, in order to
The conversion efficiency of power supply is maximized, prior art takes chip on printed circuit board (PCB) (Printed circuitboard, PCB)
The power supply mode of series connection, i.e.,：The power supply of chip and join end to end to form the voltage domain of plural serial stage, each voltage domain possesses one
Or several chips.
The content of the invention
The embodiment of the present invention provides a kind of technical scheme for carrying out series-fed.
The one side of the embodiment of the present invention, there is provided a kind of series-fed chip, the series-fed chip includes n
The unit to be powered of serial connection, the n unit to be powered is powered using series system, on each unit to be powered
Form a voltage domain respectively, the supply voltage of the series-fed chip forms the n grade voltage domain connected, wherein, n be more than
1 integer；A signal level converting unit is connected in series between adjacent unit to be powered, for being treated in the two neighboring of connection
The level conversion of signal of communication is carried out between power supply unit.
Optionally, n interval being independently arranged, for realizing different voltage domains is also included in the series-fed chip
From deep trap, each unit to be powered in the n units to be powered is located in a deep trap respectively.
Optionally, the deep trap includes N-type deep trap DEEP-NWELL or p-type deep trap DEEP-PWELL.
Optionally, each described signal level converting unit includes high to Low signal level modular converter and low to high respectively
Signal level modular converter.
Optionally, each described signal level converting unit is located in a deep trap respectively；It is to be powered in each deep trap
Unit, respectively by the low to high signal level modular converter in the signal level converting unit and upper level voltage domain
Unit connection to be powered, by high to Low signal level modular converter and next step voltage in the signal level converting unit
Unit to be powered connection in domain.
Optionally, the chip core of one or more parallel connections is included in each described unit to be powered respectively；Each
The signal level converting unit connection that each chip core in the unit to be powered is connected with place unit to be powered respectively.
Optionally, each chip core includes one group of computing unit and/or memory cell respectively.
Optionally, the signal level converting unit specifically using capacitive couplings, differential signal transmission method and or two poles
Tube voltage drop method is realized.
The other side of the embodiment of the present invention, there is provided a kind of cascade electric power system, including control device, and in power supply
Be connected in series between end and ground, the m series-fed chip as described in claim 1 to 8 any one；Supplied in each series connection
A big voltage domain is formed on electrical chip respectively, the cascade electric power system forms the m grades of big electricity of series connection between power supply and ground
Pressure domain；A chromacoder is connected in series between two neighboring series-fed chip respectively, for the adjacent of connection
The conversion of level signal and differential signal between two series-fed chips；The control device respectively with each chromacoder
Connection, for controlling each chromacoder to carry out the conversion of level signal and differential signal；
Wherein, every grade big voltage domain includes the n grades of voltage domain of series connection of correspondence series-fed chip, and m is whole more than 1
Number.
The another aspect of the embodiment of the present invention, there is provided another cascade electric power system, including control device, and supplying
Be connected in series between electric end and ground, the m series-fed chip as described in claim 1 to 8 any one；In each series connection
Form a big voltage domain on power supply chip respectively, the cascade electric power system forms the big of m grades of series connection between power supply and ground
Voltage domain；A chromacoder is connected in series between each series-fed chip and ground respectively, the string for realizing connection
The conversion of level signal and differential signal between alliance electrical chip and ground；The control device connects with each chromacoder respectively
Connect, for controlling each chromacoder to carry out the conversion of level signal and differential signal；
Wherein, every grade big voltage domain includes the n grades of voltage domain of series connection of correspondence series-fed chip, and m is whole more than 1
Number.
Optionally, also it is connected with each series-fed chip respectively including adjustment circuit, electricity is carried out to each series-fed chip
The adjustment of pressure, temperature or frequency.
Optionally, when the adjustment unit enters line frequency adjustment to each series-fed chip, specifically for：
Each series-fed chip is directed to respectively, according to the work of each unit to be powered in predetermined period detection series-fed chip
Whether normal make state；
If needing the working state abnormal of power supply unit, in the range of predeterminated frequency according to predeterminated frequency step-length improve or
Reduce the working frequency of the unit to be powered of working state abnormal.
Optionally, also including being respectively the m fan that m series-fed chip is correspondingly arranged, it is right that each fan is used for
The series-fed chip answered is radiated；
When the adjustment unit enters trip temperature adjustment to each series-fed chip, specifically for：
Each series-fed chip is directed to respectively, according to the work of each unit to be powered in predetermined period detection series-fed chip
Whether normal make state；
If needing the working state abnormal of power supply unit, improved in the range of preset rotation speed or reduce working condition not just
The rotating speed of the fan of series-fed chip where normal unit to be powered.
Optionally, when the adjustment unit detects whether the working condition of unit to be powered is normal, specifically for：
Whether the working condition of the condition adjudgement unit to be powered that the status register according to unit to be powered is indicated is normal,
The state that the status register is indicated includes following any one or more：Voltage status, state of temperature, working frequency shape
State；Or the work of unit to be powered is judged to being sent to the feedback data of the data of the unit to be powered according to unit to be powered
Whether normal make state.
Optionally, when the adjustment unit carries out voltage adjustment to each series-fed chip, the adjustment unit is specially m
Individual, each adjustment unit is connected in parallel with a series-fed chip respectively；
The adjustment unit includes resistance or mu balanced circuit.
Optionally, also including m Auxiliary Power Units, each Auxiliary Power Units connects with a series-fed chip respectively
Connect, for being powered to other units beyond series-fed chip chips kernel.
Optionally, the chromacoder specifically uses capacitive couplings, optocoupler transformation approach, transformer transformation approach, difference
Sub-signal transmission method and or diode drop method realize.
Another aspect of the embodiment of the present invention, there is provided a kind of virtual digit coin dig ore deposit machine, including cabinet, positioned at cabinet
Internal control panel and the control panel expansion board for connecting and the operation board being connected with expansion board, the operation board include this hair
The series-fed system described in series-fed chip or any of the above-described embodiment of the invention described in bright any of the above-described embodiment
System.
Another aspect of the embodiment of the present invention, there is provided a kind of server, including the internal memory that mainboard is electrically connected with mainboard
Disk and hard disk, power supply and CPU for main board power supply, the CPU are any of the above-described comprising the present invention
The cascade electric power system described in series-fed chip or any of the above-described embodiment of the invention described in embodiment.
Series-fed chip and system, virtual digit coin digging ore deposit machine and the service provided based on the above embodiment of the present invention
Device, series-fed chip includes the n unit to be powered of serial connection, is powered using series system, adjacent list to be powered
A signal level converting unit is connected in series between unit to carrying out the electricity of signal of communication between the two neighboring unit to be powered
Flat turn is changed, and thus, the present invention is realized in chip internal series-fed.Because the unit to be powered being cascaded is all same
Chip internal, influence of the voltage drop that the dead resistance come per chips packaging belt is produced to chip operation performance is smaller, lifting
The service behaviour of unit to be powered；Also, because the characteristic inside same chip is basically identical, respectively treating inside same chip
Otherness between power supply unit is smaller so that voltage's distribiuting evenly can be obtained per voltage order one domain, chip is improve
Integral working, reduces whole production cost.
Below by drawings and Examples, technical scheme is described in further detail.
Brief description of the drawings
The Description of Drawings embodiments of the invention of a part for specification are constituted, and together with description for explaining
Principle of the invention.
Referring to the drawings, according to following detailed description, the present invention can be more clearly understood from, wherein：
Fig. 1 is the structural representation of series-fed chip one embodiment of the present invention.
Fig. 2 is the structural representation of another embodiment of series-fed chip of the present invention.
Fig. 3 is the structural representation of another embodiment of series-fed chip of the present invention.
Fig. 4 is a structural representation of chip exterior series-fed.
Fig. 5 is the structural representation of cascade electric power system one embodiment of the present invention.
Fig. 6 is the structural representation of another embodiment of cascade electric power system of the present invention.
Fig. 7 is the structural representation of another embodiment of cascade electric power system of the present invention.
Fig. 8 is the structural representation of cascade electric power system further embodiment of the present invention.
Fig. 9 is the structural representation that virtual digit coin of the present invention digs ore deposit machine one embodiment.
Figure 10 is the structural representation of server one embodiment of the present invention.
Specific embodiment
Describe various exemplary embodiments of the invention in detail now with reference to accompanying drawing.It should be noted that：Unless had in addition
Body illustrates that the part and the positioned opposite of step, numerical expression and numerical value for otherwise illustrating in these embodiments do not limit this
The scope of invention.
Simultaneously, it should be appreciated that for the ease of description, the size of the various pieces shown in accompanying drawing is not according to reality
Proportionate relationship draw.
The description only actually at least one exemplary embodiment is illustrative below, never as to the present invention
And its any limitation applied or use.
May be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as a part for specification.
It should be noted that：Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined in individual accompanying drawing, then it need not be further discussed in subsequent accompanying drawing.
Fig. 1 is the structural representation of series-fed chip one embodiment of the present invention.The series-fed of the embodiment of the present invention
Chip, i.e.,：The chip being powered using series-fed mode.As shown in figure 1, the series-fed chip bag of the embodiment of the present invention
The n unit to be powered of serial connection is included, the n unit to be powered is powered using series system, in each list to be powered
Form a voltage domain in unit respectively, the supply voltage of series-fed chip forms the n grade voltage domain connected, wherein, n be more than
1 integer；A signal level converting unit is connected in series between adjacent unit to be powered, for being treated in the two neighboring of connection
The level conversion of signal of communication is carried out between power supply unit, i.e.,：By one in two neighboring unit to be powered unit hair to be powered
The level of the signal of communication for sending, is sent to another unit to be powered after the level for being converted to another unit to be powered.
Based on the above embodiment of the present invention provide series-fed chip, series-fed chip include n be connected in series
Unit to be powered, is powered using chip internal series system, and a signal electricity is connected in series between adjacent unit to be powered
To carrying out the level conversion of signal of communication between the two neighboring unit to be powered, thus, the present invention is realized flat converting unit
In chip internal series-fed.Because the unit to be powered being cascaded is all inside same chip, per chips packaging belt
Influence of the voltage drop that the dead resistance come is produced to chip operation performance is smaller, improves the service behaviour of unit to be powered；
Also, because the characteristic inside same chip is basically identical, the otherness between unit each to be powered inside same chip compared with
It is small so that voltage's distribiuting evenly can be obtained per voltage order one domain, the integral working of chip is improve, reduce whole
Production cost.
Specifically, in the series-fed chip of the embodiment of the present invention, one can be respectively included in each unit to be powered
Individual chip core (core), or, the chip core of multiple parallel connections can be respectively included in each unit to be powered.Each
Chip core can include one group of computing unit and memory cell, or can also only include computing unit or memory cell.Its
In, the signal level converting unit that each chip core in each unit to be powered is connected with place unit to be powered respectively connects
Connect.Fig. 2 is the structural representation of another embodiment of series-fed chip of the present invention, and Fig. 2 is shown in each unit to be powered
Include an embodiment for chip core respectively.Fig. 3 is the structural representation of another embodiment of series-fed chip of the present invention,
Fig. 3 includes the embodiment of the chip core of multiple parallel connections respectively in showing each unit to be powered.
Chip core per step voltage domain, includes P-channel metal-oxide-semiconductor (P-channel respectively in its circuit
Metal Oxide Semiconductor, PMOS) manage and N-channel metal-oxide semiconductor (MOS) (N-channel metal
Oxide semiconductor, NMOS) pipe.The present inventor realize it is of the invention during find, per step voltage domain chip
Kernel, the substrate of its PMOS is connected with the supply voltage or operating voltage (VDD) in this step voltage domain, and this step voltage domain
VDD again be connected with the ground (VSS) of upper level voltage domain, if do not isolated, the chip core of upper level voltage domain
The substrate of NMOS tube is just connected with the N-type trap of this step voltage domain chip core PMOS, so as to cause short circuit.
Referring back to Fig. 2 and Fig. 3, in the series-fed chip of yet another embodiment of the invention, n can also be included for real
The deep trap isolated between existing different voltage domains, this separate setting of n deep trap is mutually not attached to, every in n unit to be powered
Individual unit to be powered is located in a deep trap respectively, so that the isolation between different voltage domains on the same chip is realized, effectively
Avoid formation short circuit between different voltage domains.
Specifically, if the substrate of series-fed chip is P type substrate, the deep trap in various embodiments of the present invention is specifically N
Moldeed depth trap (DEEP-NWELL), NMOS tube and its p-type trap and PMOS and its N-type trap per step voltage domain are arranged on one
In DEEP-NWELL；If the substrate of series-fed chip is N-type substrate, the deep trap in each embodiment is specifically p-type deep trap
(DEEP-PWELL), the NMOS tube and its p-type trap and PMOS and its N-type trap per step voltage domain are arranged on a DEEP-PWELL
In.The merely exemplary deep trap shown a case that in various embodiments of the present invention is N-type deep trap, people in the art in Fig. 2 and Fig. 3
Record of the member based on the embodiment of the present invention, can know implementing using p-type deep trap.
Further, in a specific example of the above-mentioned each series-fed chip embodiment of the present invention, each signal electricity
Flat converting unit includes high to Low signal level modular converter (H2L) and low to high signal level modular converter (L 2H) respectively.
For details, reference can be made to Fig. 2, not shown in Fig. 3, the record that those skilled in the art are based on the embodiment of the present invention can take similar side
Formula realizes the concrete structure of signal level converting unit in the embodiment shown in fig. 3.
Specifically, in various embodiments of the present invention, signal level converting unit can for example be believed using capacitive couplings, difference
Number transmission method and or diode drop method realize.
In addition, as shown in Fig. 2 each signal level converting unit can be separately positioned in a deep trap, each deep trap
In unit to be powered, respectively by the low to high signal level modular converter in signal level converting unit and upper level voltage
Unit to be powered connection in domain, by the high to Low signal level modular converter in signal level converting unit and next stage electricity
Unit to be powered connection in pressure domain.The concrete structure of the embodiment not shown in Fig. 3, those skilled in the art are based on the present invention
The record of embodiment can take similar fashion to realize the specific knot of signal level converting unit in the embodiment shown in fig. 3
Structure.Because the voltage domain formed on different units to be powered is of different sizes, upper level voltage domain is higher than this step voltage domain, this level
Voltage domain again be higher than next stage voltage domain, per step voltage domain unit to be powered by low to high signal level modular converter with it is upper
Unit to be powered connection in voltage order one domain, low to high signal level modular converter can be by this step voltage domain unit to be powered
The signal of transmission is converted to the unit to be powered being sent in upper level voltage domain after the signal of upper level voltage domain；Per step voltage
The unit to be powered in domain is connected by high to Low signal level modular converter with the unit to be powered in next stage voltage domain, and height is arrived
The signal that this step voltage domain unit to be powered sends can be converted to low-signal levels modular converter the letter of next stage voltage domain
The unit to be powered in next stage voltage domain is sent to after number, so as between series-fed chip internal realizes different voltage domains
Communication.
Fig. 4 is a structural representation of chip exterior series-fed.It is that core is taken on PCB in technology shown in Fig. 4
The power supply mode of piece series connection is powered, i.e.,：The supply voltage of chip and ground join end to end to be formed n grades connect voltage domain, often
Individual voltage domain possesses one or several chips, and a chip core (core) is packaged with every chips, and one is passed through during encapsulation
Be bundled in the pin of chip core on the pin of chip by metal wire, and a resistance can be produced based on the metal wire and binding,
The resistance is the dead resistance Rb that packaging belt comes on chip, also referred to as encapsulates dead resistance.Power supply mode shown in Fig. 4 is at this
Chip exterior series-fed mode is also referred to as in inventive embodiments.By Fig. 4 it can be seen that, when using chip exterior series-fed side
When formula is powered, the voltage at each chip core two ends is (VDD-2*Iop*Rb).Wherein, VDD is supply voltage, and Iop is work
Electric current, Rb is encapsulation dead resistance.Based on easy analysis, it is assumed that the encapsulation dead resistance resistance of all chip pins is equal to
Rb。
Realize it is of the invention during, the present inventor by study find, take as shown in Figure 4 chip exterior connect
Power supply mode is powered, and there is problems with to I haven't seen you for ages：
One is the service behaviour that the voltage drop that the dead resistance that packaging belt comes on every chips is produced can influence chip, especially
Be in chip operating voltage than relatively low, and operating current than it is larger when, the electricity that the encapsulation dead resistance on chip is produced
Pressure drop can become apparent from；Two is for series-fed, it is intended that be every chips working characteristics (for example, temperature, frequency) it is complete
Complete the same, the voltage so per step voltage domain could be just the same, but in actual production process, every chips of series connection due to
The reason for production process of semiconductor, can produce difference, and the working characteristics per chips is different, so that per step voltage
The voltage in domain is not substantially uniformity, and different per voltage order one domain voltage can allow chip in working characteristics in turn
Otherness become it is bigger so that voltage's distribiuting is more uneven.Therefore, if the power supply mode of chip exterior series connection is supplied
Electricity, just must go to select the much the same chip of working characteristics to carry out series-fed, which results in production in process of production
The rising of cost, reduces production efficiency.
And pass through the embodiment shown in Fig. 2, the series-fed chip based on the embodiment of the present invention, using chip internal
When series system is powered, n voltage at chip core two ends of whole chip internal is (n*VDD-2*Iop*Rb), therefore,
Voltage on each chip core is equal to (VDD-2*Iop*Rb/n), and the voltage that encapsulation dead resistance is produced is reduced to 2*Iop*Rb/
N, relative to the power supply mode that the chip exterior shown in Fig. 4 is connected, the embodiment of the present invention entirely encapsulates the electricity of dead resistance generation
Pressure drop is lowered by n times, improves the service behaviour of chip core, so as to improve the workability of whole series-fed chip
Energy.Further, since the chip core being cascaded is all inside same chip, the otherness (example between each chip core
Such as temperature) it is more much smaller than the otherness of different chip chips kernels, compared to the power supply mode that chip exterior is connected, this hair
Bright embodiment each voltage domain can obtain voltage's distribiuting evenly, and it also avoid selecting in production process chip this
Process, improves the efficiency of production, while the yields of product can be also improved, so as to reduce whole production cost.
Fig. 5 is the structural representation of cascade electric power system one embodiment of the present invention.As shown in figure 5, the string of the embodiment
Alliance electric system includes control device, and m series-fed chip being connected in series between feeder ear VDD and ground VSS, this hair
Series-fed chip in bright embodiment is specially the series-fed chip of any of the above-described embodiment of the invention.Supplied in each series connection
A big voltage domain is formed on electrical chip respectively, cascade electric power system forms the m grades of big voltage domain of series connection between power supply and ground.
A chromacoder is connected in series between two neighboring series-fed chip respectively, adjacent two to connection are respectively used to
The conversion of level signal and differential signal between individual series-fed chip.Control device is connected with each chromacoder respectively,
For controlling each chromacoder to carry out the conversion of level signal and differential signal, so that directly real by chromacoder
Signal transmission between the two neighboring series-fed chip of existing its connection.Wherein, every grade big voltage domain includes that correspondence series connection is supplied
The n grades of voltage domain of series connection of electrical chip, m is the integer more than 1.Fig. 6 is another embodiment of cascade electric power system of the present invention
Structural representation.As shown in fig. 6, the cascade electric power system of the embodiment includes control device, and in feeder ear VDD and ground VSS
Between m series-fed chip being connected in series, the series-fed chip in the embodiment of the present invention is specially above-mentioned of the invention
The series-fed chip of one embodiment.Form big a voltage domain, cascade electric power system respectively on each series-fed chip
The m grades of big voltage domain of series connection is formed between power supply and ground.One is connected in series between each series-fed chip and ground respectively
Chromacoder, for the conversion of level signal and differential signal between the series-fed chip and ground of realizing connection.Control
Device is connected with each chromacoder respectively, for controlling each chromacoder to carry out turning for level signal and differential signal
Change.Wherein, every grade big voltage domain includes the n grades of voltage domain of series connection of correspondence series-fed chip, and m is the integer more than 1.Control
Device controls a chromacoder to be directly realized by between the series-fed chip and ground of a chromacoder connection
Level signal and differential signal conversion, then control another chromacoder realize with another signal converting means
The conversion of the level signal and differential signal between the series-fed chip of connection is put, so as to realize above-mentioned two signal converting means
Put the signal transmission between the series-fed chip of connection.
In concrete practice, typically the chip core voltage of the high current of series-fed chip is supplied using power supply circuit
Electricity, the earth terminal of upper level voltage domain series-fed chip as this step voltage domain chip to be powered feeder ear, this step voltage
The earth terminal of domain chip to be powered as next stage voltage domain chip to be powered feeder ear, m series-fed chip is according to this
Annexation is sequentially connected in series.
In a specific example of each cascade electric power system embodiment of the invention, chromacoder can be with switching levels
Signal and differential signal, can specifically use but be not limited to following any one or more mode and realize：Capacitive couplings, optocoupler
Transformation approach, transformer transformation approach, differential signal transmission method, diode drop method.
For example, when chromacoder is realized using optocoupler transformation approach, the two neighboring series connection of chromacoder connection
Power supply chip is connected by photoelectrical coupler.When chromacoder is realized using transformer transformation approach, chromacoder connects
The two neighboring series-fed chip for connecing is connected by transformer.When chromacoder is realized using differential signal transmission method,
Signal level conversion between the two neighboring series-fed chip of chromacoder connection passes through USB
The standard such as (Universal Serial Bus, USB), deserializer (SERDES) or the differential signal such as privately owned are realized.
When chromacoder is realized using diode drop method, the two neighboring series-fed chip of chromacoder connection passes through
Diode is connected.
Fig. 7 is the structural representation of another embodiment of cascade electric power system of the present invention.Fig. 8 is series-fed system of the present invention
The structural representation of further embodiment of uniting.As shown in Figure 7 and Figure 8, in the cascade electric power system of the various embodiments described above of the present invention
In, adjustment circuit can also be included, it is connected with each series-fed chip respectively, voltage, temperature are carried out to each series-fed chip
Or frequency adjustment, so that all series-fed chips are in normal operating conditions.
In a specific example of the above-mentioned each cascade electric power system embodiment of the present invention, adjustment circuit is to each series-fed
When chip enters line frequency adjustment, as frequency regulating circuit, specifically can be by a detector, respectively for each series-fed
Whether chip, the working condition according to each unit to be powered in predetermined period detection series-fed chip is normal；If having to be powered
The working state abnormal of unit, specifically can be by an adjuster, according to predeterminated frequency step-length in the range of predeterminated frequency
Improve or reduce the working frequency of the unit to be powered of working state abnormal.
The working frequency of series-fed chip, the overtension shared or too low, can all influence its normal work.The present invention
Embodiment is limited in the range of predeterminated frequency the working frequency of the unit to be powered for improving or reducing working state abnormal, i.e.,：
Working frequency after ensureing unit raising to be powered or reducing is without departing from the predeterminated frequency scope.If according to predeterminated frequency step-length
After improving or reducing working frequency, its working frequency can exceed predeterminated frequency scope, then be able to will be carried when working frequency is improved
Working frequency after height limits the upper frequency limit to predeterminated frequency；When working frequency is reduced, by the work after reduction
Frequency limits the lower-frequency limit to predeterminated frequency.By the working frequency for changing unit to be powered, thus it is possible to vary this is treated
The supply voltage that the power consumption of power supply unit, heat dissipation capacity, the temperature of place chip and the chip are shared.For example, reduce by one to wait to supply
The working frequency of electric unit, the power consumption of the unit to be powered can be reduced, and heat dissipation capacity can be reduced, and reduce the temperature of its whole chip,
So as to the supply voltage that the series-fed chip is shared can be reduced；Conversely, improving a working frequency for unit to be powered, this is treated
The power consumption of power supply unit can be improved, and heat dissipation capacity can increase, and the temperature of its whole chip can be raised, so that the series-fed chip point
The supply voltage of load can be raised.
Predeterminated frequency scope therein is each unit to be powered or the frequency range that wherein chip core can work in chip,
For example can be 200MHZ~700MHZ, predeterminated frequency step-length for example can be 6.25MHz.List each to be powered in due to chip
Cascaded structure is used between unit, when changing the working frequency of wherein one or more units to be powered, other can be influenceed in chip
The supply voltage that unit to be powered is shared, consequently, it is possible to influenceing the working condition of other units to be powered.The present inventor is based on grinding
Study carefully discovery, when predeterminated frequency step-length is set to 6.25MHz, can both be effectively improved the abnormal list to be powered of current operating state
First working condition, the normal work of the normal unit to be powered of other working conditions in chip is not interfered with also.
In a specific example in the above-mentioned each cascade electric power system embodiment of the present invention, respectively m can also be included
The m fan that individual series-fed chip is correspondingly arranged, each fan is respectively used to be carried out for a corresponding series-fed chip
Radiating.When adjustment circuit enters trip temperature adjustment to each series-fed chip, as temperature adjustment circuit, specifically can be by one
Detector, respectively for each series-fed chip, according to the work of each unit to be powered in predetermined period detection series-fed chip
Whether normal make state；If needing the working state abnormal of power supply unit, can specifically be turned default by an adjuster
The rotating speed of the fan of series-fed chip where the unit to be powered of working state abnormal is improved or reduced in fast scope.
Unit to be powered or wherein chip core it is too high or too low for temperature, can all influence its normal work.It is of the invention real
A default range of speeds in example is applied, in the range of preset rotation speed, the temperature of series-fed chip will not be too high or too low for fan
So as to influence the normal work of unit wherein to be powered.The embodiment of the present invention is limited in the range of preset rotation speed and improves or reduce work
Make the rotating speed of fan in series-fed chip where the abnormal unit to be powered of state, i.e.,：Ensure to improve or reduce aft-fan
Rotating speed without departing from the preset rotation speed scope.By the rotating speed for changing fan, thus it is possible to vary the overall temperature of series-fed chip
The supply voltage spent and its share.For example, improving the rotating speed of the fan of series-fed chip, the temperature of its whole chip can be reduced
Degree, so that the supply voltage that the series-fed chip is shared can be improved；Conversely, the rotating speed of the fan of series-fed chip is reduced,
The temperature of its whole chip can be raised, so that the supply voltage that the series-fed chip is shared can be reduced.
In a further specific example, whether each chip core has one for indicating its working condition normal
Status register, can carry out self-inspection on the series-fed chip after electricity, and each chip in series-fed chip where indicating
The state of kernel, the state that status register therein is indicated includes following any one or more：Voltage status, temperature shape
State, working frequency state.According to the state that status register is indicated, can know whether the state of chip core is normal, treat
When the state of power supply unit is abnormal, can be alerted.Correspondingly, in the embodiment, adjustment circuit detection series-fed core
When whether the working condition of piece is normal, it is particularly used in and is indicated according to the status register of each chip core in series-fed chip
Condition adjudgement series-fed chip working condition it is whether normal, if any the working state abnormal of chip core, then where
Series-fed chip working state abnormal.
Further, since each unit to be powered will carry out data transmit-receive, can be by unit to be powered whether to being sent to
Whether the data of the unit to be powered have all carried out correct feedback normal to judge the working condition of the unit to be powered.Then exist
In further another specific example, when adjustment circuit detects whether the working condition of unit to be powered is normal, specifically can be with
By a comparator, according to unit to be powered to being sent to the feedback data of the data of the unit to be powered, judge to be powered
Whether the working condition of unit is normal.For example, sending P group data to a unit to be powered, P is the integer more than 1, and detection should
Whether unit to be powered has all carried out correct feedback for the P groups data, if the unit to be powered is all carried out to the P groups data
Correct feedback, then judge that the working condition of the unit to be powered is normal；Otherwise, if the unit to be powered does not all enter to P group data
Row feedback or the feedback error to wherein certain group data, it is possible to determine that the working state abnormal of the unit to be powered.
In a specific example in the above-mentioned each cascade electric power system embodiment of the present invention, adjustment unit is supplied each series connection
When electrical chip carries out voltage adjustment, adjustment unit is specially m, and each adjustment unit is parallel with a series-fed chip respectively
Connection, each adjustment unit specifically can realize that the series-fed chip to connecting carries out voltage by resistance and/or mu balanced circuit
Adjustment.The serial partial pressure of series-fed chip can be preferably embodied as by being connected in parallel adjustment unit to power, wherein, voltage stabilizing electricity
Road for example can be the group of operational amplifier and metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, MOS) pipe
Close.
In the cascade electric power system of various embodiments of the present invention, adjustment circuit specifically can respectively according to each series-fed chip
In unit to be powered working condition, for example, if in normal operating conditions (such as whether can normally transceiving data), voltage
State, state of temperature, working frequency state etc., trip temperature adjustment are entered to each series-fed chip or to list to be powered therein
Line frequency adjustment is entered by unit.Adjustment circuit therein can specifically be realized by hardware, it is also possible to be realized by software.For example, treating
When the working condition of power supply unit is voltage status, state of temperature or working frequency state, when adjustment circuit is realized by hardware,
Can realize that exemplarily, comparator can compare the electricity of series-fed chip unit to be powered by comparator and adjuster
The voltage of pressure value, temperature value, operating frequency value and standard, the magnitude relationship between temperature, the numerical value of working frequency or scope, to
Adjuster output represents comparative result signal, for example, representing that comparative result is identical with 1,0 represents that comparative result is different；Can also
To adjuster output 0 only when comparative result is different, any signal is not exported to adjuster when comparative result is identical；Adjuster
The signal sent according to comparator is heightened or is turned down series-fed chip unit to be powered and enters trip temperature or frequency.For another example, wait to supply
When whether the working condition of electric unit is in normal operating conditions, when adjustment circuit is realized by hardware, can specifically pass through
Watch-dog and adjuster realization, exemplarily, monitor whether unit to be powered is currently in normal operating conditions by watch-dog, to
Adjuster output represents comparative result signal, for example, representing that working condition is normal with 1,0 represents working state abnormal；Also may be used
With it is only abnormal in working order when to adjuster output 0, do not export any signal to adjuster when normal in working order；Adjust
The temperature of series-fed chip is heightened or turned down to section device according to the signal that watch-dog sends, or unit to be powered frequency.
Further, referring back to Fig. 7 and Fig. 8, in the further embodiment of cascade electric power system of the present invention, can also divide
Not Bao Kuo m Auxiliary Power Units, be connected with each series-fed chip respectively, for connect series-fed chip chips
Other units beyond kernel are powered.Exemplarily, boost voltage unit for example can be that common low pressure difference linearity is steady
Power generation circuit and/or the chip such as depressor (Low Drop Out Regular, LDO) and/or DC/DC.Wherein, chip core
Some are special for I/O (input/output) module, PLL (phaselocked loop) module in other units in addition, such as series-fed chip etc.
Different functional module provides power supply, can generally be realized with DC-DC module.
The embodiment of the present invention additionally provides a kind of virtual digit coin and digs ore deposit machine.Fig. 9 is that virtual digit coin of the present invention digs ore deposit machine
The structural representation of one embodiment.As shown in figure 9, the virtual digit coin of the embodiment digs ore deposit machine including cabinet, positioned at cabinet
Internal control panel and the control panel expansion board for connecting and the operation board being connected with expansion board, operation board is comprising in the present invention
State the series-fed chip or cascade electric power system of any embodiment.
Virtual digit coin is dug in ore deposit machine, and control panel is the control centre for entirely digging ore deposit machine, and control panel passes through input/output
(IO) expansion board sends instruction and data, and operation board is powered using power supply circuit, is the arithmetic center for entirely digging ore deposit machine.Control panel
Instruction and data is issued to I/O expansion plate, instruction and data is forwarded to operation board by I/O expansion plate, will knot after operation board computing
Fruit returns to control panel by I/O expansion plate, and control panel is uploaded in internet by wired network interface.In addition, operation board is also
Other units can be included, such as power supply protection circuit, the power supply protection circuit can be in the bulk temperature exception of power supply circuit
When cut-out power supply power supply.
The embodiment of the present invention additionally provides a kind of server.Figure 10 is the structural representation of server one embodiment of the present invention
Figure.As shown in Figure 10, the server of the embodiment includes the ram disk that is electrically connected with mainboard of mainboard and hard disk, is main board power supply
Power supply and CPU, CPU comprising any of the above-described embodiment of the invention series-fed chip or
Person's cascade electric power system.
Each embodiment is described by the way of progressive in this specification, and what each embodiment was stressed is and it
The difference of its embodiment, same or analogous part cross-reference between each embodiment.For system, virtual number
Word coin is dug for ore deposit machine, server example, because it is substantially corresponding with chip embodiment, so fairly simple, the phase of description
Part is closed to be illustrated referring to the part of chip embodiment.
Chip of the invention, system and device may be achieved in many ways.For example, can be by software, hardware, firmware
Or any combinations of software, hardware, firmware realize chip of the invention, system and device.The step of for methods described
Said sequence be not limited to order described in detail above merely to illustrate, the step of the method for the present invention, unless with
Other manner is illustrated.Additionally, in certain embodiments, the present invention can also be implemented or one part is being recorded as record
Program in medium, these programs include the machine readable instructions for realizing the method according to the invention.Thus, the present invention is also
Covering storage is used for the recording medium of the program for performing the method according to the invention.
Description of the invention is given for the sake of example and description, and is not exhaustively or by the present invention
It is limited to disclosed form.Many modifications and variations are for the ordinary skill in the art obvious.Select and retouch
State embodiment and be to more preferably illustrate principle of the invention and practical application, and one of ordinary skill in the art is managed
The solution present invention is suitable to the various embodiments with various modifications of special-purpose so as to design.
Claims (19)
1. a kind of series-fed chip, it is characterised in that the series-fed chip includes the n list to be powered being connected in series
Unit, the n unit to be powered is powered using series system, forms a voltage respectively on each unit to be powered
Domain, the supply voltage of the series-fed chip forms the n grades of voltage domain of series connection, wherein, n is the integer more than 1；It is adjacent to wait to supply
A signal level converting unit is connected in series between electric unit, for being carried out between the unit two neighboring to be powered of connection
The level conversion of signal of communication.
2. chip according to claim 1, it is characterised in that also include n in the series-fed chip and be independently arranged
, deep trap for realizing isolating between different voltage domains, each unit difference position to be powered in the n unit to be powered
In a deep trap.
3. chip according to claim 2, it is characterised in that the deep trap includes N-type deep trap DEEP-NWELL or p-type
Deep trap DEEP-PWELL.
4. the chip according to claims 1 to 3 any one, it is characterised in that each described signal level converting unit
Include high to Low signal level modular converter and low to high signal level modular converter respectively.
5. chip according to claim 4, it is characterised in that each described signal level converting unit is located at respectively
In deep trap；Unit to be powered in each deep trap, respectively by the low to high signal level in the signal level converting unit
Modular converter is connected with the unit to be powered in upper level voltage domain, by the high to Low letter in the signal level converting unit
Number level switch module is connected with the unit to be powered in next stage voltage domain.
6. the chip according to claim 1 to 5 any one, it is characterised in that in each described unit to be powered respectively
Including the chip core that one or more are connected in parallel；Each chip core in each described unit to be powered is treated with place respectively
The signal level converting unit connection of power supply unit connection.
7. chip according to claim 6, it is characterised in that each chip core include respectively one group of computing unit and/
Or memory cell.
8. the chip according to claim 1 to 7 any one, it is characterised in that the signal level converting unit is specific
Using capacitive couplings, differential signal transmission method and or diode drop method realize.
9. a kind of cascade electric power system, it is characterised in that including control device, and be connected in series between feeder ear and ground, m
The individual series-fed chip as described in claim 1 to 8 any one；Form one respectively on each series-fed chip greatly
Voltage domain, the cascade electric power system forms the m grades of big voltage domain of series connection between power supply and ground；Respectively in two neighboring series connection
A chromacoder is connected in series between power supply chip, for level between the two neighboring series-fed chip to connecting
The conversion of signal and differential signal；The control device is connected with each chromacoder respectively, for controlling each signal to change
Device carries out the conversion of level signal and differential signal；
Wherein, every grade big voltage domain includes the n grades of voltage domain of series connection of correspondence series-fed chip, and m is the integer more than 1.
10. a kind of cascade electric power system, it is characterised in that including control device, and be connected in series between feeder ear and ground,
The m series-fed chip as described in claim 1 to 8 any one；One is formed respectively on each series-fed chip
Big voltage domain, the cascade electric power system forms the m grades of big voltage domain of series connection between power supply and ground；Respectively in each series-fed
A chromacoder is connected in series between chip and ground, for level letter between the series-fed chip and ground of realizing connection
Number and differential signal conversion；The control device is connected with each chromacoder respectively, for controlling each signal converting means
Put the conversion for carrying out level signal and differential signal；
Wherein, every grade big voltage domain includes the n grades of voltage domain of series connection of correspondence series-fed chip, and m is the integer more than 1.
11. system according to claim 9 or 10, it is characterised in that also including adjustment circuit, respectively with each series-fed
Chip is connected, and the adjustment of voltage, temperature or frequency is carried out to each series-fed chip.
12. systems according to claim 11, it is characterised in that the adjustment unit enters line frequency to each series-fed chip
When rate is adjusted, specifically for：
Each series-fed chip is directed to respectively, according to the work shape of each unit to be powered in predetermined period detection series-fed chip
Whether state is normal；
If needing the working state abnormal of power supply unit, improve or reduce according to predeterminated frequency step-length in the range of predeterminated frequency
The working frequency of the unit to be powered of working state abnormal.
13. systems according to claim 11, it is characterised in that also set including being respectively m series-fed chip correspondence
The m fan put, each fan is used to be radiated for corresponding series-fed chip；
When the adjustment unit enters trip temperature adjustment to each series-fed chip, specifically for：
Each series-fed chip is directed to respectively, according to the work shape of each unit to be powered in predetermined period detection series-fed chip
Whether state is normal；
If need the working state abnormal of power supply unit, working state abnormal is improved in the range of preset rotation speed or reduced
The rotating speed of the fan of series-fed chip where unit to be powered.
14. system according to claim 12 or 13, it is characterised in that the adjustment unit detects the work of unit to be powered
Make state it is whether normal when, specifically for：
Whether the working condition of the condition adjudgement unit to be powered that the status register according to unit to be powered is indicated is normal, described
The state that status register is indicated includes following any one or more：Voltage status, state of temperature, working frequency state；Or
Person, to being sent to the feedback data of the data of the unit to be powered, judges the working condition of unit to be powered according to unit to be powered
It is whether normal.
15. systems according to claim 11, it is characterised in that the adjustment unit carries out electricity to each series-fed chip
During pressure adjustment, the adjustment unit is specially m, and each adjustment unit is connected in parallel with a series-fed chip respectively；
The adjustment unit includes resistance or mu balanced circuit.
16. system according to claim 9 to 15 any one, it is characterised in that also including m Auxiliary Power Units,
Each Auxiliary Power Units is connected with a series-fed chip respectively, beyond to series-fed chip chips kernel
Other units are powered.
17. system according to claim 9 to 16 any one, it is characterised in that the chromacoder is specifically adopted
Realized with capacitive couplings, optocoupler transformation approach, transformer transformation approach, differential signal transmission method and or diode drop method.
A kind of 18. virtual digit coin dig ore deposit machine, it is characterised in that including cabinet, control panel and control panel positioned at cabinet inside
The expansion board of connection and the operation board being connected with expansion board, the operation board include claim 1 to 8 any claim institute
The cascade electric power system described in series-fed chip or claim 9 to 17 any claim stated.
19. a kind of servers, it is characterised in that the ram disk and hard disk that are electrically connected with mainboard including mainboard, be main board power supply
Power supply and CPU, the CPU include the series connection described in claim 1 to 8 any claim
Cascade electric power system described in power supply chip or claim 9 to 17 any claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611169618.6A CN106774767A (en) | 2016-12-16 | 2016-12-16 | Series-fed chip and system, virtual digit coin dig ore deposit machine and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611169618.6A CN106774767A (en) | 2016-12-16 | 2016-12-16 | Series-fed chip and system, virtual digit coin dig ore deposit machine and server |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106774767A true CN106774767A (en) | 2017-05-31 |
Family
ID=58892322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611169618.6A Pending CN106774767A (en) | 2016-12-16 | 2016-12-16 | Series-fed chip and system, virtual digit coin dig ore deposit machine and server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106774767A (en) |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107145208A (en) * | 2017-06-20 | 2017-09-08 | 算丰科技（北京）有限公司 | Plural serial stage power supply circuit, method, device, digging ore deposit machine and server |
| CN107621865A (en) * | 2017-09-20 | 2018-01-23 | 北京比特大陆科技有限公司 | Series-fed circuit and its powering method, dig ore deposit machine, server, equipment |
| CN108040418A (en) * | 2017-12-05 | 2018-05-15 | 深圳比特微电子科技有限公司 | Data processing equipment and ideal money dig ore deposit machine and computer server |
| CN108415320A (en) * | 2018-02-13 | 2018-08-17 | 深圳比特微电子科技有限公司 | Power supply circuit, circuit board and virtual digit coin dig mine machine |
| CN108446004A (en) * | 2018-03-21 | 2018-08-24 | 北京比特大陆科技有限公司 | Circuit device, electronic equipment dig mine machine and server |
| CN108459934A (en) * | 2017-12-22 | 2018-08-28 | 深圳比特微电子科技有限公司 | The method for searching optimum frequency |
| CN108693934A (en) * | 2018-06-28 | 2018-10-23 | 北京比特大陆科技有限公司 | A kind of digital cash digs mine machine and digital cash digs mine system |
| CN108923778A (en) * | 2018-06-22 | 2018-11-30 | 比飞力（深圳）科技有限公司 | A kind of logic level converting circuit and integrated circuit |
| CN109104179A (en) * | 2018-06-22 | 2018-12-28 | 比飞力（深圳）科技有限公司 | A kind of integrated circuit and electronic equipment |
| CN109874315A (en) * | 2017-12-21 | 2019-06-11 | 北京比特大陆科技有限公司 | Series-fed circuit, system and method |
| CN110308781A (en) * | 2019-03-26 | 2019-10-08 | 深圳大锄科技有限公司 | One kind can tolerance high power density series-fed devices and methods therefor |
| CN110333766A (en) * | 2019-04-26 | 2019-10-15 | 深圳市致宸信息科技有限公司 | It is a kind of that method and devices that calculating power plate are controlled based on single channel power supply more |
| WO2019233206A1 (en) * | 2018-06-06 | 2019-12-12 | 北京嘉楠捷思信息技术有限公司 | Chip frequency modulation method and apparatus of computing device, computing board, computing device and storage medium |
| WO2020057180A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | On-chip passive power supply compensation circuit and operational unit applying same, and chip, hashboard and computing device |
| CN111007300A (en) * | 2019-12-26 | 2020-04-14 | 深圳杰微芯片科技有限公司 | Method and device for detecting voltage of series circuit and storage medium |
| WO2020107175A1 (en) * | 2018-11-26 | 2020-06-04 | 北京比特大陆科技有限公司 | Frequency processing method, device and apparatus, and storage medium |
| CN111274069A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Data processing method and device |
| CN111309353A (en) * | 2020-01-20 | 2020-06-19 | 山东超越数控电子股份有限公司 | Method and device for updating FPGA (field programmable Gate array) firmware of operation board based on server control board |
| CN111859829A (en) * | 2019-04-04 | 2020-10-30 | 北京比特大陆科技有限公司 | Method, apparatus and device for controlling force calculation board, medium and program product |
| CN111856245A (en) * | 2020-07-13 | 2020-10-30 | 上海聪链信息科技有限公司 | Dynamic frequency conversion method and system for block chain server chip |
| CN112256115A (en) * | 2020-09-21 | 2021-01-22 | 北京比特大陆科技有限公司 | Power supply circuit, chip and electronic equipment |
| US11016554B2 (en) | 2019-01-08 | 2021-05-25 | Digwise Technology Corporation, Ltd | Semiconductor apparatus |
| CN113346468A (en) * | 2020-03-02 | 2021-09-03 | 蜜蜂计算(香港)股份有限公司 | Multistage series circuit power supply device and mining machine thereof |
| CN114546086A (en) * | 2020-11-25 | 2022-05-27 | 北京比特大陆科技有限公司 | Chip, series power supply circuit, data processing equipment and computer server |
| CN114546089A (en) * | 2020-11-25 | 2022-05-27 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic equipment |
| CN112805657B (en) * | 2018-11-26 | 2024-04-30 | 北京比特大陆科技有限公司 | Frequency processing method, device, equipment and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102722605A (en) * | 2012-05-22 | 2012-10-10 | 上海宏力半导体制造有限公司 | Circuit verification method and semiconductor device simulation method |
| CN103546144A (en) * | 2013-10-31 | 2014-01-29 | 矽力杰半导体技术(杭州)有限公司 | High-voltage side circuit with multiple voltage domains, semiconductor structure and level shifting circuit |
| CN104242912A (en) * | 2013-06-13 | 2014-12-24 | 阿尔特拉公司 | multiple-voltage programmable logic fabric |
| CN104242909A (en) * | 2014-10-22 | 2014-12-24 | 上海芯导电子科技有限公司 | Level conversion circuit |
| CN105045364A (en) * | 2015-07-21 | 2015-11-11 | 北京比特大陆科技有限公司 | Serial power supply circuit, virtual digital coin mining machine and computer server |
| CN106383566A (en) * | 2016-10-21 | 2017-02-08 | 算丰科技（北京）有限公司 | Power supply circuit |
| CN206523836U (en) * | 2016-12-16 | 2017-09-26 | 算丰科技（北京）有限公司 | Series-fed chip and system |
-
2016
- 2016-12-16 CN CN201611169618.6A patent/CN106774767A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102722605A (en) * | 2012-05-22 | 2012-10-10 | 上海宏力半导体制造有限公司 | Circuit verification method and semiconductor device simulation method |
| CN104242912A (en) * | 2013-06-13 | 2014-12-24 | 阿尔特拉公司 | multiple-voltage programmable logic fabric |
| CN103546144A (en) * | 2013-10-31 | 2014-01-29 | 矽力杰半导体技术(杭州)有限公司 | High-voltage side circuit with multiple voltage domains, semiconductor structure and level shifting circuit |
| CN104242909A (en) * | 2014-10-22 | 2014-12-24 | 上海芯导电子科技有限公司 | Level conversion circuit |
| CN105045364A (en) * | 2015-07-21 | 2015-11-11 | 北京比特大陆科技有限公司 | Serial power supply circuit, virtual digital coin mining machine and computer server |
| CN106383566A (en) * | 2016-10-21 | 2017-02-08 | 算丰科技（北京）有限公司 | Power supply circuit |
| CN206523836U (en) * | 2016-12-16 | 2017-09-26 | 算丰科技（北京）有限公司 | Series-fed chip and system |
Cited By (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107145208A (en) * | 2017-06-20 | 2017-09-08 | 算丰科技（北京）有限公司 | Plural serial stage power supply circuit, method, device, digging ore deposit machine and server |
| CN107621865A (en) * | 2017-09-20 | 2018-01-23 | 北京比特大陆科技有限公司 | Series-fed circuit and its powering method, dig ore deposit machine, server, equipment |
| CN107621865B (en) * | 2017-09-20 | 2020-12-11 | 北京比特大陆科技有限公司 | Series power supply circuit and electrifying method, mining machine, server and equipment thereof |
| CN108040418A (en) * | 2017-12-05 | 2018-05-15 | 深圳比特微电子科技有限公司 | Data processing equipment and ideal money dig ore deposit machine and computer server |
| CN109874315A (en) * | 2017-12-21 | 2019-06-11 | 北京比特大陆科技有限公司 | Series-fed circuit, system and method |
| CN108459934A (en) * | 2017-12-22 | 2018-08-28 | 深圳比特微电子科技有限公司 | The method for searching optimum frequency |
| CN108459934B (en) * | 2017-12-22 | 2021-01-29 | 深圳比特微电子科技有限公司 | Method for searching optimum frequency |
| CN108415320A (en) * | 2018-02-13 | 2018-08-17 | 深圳比特微电子科技有限公司 | Power supply circuit, circuit board and virtual digit coin dig mine machine |
| CN108415320B (en) * | 2018-02-13 | 2021-06-29 | 深圳比特微电子科技有限公司 | Power supply circuit, circuit board and virtual digital coin ore digging machine |
| CN108446004A (en) * | 2018-03-21 | 2018-08-24 | 北京比特大陆科技有限公司 | Circuit device, electronic equipment dig mine machine and server |
| WO2019233206A1 (en) * | 2018-06-06 | 2019-12-12 | 北京嘉楠捷思信息技术有限公司 | Chip frequency modulation method and apparatus of computing device, computing board, computing device and storage medium |
| US11502693B2 (en) | 2018-06-06 | 2022-11-15 | Canaan Creative Co., Ltd. | Chip frequency modulation method and apparatus of computing device, hash board, computing device and storage medium |
| CN109104179A (en) * | 2018-06-22 | 2018-12-28 | 比飞力（深圳）科技有限公司 | A kind of integrated circuit and electronic equipment |
| CN108923778A (en) * | 2018-06-22 | 2018-11-30 | 比飞力（深圳）科技有限公司 | A kind of logic level converting circuit and integrated circuit |
| CN108693934A (en) * | 2018-06-28 | 2018-10-23 | 北京比特大陆科技有限公司 | A kind of digital cash digs mine machine and digital cash digs mine system |
| WO2020057180A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | On-chip passive power supply compensation circuit and operational unit applying same, and chip, hashboard and computing device |
| US11442517B2 (en) | 2018-09-20 | 2022-09-13 | Canaan Creative Co., Ltd. | On-chip passive power supply compensation circuit and operation unit, chip, hash board and computing device using same |
| WO2020107175A1 (en) * | 2018-11-26 | 2020-06-04 | 北京比特大陆科技有限公司 | Frequency processing method, device and apparatus, and storage medium |
| CN112805657B (en) * | 2018-11-26 | 2024-04-30 | 北京比特大陆科技有限公司 | Frequency processing method, device, equipment and storage medium |
| CN112805657A (en) * | 2018-11-26 | 2021-05-14 | 北京比特大陆科技有限公司 | Frequency processing method, device, equipment and storage medium |
| CN111274069A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Data processing method and device |
| CN111274069B (en) * | 2018-12-05 | 2023-07-07 | 锐迪科（重庆）微电子科技有限公司 | Data processing method and device |
| US11016554B2 (en) | 2019-01-08 | 2021-05-25 | Digwise Technology Corporation, Ltd | Semiconductor apparatus |
| CN110308781A (en) * | 2019-03-26 | 2019-10-08 | 深圳大锄科技有限公司 | One kind can tolerance high power density series-fed devices and methods therefor |
| CN111859829A (en) * | 2019-04-04 | 2020-10-30 | 北京比特大陆科技有限公司 | Method, apparatus and device for controlling force calculation board, medium and program product |
| CN111859829B (en) * | 2019-04-04 | 2024-04-16 | 北京比特大陆科技有限公司 | Method, apparatus and device for controlling a computing pad, and medium and program product |
| CN110333766B (en) * | 2019-04-26 | 2020-12-08 | 深圳市致宸信息科技有限公司 | Method and device for controlling multi-computing-force board based on single-path power supply |
| CN110333766A (en) * | 2019-04-26 | 2019-10-15 | 深圳市致宸信息科技有限公司 | It is a kind of that method and devices that calculating power plate are controlled based on single channel power supply more |
| CN111007300A (en) * | 2019-12-26 | 2020-04-14 | 深圳杰微芯片科技有限公司 | Method and device for detecting voltage of series circuit and storage medium |
| CN111309353A (en) * | 2020-01-20 | 2020-06-19 | 山东超越数控电子股份有限公司 | Method and device for updating FPGA (field programmable Gate array) firmware of operation board based on server control board |
| CN111309353B (en) * | 2020-01-20 | 2023-05-23 | 超越科技股份有限公司 | Method and equipment for updating operation board FPGA firmware based on server control board |
| CN113346468A (en) * | 2020-03-02 | 2021-09-03 | 蜜蜂计算(香港)股份有限公司 | Multistage series circuit power supply device and mining machine thereof |
| CN111856245A (en) * | 2020-07-13 | 2020-10-30 | 上海聪链信息科技有限公司 | Dynamic frequency conversion method and system for block chain server chip |
| CN112256115A (en) * | 2020-09-21 | 2021-01-22 | 北京比特大陆科技有限公司 | Power supply circuit, chip and electronic equipment |
| WO2022057956A1 (en) * | 2020-09-21 | 2022-03-24 | 北京比特大陆科技有限公司 | Power supply circuit, chip, and electronic device |
| WO2022111361A1 (en) * | 2020-11-25 | 2022-06-02 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic device |
| WO2022111359A1 (en) * | 2020-11-25 | 2022-06-02 | 北京比特大陆科技有限公司 | Chip, series power supply circuit, data processing device, and computer server |
| CN114546089A (en) * | 2020-11-25 | 2022-05-27 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic equipment |
| CN114546089B (en) * | 2020-11-25 | 2023-11-28 | 北京比特大陆科技有限公司 | Chip power supply circuit and electronic equipment |
| CN114546086A (en) * | 2020-11-25 | 2022-05-27 | 北京比特大陆科技有限公司 | Chip, series power supply circuit, data processing equipment and computer server |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106774767A (en) | Series-fed chip and system, virtual digit coin dig ore deposit machine and server | |
| CN206523836U (en) | Series-fed chip and system | |
| CN106383566A (en) | Power supply circuit | |
| US10824219B2 (en) | Hard disk peak-staggering starting system | |
| CN101446856B (en) | Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor | |
| CN207518573U (en) | Reconfigurable transmitter | |
| CN102998982B (en) | Power control circuit, the semiconductor devices including it | |
| CN106249834A (en) | Power supply circuits, virtual digit coin dig ore deposit machine and computer server | |
| CN204810255U (en) | Clock recovery framework is permitd to incline and system thereof | |
| CN107463456A (en) | A kind of system and method for lifting double netcard NCSI management system switching efficiencies | |
| TWI550392B (en) | Power management for an electronic device | |
| CN103227648A (en) | Ground referenced single-ended signaling | |
| CN107947305A (en) | A kind of wireless charging circuit, system, method and terminal device | |
| CN103227621A (en) | Data-driven charge-pump transmitter for differential signaling | |
| CN106201758B (en) | A kind of method and device that server node hard disk powers on | |
| CN108446004A (en) | Circuit device, electronic equipment dig mine machine and server | |
| CN107621865A (en) | Series-fed circuit and its powering method, dig ore deposit machine, server, equipment | |
| Liu et al. | A 0.1 pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI | |
| CN206039425U (en) | Supply circuit , virtual digital coin dig ore deposit machine and computer server | |
| CN109756223A (en) | Interface circuit and interface arrangement | |
| CN108233699A (en) | A kind of power management chip, electric power system and electronic equipment | |
| CN205121469U (en) | Series connection supply circuit , virtual digital coin dig ore deposit machine and computer server | |
| CN104168012B (en) | Voltage level shifter and its system of realization | |
| CN206515778U (en) | Power supply circuit | |
| CN106326174A (en) | Two-wire communication circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20170921 Address after: 100029 Beijing, Haidian District North Austrian industrial base project, building 2, floor 6 Applicant after: BEIJING BITMAIN TECHNOLOGY CO., LTD. Address before: 100029 Beijing city Haidian District Baosheng Road No. 1 Building No. 25 hospital three Applicant before: Feng Feng Technology (Beijing) Co., Ltd. |
|
| TA01 | Transfer of patent application right |