CN112805657A - Frequency processing method, device, equipment and storage medium - Google Patents
Frequency processing method, device, equipment and storage medium Download PDFInfo
- Publication number
- CN112805657A CN112805657A CN201880098349.XA CN201880098349A CN112805657A CN 112805657 A CN112805657 A CN 112805657A CN 201880098349 A CN201880098349 A CN 201880098349A CN 112805657 A CN112805657 A CN 112805657A
- Authority
- CN
- China
- Prior art keywords
- chip
- frequency
- chips
- determining
- voltage domain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000004364 calculation method Methods 0.000 claims description 53
- 238000012545 processing Methods 0.000 claims description 26
- 238000004590 computer program Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000010408 sweeping Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
A frequency processing method, apparatus, device and storage medium, the method is suitable for a series circuit, the said series circuit includes more than two chip sets connected in parallel each other, each chip set includes more than two chips connected in series sequentially, the method includes confirming the frequency combination (101); adjusting a combination of operating frequencies of chips in the same voltage domain in the series circuit to the frequency combination (102). The method can improve the overall computational power of the chips in the series circuit.
Description
The present application relates to the field of computer technologies, and for example, to a frequency processing method, apparatus, device, and storage medium.
In practical applications, the chips on the whole serial circuit need to work at the same working frequency to keep the balance of the voltage domains on the chips of each group. In addition, when frequency sweeping operation is performed, a working frequency can be set first, all chips can work under the frequency, when more than three chips can not work at the frequency, the frequency needs to be reduced again, frequency sweeping is started again, and frequency sweeping is only calculated to pass when the number of chips which do not meet the frequency is less than three.
However, in the conventional frequency sweeping method, all chips (regardless of their constitutions) must be moved to the worst-case chip, that is, the worst-case chip operates at a frequency that can be borne by the worst-case chip, which results in a waste of processing capability of the better-case chip and also reduces a calculation value of the whole series circuit.
The above background is only for the purpose of aiding understanding of the present application and does not constitute an admission or admission that any of the matter referred to is part of the common general knowledge relative to the present application.
Disclosure of Invention
The embodiment of the application provides a frequency processing method, a frequency processing device, frequency processing equipment and a storage medium, which are used for improving the overall computational power of chips in a series circuit.
A first aspect of an embodiment of the present application provides a frequency processing method, where the method is applicable to a serial circuit, where the serial circuit includes more than two chip sets connected in parallel, and each chip set includes more than two chips connected in series in sequence, and the frequency processing method includes:
determining a frequency combination; and adjusting the working frequency combination of the chips in the same voltage domain in the series circuit into the frequency combination.
A second aspect of the embodiments of the present application provides a frequency processing apparatus, which is suitable for a serial circuit, where the serial circuit includes more than two chip sets connected in parallel with each other, and each chip set includes more than two chips connected in series in sequence, and the apparatus includes: a processor and a memory, the memory having instructions stored therein, which when executed by the processor, perform the method of:
determining a frequency combination; and adjusting the working frequency combination of the chips in the same voltage domain in the series circuit into the frequency combination.
A third aspect of the embodiments of the present application provides a computer device, which includes a series circuit, and the frequency processing apparatus according to the second aspect; the series circuit comprises more than two chip groups which are connected in parallel, each chip group comprises more than two chips which are connected in series in sequence, and the frequency processing device is used for adjusting the working frequency of the chips on the series circuit.
An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions configured to perform the method of the first aspect.
Embodiments of the present application further provide a computer program product comprising a computer program stored on a computer-readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method of the first aspect described above.
One or more embodiments are illustrated in the accompanying drawings, which correspond to the accompanying drawings, and which do not constitute a limitation on the embodiments, in which elements having the same reference numeral designations represent like elements, and in which:
FIG. 1 is a schematic diagram of a series circuit suitable for use with embodiments of the present application;
fig. 2 is a schematic view of an application scenario provided in an embodiment of the present application;
fig. 3 is a flowchart of a frequency processing method according to an embodiment of the present application;
fig. 4 is a flowchart of a method for determining a frequency combination according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a frequency processing apparatus according to an embodiment of the present application.
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
For the sake of convenience, the following terms are explained in relation to the embodiments of the present application:
chip constitution: in the embodiment of the present application, the chip physical quality is used to describe the processing capability of the chip, and the stronger the processing capability of the chip, the better the physical quality of the chip, and conversely, the worse the physical quality of the chip.
Constitution grade: in the embodiment of the application, the strength of the processing capacity of the chip is described by the body constitution grade.
Calculating a force value: in the embodiment of the present application, the computation value refers to a value for describing the processing capability of the chip.
Fig. 1 is a schematic diagram of a serial circuit suitable for use in an embodiment of the present application, where the serial circuit includes more than two chip sets connected in parallel, and each chip set includes more than two chips connected in series in sequence. As shown in fig. 1, in practical applications, in order to ensure that voltage domains of each chip set on the serial circuit are balanced, it is necessary to make the chips on the whole serial circuit all operate at the operating frequency of the chip with the worst physical quality, however, the physical quality of the chips is good or bad, if the chips on the whole serial circuit all operate at the operating frequency of the chip with the worst physical quality, the performance of the chips with good physical qualities is greatly limited, which causes great waste to the performance of the chips, and also affects the operating performance of the corresponding electronic devices.
In view of the above problems in the prior art, embodiments of the present application provide a frequency processing scheme, in which different chips in the same voltage domain operate at a set frequency combination to obtain an overall optimal performance, and since the operating frequency combinations of the chips in each voltage domain on the serial circuit are all the same frequency combination, the balance of the voltage domains on the serial circuit can be ensured. For example, fig. 2 is a schematic diagram of an application scenario provided by an embodiment of the present application, as shown in fig. 2, in fig. 2, each voltage domain of the series circuit may include 3 chips, and each of the chips in each voltage domain may operate at a frequency combination (500M, 600M, 700M), for example, 3 chips in a first voltage domain may operate at 500M, 600M, 700M, respectively, 3 chips in a second voltage domain may operate at 600M, 500M, 700M, respectively, 3 chips in a third voltage domain may operate at 700M, 500M, 600M, respectively, and so on, thus, the balance of each voltage domain can be ensured, each chip can also exert better performance, therefore, the chip with better quality in the series circuit cannot be tired by the chip with poorer quality, and the utilization efficiency of the chip in the series circuit is improved.
The technical solution of the present application is set forth in detail below with reference to exemplary embodiments.
Fig. 3 is a flowchart of a frequency processing method according to an embodiment of the present application. The method is suitable for a series circuit which comprises more than two chip groups which are mutually connected in parallel, wherein each chip group comprises more than two chips which are sequentially connected in series. The method may be performed by a frequency processing device, which may be, but is not limited to, a corresponding processor or controller. As shown in fig. 3, the method includes:
The number of frequencies in the frequency combination may be generally equal to the number of chips in each voltage domain of the series circuit, for example, if 3 chips are included in one voltage domain of the series circuit, the number of frequencies in the frequency combination may be 3. Of course, the categories of the 3 frequencies in the frequency combination (specifically, the frequencies with different values are a category) may be different from each other or partially the same, for example, the frequencies in the frequency combination may be 500M, 600M, and 700M, respectively, or may be 500M, 700M, or 600M, and 700M, respectively.
That is to say, in this embodiment, when the specific values of some frequencies in the frequency combination are the same, it can be characterized that multiple chips in the same voltage domain may operate at the same frequency, for example, the number of frequencies in the frequency combination is 5, and the specific values of the frequencies are 100M, 200M, 300M, 500M, and 500M, so that it can be determined that two chips in the same voltage domain need to operate at 500M. However, in order to optimize the performance of the whole voltage domain or the whole series circuit, the specific values of the frequencies in the frequency combinations preferably set in this embodiment are different from each other, so that chips with different physical constitutions in the same voltage domain can operate at different frequencies, so as to exert the individual advantages of the chips as much as possible.
Further, in a feasible design, the present embodiment may also preset the frequency combination according to needs, for example, in a possible scenario, a person skilled in the art may set the frequency combination in the present embodiment by comprehensively considering the power consumption and the performance according to a specific application scenario of the series circuit.
In another possible design, the calculation values of all chips in the series circuit are calculated, and the calculation values of the chips are comprehensively considered to obtain a frequency combination which can stabilize the voltage domain of the series circuit and optimize the performance.
And 102, adjusting the working frequency combination of the chips in the same voltage domain in the series circuit into the frequency combination.
For example, assuming that 3 chips are included in each voltage domain of the series circuit, the operating frequencies of the chips in each voltage domain may be adjusted such that the combinations of the operating frequencies of the chips in each voltage domain are (700M, 800M, 900M), for example, 3 chips in the first voltage domain may operate at 700M, 800M, 900M, respectively, 3 chips in the second voltage domain may operate at 800M, 700M, 900M, respectively, 3 chips in the third voltage domain may operate at 900M, 800M, 700M, respectively, and so on.
The foregoing is, of course, illustrative only and is not intended to be the only limitation on the scope of the application.
In this embodiment, by determining the frequency combination and adjusting the working frequency combination of each chip in the same voltage domain in the series circuit to the frequency combination, different chips in the same voltage domain can work on the set frequency combination, and because the working frequency combinations of the chips in each voltage domain on the series circuit are all the same frequency combination, the processing capability of each chip in the series circuit can be released on the premise of ensuring the voltage domain balance of the series circuit, so that the overall performance of the series circuit is improved.
The above technical solution is further expanded and optimized by combining specific embodiments.
Fig. 4 is a flowchart of a method for determining a frequency combination according to an embodiment of the present application, and as shown in fig. 4, on the basis of the embodiment of fig. 3, step 101 may include the following steps:
And step 203, combining the optimal working frequencies of the chips with different physique grades into the frequency combination.
In one possible embodiment, the optimal operating frequency may be an operating frequency that can maximize the overall computational power of the chips with the same physical quality level in each voltage domain, and thus maximize the computational power of the entire voltage domain.
Further, determining the quality class of each chip in each voltage domain may include:
adjusting the stepping according to a preset frequency to enable each chip in the series circuit to work at different working frequencies in sequence;
determining the calculation force value of each chip on each working frequency;
determining the longitudinal force calculation sum of each chip on each working frequency based on the force calculation value; the longitudinal force calculation sum is the sum of force calculation values of the same chip on different working frequencies;
and determining the physique grade of each chip in each voltage domain based on the longitudinal force calculation sum.
For example, the operating frequency of the chip may be gradually decreased from a higher value to a lower value, such as from 800M to 500M, and the frequency adjustment steps may be decreased one at a time; of course, the operating frequency of the chip may be increased from a lower value to a higher value, such as from 400M to 900M, and the frequency adjustment step may be decreased one time, which is not limited in any way.
The frequency adjustment step can be flexibly set according to actual conditions, for example, set to be 20M, 25M, 10M, etc., as long as the actual requirements can be met, and no limitation is made to this.
In some possible embodiments, the calculation power in the vertical direction and the physical quality rating of the larger chip are higher, and the calculation power in the vertical direction and the physical quality rating of the smaller chip are lower, for example, if the calculation power in the vertical direction of the two chips is 125030000 and 250000000 respectively, the calculation power in the vertical direction and the physical quality rating of the chip 250000000 can be determined to be higher, which is not described in detail herein.
Further, the determining the calculation force value of each chip at each operating frequency may include:
determining the number of the chips on any working frequency aiming at any chip;
and taking the product of the working frequency and the echo number as a calculation force value of the chip under the working frequency.
It should be noted that the reply number may be a nonce, i.e. a random number, and may be a nonce received by the chip. Of course, in some possible embodiments, the number of replies may also be a reply rate, i.e. nonce/total nonce that should be received, without any limitation,
furthermore, it should be noted that, in some possible embodiments, the reply number may be a message sent to the chip by a corresponding controller or processor, such as a controller or processor on a control board in the electronic device, and the details thereof are not described herein.
Further, the determining the optimal operating frequency of each chip with the same quality class in each voltage domain includes:
determining the transverse force sum of each chip of any constitution grade in any voltage domain under each working frequency; wherein, the transverse calculation force sum is the sum of calculation force values of all chips of the physique grades in the voltage domain under all working frequencies;
and determining the maximum lateral computing force and the corresponding working frequency as the optimal working frequency of the chips of the physique grades in the voltage domain.
In the following, a detailed description is given of the frequency processing method provided in the present application, by way of a specific example:
for example, assuming a series circuit comprising 84 chips, 28 voltage domains, each comprising 3 chips, the frequency combination can be determined by: a fixed frequency adjustment step, such as 25M, is first determined. Then all chips in the whole series circuit can be operated at the frequency of 700M, the product of the number of nonces received by each chip and the operating frequency (i.e. 700M) is used as the calculation value of the chip at the operating frequency, then 675M, 650M, 625M, 600M, … … are tested, and the frequency adjustment step is decreased by one step each time until the number of nonces received by all chips in the series circuit at a certain operating frequency is greater than 99.5% of the total number of nonces that should be received, for example, after the frequency is less than 600M, the number of nonces received by all chips is greater than 99.5% of the total number of nonces that should be received, and then 600M can be tested because the frequency is changed from high to low and the recovery number is changed from low to high in the whole test process, and when the recovery number is high to a certain degree, it is shown that the frequency is stable enough and no longer needs to adjust the frequency down. For clarity, the following description is given by taking the calculation values of 12 chips (as asic1-asic12 in table one) as an example:
watch 1
The table is a calculation power value table of 12 chips obtained based on the method, wherein the chips asic1-asic3 belong to the same voltage domain, the chips asic4-asic6 belong to the same voltage domain, the chips asic7-asic9 belong to the same voltage domain, and the chips asic10-asic12 belong to the same voltage domain. In table one, the data in each table under the chip number is the product of the nonce received by the chip and the corresponding operating frequency, i.e. the calculation value of the chip under the current operating frequency. The sum of the longitudinal force calculations in the table is the sum of the force calculations of a certain chip at different frequencies, and the quality of the 3 chips in the voltage domain can be obtained by comparing the sum of the longitudinal force calculations of the 3 chips in the same voltage domain, for example, it can be determined from table one that the quality of the chip in the voltage domain composed of the chips asic1-asic3 can be respectively low-level (hereinafter referred to as "3"), high-level (hereinafter referred to as "1") and middle-level (hereinafter referred to as "2"), which is not described herein again.
Then, by sorting the quality classes of the chips in each voltage domain, the quality classes of all the chips in a series circuit can be obtained, as shown in table two.
In table two, the physical grades of the chips in each voltage domain can be represented by numbers 1, 2 and 3, wherein "1" represents the highest physical grade of the chip, and "3" represents the lowest physical grade of the chip.
All columns with constitution grade "1" are moved to a new table to form table three, all columns with constitution grade "2" are moved to a new table to form table four, and all columns with constitution grade "3" are moved to a new table to form table five.
Watch two
Watch III
Watch four
Watch five
In table three, table four and table five, the transverse calculated force and the sum of the calculated force values of the chips with the same physical quality grade under the same frequency are represented, for the chip with the same physical quality grade, the transverse calculated force and the maximum corresponding working frequency are the optimal working frequency (also called the comprehensive optimal frequency) of the chip with the physical quality grade, and as can be known from table three, the transverse calculated force and the maximum working frequency of the chip with the physical quality grade No. 1 are obtained when the working frequency is 675M, so that the optimal working frequency of the chip with the physical quality grade No. 1 is 675M; as can be seen from table four, the chip with "2" quality class has the highest horizontal calculation power when the operating frequency is 650M, so the optimal operating frequency of the chip with "2" quality class is 655M; as can be seen from table five, the chip with "3" quality class has the highest lateral computational power sum when the operating frequency is 625M, and therefore the optimum operating frequency of the chip with "3" quality class is 625M.
As can be seen from the above, the finally determined frequency combinations may be 675M, 650M, and 625M. That is, the operating frequency of the chip with physical quality class "1" in each voltage domain may be set to 675M, the operating frequency of the chip with physical quality class "2" in each voltage domain may be set to 650M, and the operating frequency of the chip with physical quality class "3" in each voltage domain may be set to 625M, so as to ensure that the chips with different physical quality classes can operate at their own preferred operating frequencies.
The foregoing is, of course, by way of example only and is not intended as a sole limitation of this application.
In this embodiment, the quality classes of the chips in the voltage domains are determined, the optimal operating frequencies of the chips with the same quality class in the voltage domains are determined, and the optimal operating frequencies of the chips with different quality classes are combined into a frequency combination suitable for the voltage domains, so that the processing capability of the chips with the quality classes can be released, and the processing capability of the whole series circuit can be improved.
Fig. 5 is a schematic structural diagram of a frequency processing apparatus according to an embodiment of the present application. Specifically, the frequency processing apparatus 50 shown in fig. 5 is applied to a series circuit including two or more chip sets connected in parallel with each other, each chip set including two or more chips connected in series in sequence, and the frequency processing apparatus 50 includes: a processor 51 and a memory 52, said memory 52 having stored therein instructions that, when executed by said processor 51, perform the method of:
determining a frequency combination;
and adjusting the working frequency combination of the chips in the same voltage domain in the series circuit into the frequency combination.
In one possible design, the processor 51 may specifically determine the frequency combination by:
determining the physique grade of each chip in each voltage domain;
determining the optimal working frequency of each chip with the same constitution grade in each voltage domain;
and combining the optimal working frequencies of the chips with different physique grades into the frequency combination.
In one possible design, the processor 51 may specifically determine the physical quality level of each chip in each voltage domain by:
adjusting the stepping according to a preset frequency to enable each chip in the series circuit to work at different working frequencies in sequence;
determining the calculation force value of each chip on each working frequency;
determining the longitudinal force calculation sum of each chip on each working frequency based on the force calculation value; the longitudinal force calculation sum is the sum of force calculation values of the same chip on different working frequencies;
and determining the physique grade of each chip in each voltage domain based on the longitudinal force calculation sum.
In one possible design, the processor 51 may specifically determine the computation value of each chip at each operating frequency by:
determining the number of the chips on any working frequency aiming at any chip;
and taking the product of the working frequency and the echo number as a calculation force value of the chip under the working frequency.
In one possible design, the processor 51 may specifically determine the optimal operating frequency of each chip with the same quality class in each voltage domain by:
determining the transverse force sum of each chip of any constitution grade in any voltage domain under each working frequency; wherein, the transverse calculation force sum is the sum of calculation force values of all chips of the physique grades in the voltage domain under all working frequencies;
and determining the maximum lateral computing force and the corresponding working frequency as the optimal working frequency of the chips of the physique grades in the voltage domain.
The apparatus of this embodiment can be used to execute the method of any of the above embodiments, and the execution manner and the beneficial effects are similar, which are not described herein again.
The embodiment of the application also provides computer equipment, wherein the computer equipment comprises a series circuit and the frequency processing device in the embodiment; the series circuit comprises more than two chip groups which are connected in parallel, each chip group comprises more than two chips which are connected in series in sequence, and the frequency processing device is used for adjusting the working frequency of the chips on the series circuit.
In some possible embodiments, the computer device may be any electronic device capable of implementing data processing, such as an AI supercomputing device, a digital voucher processing device, and the like.
Furthermore, it should be noted that the series circuit may be disposed on a corresponding circuit board, such as a substrate of a motherboard or a substrate of an operation board, and the chips in the series circuit may be connected to a controller on a control board in a computer device for communication, so as to realize transmission of control signals.
Embodiments of the present application further provide a computer-readable storage medium storing computer-executable instructions configured to execute the frequency processing method.
An embodiment of the present application further provides a computer program product, which includes a computer program stored on a computer-readable storage medium, the computer program including program instructions, which, when executed by a computer, cause the computer to execute the above frequency processing method.
The computer-readable storage medium described above may be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium.
The technical solution of the embodiment of the present application may be embodied in the form of a software product, where the computer software product is stored in a storage medium and includes one or more instructions to enable a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiment of the present application. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes, and may also be a transient storage medium.
As used in this application, although the terms "first," "second," etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, unless the meaning of the description changes, so long as all occurrences of the "first element" are renamed consistently and all occurrences of the "second element" are renamed consistently. The first and second elements are both elements, but may not be the same element.
The words used in this application are words of description only and not of limitation of the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The various aspects, implementations, or features of the described embodiments can be used alone or in any combination. Aspects of the described embodiments may be implemented by software, hardware, or a combination of software and hardware. The described embodiments may also be embodied by a computer-readable medium having computer-readable code stored thereon, the computer-readable code comprising instructions executable by at least one computing device. The computer readable medium can be associated with any data storage device that can store data which can be read by a computer system. Exemplary computer readable media can include read-only memory, random-access memory, CD-ROMs, HDDs, DVDs, magnetic tape, and optical data storage devices, among others. The computer readable medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
The above description of the technology may refer to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration embodiments in which the described embodiments may be practiced. These embodiments, while described in sufficient detail to enable those skilled in the art to practice them, are non-limiting; other embodiments may be utilized and changes may be made without departing from the scope of the described embodiments. For example, the order of operations described in a flowchart is non-limiting, and thus the order of two or more operations illustrated in and described in accordance with the flowchart may be altered in accordance with several embodiments. As another example, in several embodiments, one or more operations illustrated in and described with respect to the flowcharts are optional or may be eliminated. Additionally, certain steps or functions may be added to the disclosed embodiments, or two or more steps may be permuted in order. All such variations are considered to be encompassed by the disclosed embodiments and the claims.
Additionally, terminology is used in the foregoing description of the technology to provide a thorough understanding of the described embodiments. However, no unnecessary detail is required to implement the described embodiments. Accordingly, the foregoing description of the embodiments has been presented for purposes of illustration and description. The embodiments presented in the foregoing description and the examples disclosed in accordance with these embodiments are provided solely to add context and aid in the understanding of the described embodiments. The above description is not intended to be exhaustive or to limit the described embodiments to the precise form disclosed. Many modifications, alternative uses, and variations are possible in light of the above teaching. In some instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the described embodiments.
Claims (12)
- A frequency processing method is applicable to a series circuit, the series circuit comprises more than two chip groups which are mutually connected in parallel, each chip group comprises more than two chips which are sequentially connected in series, and the frequency processing method comprises the following steps:determining a frequency combination;and adjusting the working frequency combination of the chips in the same voltage domain in the series circuit into the frequency combination.
- The frequency processing method of claim 1, wherein the determining a frequency combination comprises:determining the physique grade of each chip in each voltage domain;determining the optimal working frequency of each chip with the same constitution grade in each voltage domain;and combining the optimal working frequencies of the chips with different physique grades into the frequency combination.
- The method of claim 2, wherein determining the fitness level of each chip in each voltage domain comprises:adjusting the stepping according to a preset frequency to enable each chip in the series circuit to work at different working frequencies in sequence;determining the calculation force value of each chip on each working frequency;determining the longitudinal force calculation sum of each chip on each working frequency based on the force calculation value; the longitudinal force calculation sum is the sum of force calculation values of the same chip on different working frequencies;and determining the physique grade of each chip in each voltage domain based on the longitudinal force calculation sum.
- The method of claim 3, wherein determining the computation force value for each chip at each operating frequency comprises:determining the number of the chips on any working frequency aiming at any chip;and taking the product of the working frequency and the echo number as a calculation force value of the chip under the working frequency.
- The method of claim 2, wherein determining the optimal operating frequency for each chip having the same quality class in each voltage domain comprisesDetermining the transverse force sum of each chip of any constitution grade in any voltage domain under each working frequency; wherein, the transverse calculation force sum is the sum of calculation force values of all chips of the physique grades in the voltage domain under all working frequencies;and determining the maximum lateral computing force and the corresponding working frequency as the optimal working frequency of the chips of the physique grades in the voltage domain.
- A frequency processing apparatus, characterized in that the apparatus is adapted to a series circuit, the series circuit comprises more than two mutually parallel chip sets, each chip set comprises more than two chips connected in series in turn, the apparatus comprises: a processor and a memory, the memory having instructions stored therein that, when executed by the processor, perform the method of:determining a frequency combination;and adjusting the working frequency combination of the chips in the same voltage domain in the series circuit into the frequency combination.
- The apparatus of claim 6, wherein the processor, when determining the frequency combination, is configured to:determining the physique grade of each chip in each voltage domain;determining the optimal working frequency of each chip with the same constitution grade in each voltage domain;and combining the optimal working frequencies of the chips with different physique grades into the frequency combination.
- The apparatus of claim 7, wherein the processor determines the quality class of each chip in each voltage domain by:adjusting the stepping according to a preset frequency to enable each chip in the series circuit to work at different working frequencies in sequence;determining the calculation force value of each chip on each working frequency;determining the longitudinal force calculation sum of each chip on each working frequency based on the force calculation value; the longitudinal force calculation sum is the sum of force calculation values of the same chip on different working frequencies;and determining the physique grade of each chip in each voltage domain based on the longitudinal force calculation sum.
- The apparatus of claim 8, wherein the processor determines the computation power of each chip at each operating frequency by:determining the number of the chips on any working frequency aiming at any chip;and taking the product of the working frequency and the echo number as a calculation force value of the chip under the working frequency.
- The apparatus of claim 7, wherein the processor determines the optimal operating frequency of each chip with the same quality class in each voltage domain by:determining the transverse calculation force sum of each chip of any constitution grade in any voltage domain under each working frequency; wherein, the transverse calculation force sum is the sum of calculation force values of all chips of the physique grades in the voltage domain under all working frequencies;and determining the maximum lateral computing force and the corresponding working frequency as the optimal working frequency of the chips of the physique grades in the voltage domain.
- A computer device, characterized in that the computer device comprises a series circuit, and a frequency processing means according to any of claims 6-10;the series circuit comprises more than two chip groups which are connected in parallel, each chip group comprises more than two chips which are connected in series in sequence, and the frequency processing device is used for adjusting the working frequency of the chips on the series circuit.
- A computer storage medium having stored thereon computer-executable instructions configured to perform the method of any one of claims 1-5.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/117504 WO2020107175A1 (en) | 2018-11-26 | 2018-11-26 | Frequency processing method, device and apparatus, and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112805657A true CN112805657A (en) | 2021-05-14 |
| CN112805657B CN112805657B (en) | 2024-04-30 |
Family
ID=70854737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880098349.XA Active CN112805657B (en) | 2018-11-26 | 2018-11-26 | Frequency processing method, device, equipment and storage medium |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112805657B (en) |
| WO (1) | WO2020107175A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117234744A (en) * | 2023-11-15 | 2023-12-15 | 成都芯脉微电子有限责任公司 | Multi-chip system performance optimization method, system, electronic equipment and medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150153819A1 (en) * | 2013-11-29 | 2015-06-04 | Fujitsu Limited | Management apparatus and method for controlling information processing apparatuses |
| CN106569574A (en) * | 2015-10-10 | 2017-04-19 | 中兴通讯股份有限公司 | Frequency management method and device for multicore CPU (Central Processing Unit) |
| CN106774767A (en) * | 2016-12-16 | 2017-05-31 | 算丰科技（北京）有限公司 | Series-fed chip and system, virtual digit coin dig ore deposit machine and server |
| CN106855838A (en) * | 2016-12-29 | 2017-06-16 | 杭州嘉楠耘智信息科技有限公司 | Working frequency adjusting method, device and system |
| CN206523836U (en) * | 2016-12-16 | 2017-09-26 | 算丰科技（北京）有限公司 | Series-fed chip and system |
| CN107621865A (en) * | 2017-09-20 | 2018-01-23 | 北京比特大陆科技有限公司 | Series-fed circuit and its powering method, dig ore deposit machine, server, equipment |
-
2018
- 2018-11-26 WO PCT/CN2018/117504 patent/WO2020107175A1/en active Application Filing
- 2018-11-26 CN CN201880098349.XA patent/CN112805657B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150153819A1 (en) * | 2013-11-29 | 2015-06-04 | Fujitsu Limited | Management apparatus and method for controlling information processing apparatuses |
| CN106569574A (en) * | 2015-10-10 | 2017-04-19 | 中兴通讯股份有限公司 | Frequency management method and device for multicore CPU (Central Processing Unit) |
| CN106774767A (en) * | 2016-12-16 | 2017-05-31 | 算丰科技（北京）有限公司 | Series-fed chip and system, virtual digit coin dig ore deposit machine and server |
| CN206523836U (en) * | 2016-12-16 | 2017-09-26 | 算丰科技（北京）有限公司 | Series-fed chip and system |
| CN106855838A (en) * | 2016-12-29 | 2017-06-16 | 杭州嘉楠耘智信息科技有限公司 | Working frequency adjusting method, device and system |
| CN107621865A (en) * | 2017-09-20 | 2018-01-23 | 北京比特大陆科技有限公司 | Series-fed circuit and its powering method, dig ore deposit machine, server, equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117234744A (en) * | 2023-11-15 | 2023-12-15 | 成都芯脉微电子有限责任公司 | Multi-chip system performance optimization method, system, electronic equipment and medium |
| CN117234744B (en) * | 2023-11-15 | 2024-01-30 | 成都芯脉微电子有限责任公司 | Multi-chip system performance optimization method, system, electronic equipment and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020107175A1 (en) | 2020-06-04 |
| CN112805657B (en) | 2024-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3306832A1 (en) | Method for multi-point cooperation considering delay in wireless communication system | |
| CN106911780A (en) | Traffic ID generation method, apparatus and system | |
| CN111506154B (en) | Method and system for increasing computing power and reducing computing power ratio of computer | |
| US20110196916A1 (en) | Client terminal, server, cloud computing system, and cloud computing method | |
| CN104461673A (en) | Virtual machine transferring judgment method and device | |
| CN111984204B (en) | Data reading and writing method and device, electronic equipment and storage medium | |
| CN112805657A (en) | Frequency processing method, device, equipment and storage medium | |
| CN111511028A (en) | Multi-user resource allocation method, device, system and storage medium | |
| CN114429195B (en) | Performance optimization method and device for training mixed expert model | |
| KR102562732B1 (en) | Apparatus and Method for Task Offloading of MEC-Based Wireless Network | |
| CN112217608B (en) | Data rate adjusting method and device, computer readable medium and electronic equipment | |
| CN105027100A (en) | Data sharing system | |
| CN108459926A (en) | Data remote backup method, apparatus and computer-readable medium | |
| CN115964984B (en) | Method and device for balanced winding of digital chip layout | |
| CN115883391A (en) | Single-user service selection method and device | |
| CN105472029A (en) | Single sign-on method and system based on cache | |
| CN112291326B (en) | Load balancing method, load balancing device, storage medium and electronic equipment | |
| CN103117955A (en) | Method, device and system of message transmission | |
| CN110620733A (en) | Service flow control method and device | |
| US10014896B2 (en) | Dual receive processing in wireless communications | |
| CN102215213B (en) | Multimedia frequency control method, equipment and system | |
| CN105072047A (en) | Message transmitting and processing method | |
| CN106096022B (en) | Method and device for dividing multi-domain network packet classification rules | |
| CN104202095A (en) | Base station floor noise reducing method and device | |
| KR101653090B1 (en) | Method and Apparatus for Efficient Spectrum Sharing for Multiple D2D Group Communications Based on Interference Alignment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |