CN117234744A - Multi-chip system performance optimization method, system, electronic equipment and medium - Google Patents
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Abstract
The application belongs to the technical field of high-performance computing, and aims to provide a multi-chip system performance optimization method, a multi-chip system performance optimization system, electronic equipment and a multi-chip system medium. In the implementation process, the optimal working frequency of each chip in the multi-chip system is obtained, then the average working frequency of all chips in each voltage domain in the multi-chip system is obtained according to the optimal working frequency of each chip, then the lowest average working frequency in all voltage domains is obtained according to the average working frequency of all chips in each voltage domain, and finally the working frequency of each chip in the multi-chip system is adjusted according to the lowest average working frequency in all voltage domains, so that the self-adaptive optimization of the performance of the multi-chip system is realized, the overall optimal performance of the multi-chip system can be achieved under the condition that the operation is kept stable, and the multi-chip system has popularization and application values.
Description
Technical Field
The application belongs to the technical field of high-performance computing, and particularly relates to a multi-chip system performance optimization method, a multi-chip system performance optimization system, electronic equipment and a multi-chip system medium.
Background
The multi-chip system is an electronic device in which a plurality of special function chips (or chiplets) are packaged as a whole, which can realize optimization of power consumption and further reduce the cost of the electronic device. At present, a multi-chip system such as an encryption computing server is generally composed of 100-1000 encryption computing chips, the encryption computing chips are integrally arranged on a computing board, and a serial power supply mode is generally adopted to supply power to the encryption computing chips at present, so that the production cost can be reduced, and the energy conversion efficiency of a power supply can be improved. However, in using the prior art, the inventors found that there are at least the following problems in the prior art:
under the current chip replacing technical conditions, individual performance differences exist among the calculated chips due to the chip production and manufacturing process, chip packaging and other reasons, for example, certain differences exist in the highest working frequency of a plurality of chips which can operate under a specific voltage. Under the prior art condition, the multi-chip system can configure the same frequency for all chips to avoid damaging the balance of each voltage domain in the serial power supply, which is not beneficial to exerting the maximum overall performance of all the encryption computing chips, so that the overall performance of the multi-chip system is not optimal.
Therefore, how to increase the overall computing power of the encryption computing chip in the serial power supply mode becomes a problem that a technician needs to pay attention to.
Disclosure of Invention
The application aims to solve the technical problems at least to a certain extent, and provides a multi-chip system performance optimization method, a multi-chip system performance optimization system, electronic equipment and a multi-chip system medium.
In order to achieve the above purpose, the present application adopts the following technical scheme:
in a first aspect, the present application provides a method for optimizing performance of a multi-chip system, including:
obtaining the optimal working frequency of each chip in the multi-chip system; the multi-chip system is divided into a plurality of voltage domains, and each voltage domain comprises a plurality of chips connected in parallel;
according to the optimal working frequency of each chip, the average working frequency of all chips in each voltage domain in the multi-chip system is obtained;
obtaining the lowest average working frequency in all the voltage domains according to the average working frequency of all the chips in each voltage domain;
and adjusting the working frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains.
The application can ensure the power supply balance of each voltage domain, so that all chips in the multi-chip system can achieve the optimal working performance, the self-adaptive optimization of the performance of the multi-chip system is realized, and the application is applicable to the performance adjustment of most multi-chip systems. Specifically, in the implementation process, the optimal working frequency of each chip in the multi-chip system is obtained, then the average working frequency of all chips in each voltage domain in the multi-chip system is obtained according to the optimal working frequency of each chip, then the lowest average working frequency in all voltage domains is obtained according to the average working frequency of all chips in each voltage domain, and finally the working frequency of each chip in the multi-chip system is adjusted according to the lowest average working frequency in all voltage domains, so that the self-adaptive optimization of the performance of the multi-chip system is realized, the multi-chip system can achieve the overall optimal performance under the condition of keeping the operation stable, and the popularization and application values are realized.
In one possible design, obtaining the optimal operating frequency for any one chip in a multi-chip system includes:
testing the working state of the current chip under test voltage and test frequency to obtain the number of computing cores which can normally work in the chip;
judging whether all the computing cores in the chip can work normally according to the number of the computing cores which can work normally in the chip, if so, increasing the test frequency to obtain an increased test frequency, taking the increased test frequency as the test frequency, and then carrying out working state test on the current chip under the test voltage and the test frequency again; if not, entering the next step;
judging whether the number of the computing cores which can normally work in the chip is larger than a preset threshold value, if so, stopping working state test, and taking the current test frequency as the optimal working frequency of the chip; if not, reducing the test frequency to obtain the reduced test frequency, taking the reduced test frequency as the test frequency, and then carrying out working state test on the current chip under the test voltage and the test frequency again.
In one possible design, the average operating frequency of all chips in any one voltage domain in the multi-chip system is the average of the current optimal operating frequencies of all chips in the voltage domain.
In one possible design, the lowest average operating frequency in all voltage domains is:
C=min{B voltage domain 1 ，B Voltage domain 2 ，……，B Voltage domain j ，……，B Voltage domain n }；
Wherein B is Voltage domain j An average operating frequency for all chips in a jth voltage domain in the multi-chip system; n is the total number of voltage domains in the multi-chip system, and n is a natural number greater than 1.
In one possible design, the operating frequency adjustment for each chip in the multi-chip system according to the lowest average operating frequency in all voltage domains includes:
obtaining the adjustment frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains;
according to the adjusting frequency of each chip in the multi-chip system, the working frequency of each chip in the multi-chip system is adjusted to obtain the final working frequency of each chip in the multi-chip system; wherein the average final operating frequency of all chips in each voltage domain in the multi-chip system is the same as the lowest average operating frequency.
In one possible design, the adjustment frequency of the ith chip in the multi-chip system is:
D chip i =(B Voltage domain i' -C)/n；
Wherein B is Voltage domain i' For the average operating frequency of all chips in the voltage domain where chip i is located, i' e {1,2, … …, n }, n being the total number of voltage domains in the multi-chip system, n being a natural number greater than 1; c is the lowest average operating frequency in all voltage domains;
correspondingly, the final working frequency of the ith chip in the multi-chip system is as follows:
E chip i =A Chip i -D Chip i ；
Wherein A is Chip i The optimal operating frequency of the ith chip.
In one possible design, after obtaining the final operating frequency of each chip in the multi-chip system, the method further includes:
after restarting the multi-chip system each time, configuring the working frequency of each chip in the multi-chip system according to the final working frequency of each chip in the multi-chip system.
In a second aspect, the present application provides a multi-chip system performance optimization system for implementing a multi-chip system performance optimization method as described in any one of the above; the multi-chip system performance optimization system comprises:
the chip testing module is used for obtaining the optimal working frequency of each chip in the multi-chip system; the multi-chip system is divided into a plurality of voltage domains, and each voltage domain comprises a plurality of chips connected in parallel;
the first calculation module is in communication connection with the chip test module and is used for acquiring the average working frequency of all chips in each voltage domain in the multi-chip system according to the optimal working frequency of each chip;
the second calculation module is in communication connection with the first calculation module and is used for obtaining the lowest average working frequency in all the voltage domains according to the average working frequency of all the chips in each voltage domain;
and the performance optimization module is in communication connection with the second calculation module and is used for adjusting the working frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains.
In a third aspect, the present application provides an electronic device, comprising:
a memory for storing computer program instructions; the method comprises the steps of,
a processor for executing the computer program instructions to perform the operations of the multi-chip system performance optimization method as set forth in any one of the preceding claims.
In a fourth aspect, the present application provides a computer readable storage medium storing computer program instructions that are configured to perform, when run, the operations of the multi-chip system performance optimization method of any one of the above.
Drawings
FIG. 1 is a flow chart of a method of optimizing performance of a multichip system in example 1;
FIG. 2 is a flowchart for obtaining the optimal operating frequency of any chip in the multichip system in example 1;
FIG. 3 is a block diagram of a multi-chip system performance optimization system of example 2;
fig. 4 is a block diagram of an electronic device in embodiment 3.
Detailed Description
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the present application will be briefly described below with reference to the accompanying drawings and the description of the embodiments or the prior art, and it is obvious that the following description of the structure of the drawings is only some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art. It should be noted that the description of these examples is for aiding in understanding the present application, but is not intended to limit the present application.
Example 1:
the embodiment discloses a performance optimization method of a multi-chip system, which can be executed by a computer device or a virtual machine with certain computing resources, for example, an electronic device such as a personal computer, a smart phone, a personal digital assistant or a wearable device, or a virtual machine.
As shown in FIG. 1, a method for optimizing performance of a multi-chip system may include, but is not limited to, the following steps:
s1, obtaining the optimal working frequency of each chip in a multi-chip system; wherein the multi-chip system is divided into a plurality of voltage domains, each voltage domain comprises a plurality of chips connected in parallel, and the ith chip in the multi-chip system is divided into a plurality of voltage domainsThe optimal working frequency is marked as A Chip i The method comprises the steps of carrying out a first treatment on the surface of the It should be appreciated that a multi-chip system includes a power board and a plurality of chips integrally disposed on the power board that can exert a maximum power when operated at an optimal operating frequency. Specifically, taking 108 chips as an example in a multi-chip system, the multi-chip system is divided into 18 voltage domains, each voltage domain comprises 6 chips, all chips in a single voltage domain are connected in parallel, and a chipset between the voltage domains is connected in series.
In this embodiment, as shown in fig. 2, obtaining the optimal operating frequency of any chip in the multi-chip system includes:
testing the working state of the current chip under test voltage and test frequency to obtain the number of computing cores which can normally work in the chip; it should be noted that, generally, several tens of computing cores are disposed in a single chip, the computing cores may also be represented as cores, and multiple computing cores may execute computing tasks of the chip in parallel. When the working state test is carried out on the chip, if any computing core can calculate a preset test task to obtain a correct result, the core is considered to work normally under the test voltage and the test frequency.
Judging whether all the computing cores in the chip can work normally or not according to the number of the computing cores which can work normally in the chip, namely judging whether the number of the computing cores which can work normally in the chip is the same as the total number of the computing cores in the chip or not, if so, increasing the test frequency to obtain the increased test frequency, taking the increased test frequency as the test frequency, and then carrying out working state test on the current chip under the test voltage and the test frequency again; if not, entering the next step;
judging whether the number of the computing cores which can normally work in the chip is larger than a preset threshold value, if so, stopping working state test, and taking the current test frequency as the optimal working frequency of the chip; if not, reducing the test frequency to obtain the reduced test frequency, taking the reduced test frequency as the test frequency, and then carrying out working state test on the current chip under the test voltage and the test frequency again.
It should be noted that in this embodiment, the foregoing steps provide a basis for determining the computing capability of a single chip, based on which the optimal operating frequency of each chip in the multi-chip system can be obtained, and the chip can have the optimal operating performance under the optimal operating frequency.
S2, acquiring the average working frequency of all chips in each voltage domain in the multi-chip system according to the optimal working frequency of each chip; wherein the average operating frequency of all chips in the jth voltage domain is denoted as B Voltage domain j 。
Specifically, in this embodiment, the average operating frequency of all the chips in any one voltage domain in the multi-chip system is the average value of the current optimal operating frequencies of all the chips in the voltage domain.
S3, obtaining the lowest average working frequency in all the voltage domains according to the average working frequency of all the chips in each voltage domain.
Wherein the lowest average operating frequency in all voltage domains is: c=min { B Voltage domain 1 ，B Voltage domain 2 ，……，B Voltage domain j ，……，B Voltage domain n }。
Wherein B is Voltage domain j An average operating frequency for all chips in a jth voltage domain in the multi-chip system; n is the total number of voltage domains in the multi-chip system, and n is a natural number greater than 1.
S4, adjusting the working frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains.
In this embodiment, the adjusting the operating frequency of each chip in the multi-chip system according to the lowest average operating frequency in all voltage domains includes:
s401, obtaining the adjustment frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains.
S402, adjusting the working frequency of each chip in the multi-chip system according to the adjusting frequency of each chip in the multi-chip system to obtain the final working frequency of each chip in the multi-chip system; wherein the average final operating frequency of all chips in each voltage domain in the multi-chip system is the same as the lowest average operating frequency.
Specifically, in this embodiment, the adjustment frequency of the ith chip in the multi-chip system is:
D chip i =(B Voltage domain i' -C)/n；
Wherein B is Voltage domain i' For the average operating frequency of all chips in the voltage domain where chip i is located, i' e {1,2, … …, n }, n being the total number of voltage domains in the multi-chip system, n being a natural number greater than 1; c is the lowest average operating frequency in all voltage domains;
correspondingly, the final working frequency of the ith chip in the multi-chip system is as follows:
E chip i =A Chip i -D Chip i ；
Wherein A is Chip i The optimal operating frequency of the ith chip.
In this embodiment, after obtaining the final working frequency of each chip in the multi-chip system, the method further includes:
after restarting the multi-chip system each time, configuring the working frequency of each chip in the multi-chip system according to the final working frequency of each chip in the multi-chip system.
From the practical effect of the embodiment, the performance of the multi-chip system can be improved by 5% -10% without sacrificing the overall stability of the multi-chip system. From the aspect of overall performance and power, the embodiment can well solve the problem of power distribution among multiple chips, and the chips with better computing capacity can be distributed to obtain more working frequencies, so that the multi-chip system in the embodiment has better overall performance under the same power. From the aspect of production cost, the embodiment can avoid inputting extremely high cost to grade chips, so that chips with certain performance differences can be used in the same multi-chip system.
The embodiment can ensure that all chips in the multi-chip system reach the optimal working performance (namely the optimal working frequency) under the condition of ensuring the power supply balance of each voltage domain, thereby realizing the self-adaptive optimization of the performance of the multi-chip system and being applicable to the performance adjustment of most multi-chip systems. Specifically, in the implementation process, the optimal working frequency of each chip in the multi-chip system is obtained, then the average working frequency of all chips in each voltage domain in the multi-chip system is obtained according to the optimal working frequency of each chip, then the lowest average working frequency in all voltage domains is obtained according to the average working frequency of all chips in each voltage domain, and finally the working frequency of each chip in the multi-chip system is adjusted according to the lowest average working frequency in all voltage domains, so that the self-adaptive optimization of the performance of the multi-chip system is realized, the overall optimal performance of the multi-chip system can be achieved under the condition that the operation is kept stable, and the popularization and application values are realized.
An alternative to this embodiment is as follows: the chips are divided into 5 grades according to the performance, or the chips are divided into 10 grades by putting more cost, and the chips with the same grade are assembled in the assembling process of the multi-chip system, so that the chips in the multi-chip system can obtain consistent performance. It is thus apparent that the present embodiment can be applied to a fully assembled multi-chip system with lower application costs relative to this alternative.
Example 2:
the embodiment discloses a performance optimization system of a multi-chip system, which is used for realizing the performance optimization method of the multi-chip system in the embodiment 1; as shown in fig. 3, the multi-chip system performance optimization system includes:
the chip testing module is used for obtaining the optimal working frequency of each chip in the multi-chip system; the multi-chip system is divided into a plurality of voltage domains, and each voltage domain comprises a plurality of chips connected in parallel;
the first calculation module is in communication connection with the chip test module and is used for acquiring the average working frequency of all chips in each voltage domain in the multi-chip system according to the optimal working frequency of each chip;
the second calculation module is in communication connection with the first calculation module and is used for obtaining the lowest average working frequency in all the voltage domains according to the average working frequency of all the chips in each voltage domain;
and the performance optimization module is in communication connection with the second calculation module and is used for adjusting the working frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains.
Example 3:
on the basis of embodiment 1 or 2, this embodiment discloses an electronic device, which may be a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like. An electronic device may be referred to as a terminal, a portable terminal, a desktop terminal, etc., as shown in fig. 4, the electronic device includes:
a memory for storing computer program instructions; the method comprises the steps of,
a processor configured to execute the computer program instructions to perform the operations of the multi-chip system performance optimization method of any of embodiment 1.
In particular, processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 301 may be implemented in at least one hardware form of DSP (Digital Signal Processing ), FPGA (Field-Programmable Gate Array, field programmable gate array), PLA (Programmable Logic Array ). The processor 301 may also include a main processor, which is a processor for processing data in an awake state, also called a CPU (Central Processing Unit ), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 301 may integrate a GPU (Graphics Processing Unit, image processor) for rendering and drawing of content required to be displayed by the display screen.
Memory 302 may include one or more computer-readable storage media, which may be non-transitory. Memory 302 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in memory 302 is used to store at least one instruction for execution by processor 301 to implement the multi-chip system performance optimization method provided in embodiment 1 of the present application.
In some embodiments, the terminal may further optionally include: a communication interface 303, and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected by a bus or signal lines. The respective peripheral devices may be connected to the communication interface 303 through a bus, signal line, or circuit board. Specifically, the peripheral device includes: at least one of radio frequency circuitry 304, a display screen 305, and a power supply 306.
The communication interface 303 may be used to connect at least one peripheral device associated with an I/O (Input/Output) to the processor 301 and the memory 302. In some embodiments, processor 301, memory 302, and communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, either or both of the processor 301, the memory 302, and the communication interface 303 may be implemented on separate chips or circuit boards, which is not limited in this embodiment.
The Radio Frequency circuit 304 is configured to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuitry 304 communicates with a communication network and other communication devices via electromagnetic signals.
The display screen 305 is used to display a UI (User Interface). The UI may include graphics, text, icons, video, and any combination thereof.
The power supply 306 is used to power the various components in the electronic device.
Example 4:
on the basis of any one of embodiments 1 to 3, this embodiment discloses a computer-readable storage medium for storing computer-readable computer program instructions configured to perform the operations of the multi-chip system performance optimization method described in embodiment 1 when run.
It will be apparent to those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, or they may alternatively be implemented in program code executable by computing devices, such that they may be stored in a memory device for execution by the computing devices, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps within them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solution of the present application, and not limiting thereof; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced by equivalents. Such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A multi-chip system performance optimization method is characterized in that: comprising the following steps:
obtaining the optimal working frequency of each chip in the multi-chip system; the multi-chip system is divided into a plurality of voltage domains, and each voltage domain comprises a plurality of chips connected in parallel;
according to the optimal working frequency of each chip, the average working frequency of all chips in each voltage domain in the multi-chip system is obtained;
obtaining the lowest average working frequency in all the voltage domains according to the average working frequency of all the chips in each voltage domain;
and adjusting the working frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains.
2. The method for optimizing the performance of a multichip system according to claim 1, wherein: the method for obtaining the optimal working frequency of any chip in the multi-chip system comprises the following steps:
testing the working state of the current chip under test voltage and test frequency to obtain the number of computing cores which can normally work in the chip;
judging whether all the computing cores in the chip can work normally according to the number of the computing cores which can work normally in the chip, if so, increasing the test frequency to obtain an increased test frequency, taking the increased test frequency as the test frequency, and then carrying out working state test on the current chip under the test voltage and the test frequency again; if not, entering the next step;
judging whether the number of the computing cores which can normally work in the chip is larger than a preset threshold value, if so, stopping working state test, and taking the current test frequency as the optimal working frequency of the chip; if not, reducing the test frequency to obtain the reduced test frequency, taking the reduced test frequency as the test frequency, and then carrying out working state test on the current chip under the test voltage and the test frequency again.
3. The method for optimizing the performance of a multichip system according to claim 1, wherein: the average operating frequency of all chips in any one of the voltage domains in the multi-chip system is the average of the current optimal operating frequencies of all chips in the voltage domain.
4. The method for optimizing the performance of a multichip system according to claim 1, wherein: the lowest average operating frequency in all voltage domains is:
C=min{B voltage domain 1 ，B Voltage domain 2 ，……，B Voltage domain j ，……，B Voltage domain n }；
Wherein B is Voltage domain j An average operating frequency for all chips in a jth voltage domain in the multi-chip system; n is the total number of voltage domains in the multi-chip system, and n is a natural number greater than 1.
5. The method for optimizing the performance of a multichip system according to claim 1, wherein: and adjusting the working frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains, wherein the method comprises the following steps:
obtaining the adjustment frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains;
according to the adjusting frequency of each chip in the multi-chip system, the working frequency of each chip in the multi-chip system is adjusted to obtain the final working frequency of each chip in the multi-chip system; wherein the average final operating frequency of all chips in each voltage domain in the multi-chip system is the same as the lowest average operating frequency.
6. The method for optimizing the performance of a multichip system according to claim 5, wherein: the adjustment frequency of the ith chip in the multi-chip system is as follows:
D chip i =(B Voltage domain i' -C)/n；
Wherein B is Voltage domain i' For the average operating frequency of all chips in the voltage domain where chip i is located, i' e {1,2, … …, n }, n being the total number of voltage domains in the multi-chip system, n being a natural number greater than 1; c is the lowest average operating frequency in all voltage domains;
correspondingly, the final working frequency of the ith chip in the multi-chip system is as follows:
E chip i =A Chip i -D Chip i ；
Wherein A is Chip i The optimal operating frequency of the ith chip.
7. The method for optimizing the performance of a multichip system according to claim 4, wherein: after obtaining the final working frequency of each chip in the multi-chip system, the method further comprises:
after restarting the multi-chip system each time, configuring the working frequency of each chip in the multi-chip system according to the final working frequency of each chip in the multi-chip system.
8. A multi-chip system performance optimization system, characterized by: for implementing the multi-chip system performance optimization method of any one of claims 1 to 7; the multi-chip system performance optimization system comprises:
the chip testing module is used for obtaining the optimal working frequency of each chip in the multi-chip system; the multi-chip system is divided into a plurality of voltage domains, and each voltage domain comprises a plurality of chips connected in parallel;
the first calculation module is in communication connection with the chip test module and is used for acquiring the average working frequency of all chips in each voltage domain in the multi-chip system according to the optimal working frequency of each chip;
the second calculation module is in communication connection with the first calculation module and is used for obtaining the lowest average working frequency in all the voltage domains according to the average working frequency of all the chips in each voltage domain;
and the performance optimization module is in communication connection with the second calculation module and is used for adjusting the working frequency of each chip in the multi-chip system according to the lowest average working frequency in all voltage domains.
9. An electronic device, characterized in that: comprising the following steps:
a memory for storing computer program instructions; the method comprises the steps of,
a processor for executing the computer program instructions to perform the operations of the multi-chip system performance optimization method of any one of claims 1 to 7.
10. A computer readable storage medium storing computer program instructions readable by a computer, characterized by: the computer program instructions are configured to perform the operations of the multi-chip system performance optimization method of any one of claims 1 to 7 when run.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117234744B (en) | 2024-01-30 |
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