CN110045793A - Computing device and computing system - Google Patents

Abstract

The present invention provides a computing device and computing system, wherein the computing device includes: a plurality of computing chips connected in series; and a plurality of LDO modules, respectively connected to the plurality of computing chips; wherein, each computing chip The signal input terminal of 1 is connected to the output terminal of an LDO module. The computing device and computing system of the present invention supply power to the input signal of the computing chip through the LDO module, improve the signal transmission quality and transmission rate, and avoid the reduction of signal transmission quality caused by uneven voltage division of the computing chip.

Description

Computing devices and computing systems

technical field

The invention belongs to the technical field of computing, and in particular relates to a computing device and a computing system.

Background technique

At present, with the development of computing technology, the computing demand with large amount of data and high complexity also increases, and the chip core voltage required to complete this type of complex computing increases accordingly. Since the computing chips are usually connected in series, the core voltage of the previous-stage chip is the reference ground voltage of the next-stage chip. As the core voltage of the chip increases, the reference ground voltage of the latter-stage chip increases, causing signal interference and affecting signal transmission. quality and transmission efficiency. To make the signal undisturbed, you need to increase the amplitude of the signal. However, increasing the amplitude of the signal results in a substantial increase in the cost of the system, as well as a significant increase in heat generation, which affects the performance of the system.

In general, the existing computing devices and computing systems mainly have the following technical defects: uneven voltage division of the core of the computing chip, which affects the quality of signal transmission; and low transmission rate, which cannot well meet the needs of use.

Therefore, there is an urgent need to provide a computing device and computing system with good signal transmission quality and high transmission rate.

SUMMARY OF THE INVENTION

(1) Technical problems to be solved

The present invention provides a computing device and a computing system to at least partially solve the above technical problems.

(2) Technical solutions

According to one aspect of the present invention, there is provided a computing device, comprising:

a plurality of computing chips connected in series; and

a plurality of LDO modules, respectively connected to the plurality of computing chips;

Wherein, the signal input end of each computing chip is connected with the output end of one LDO module.

In some embodiments, the plurality of computing chips are respectively: a first computing chip to an nth computing chip, wherein the input terminal of the kth computing chip is connected to the output terminal of the k-1th computing chip;

The plurality of LDO modules are respectively: the first LDO module to the nth LDO module, wherein the signal input terminal of the kth computing chip is connected to the output terminal of the kth LDO module; n≥2, 1≤k≤n;

The LDO module has a reference ground input terminal and a power input terminal.

In some embodiments, the reference ground input terminal of the kth LDO module is connected to the input terminal of the kth computing chip, and k takes a value of 1.

In some embodiments, the reference ground input terminal of the kth LDO module is connected to the output terminal of the k-1th computing chip, and k ranges from 2 to n.

In some embodiments, the computing device further includes: a power module connected to the power input terminal of the LDO module.

In some embodiments, the power input voltage of the kth LDO module is 3-4 times the core voltage of the kth computing chip.

A computing system, comprising one or more of the computing devices; further comprising:

an input data device, connected to the computing device, for receiving cloud data and transmitting it to the computing device; and

An output data device is connected to the computing device, and is used for transmitting the calculation result of the computing device to the cloud.

In some embodiments, the computing system further includes: a radiator, where the radiator includes a liquid-cooled heat dissipation unit and/or an air-cooled heat dissipation unit.

In some embodiments, the computing device is a pluggable computing device.

In some embodiments, the pluggable computing device has pluggable connectors and/or pluggable interfaces.

(3) Beneficial effects

It can be seen from the above technical solutions that the computing device and computing system of the present invention have at least one of the following beneficial effects:

(1) Supply power to the input signal of the computing chip through the LDO module. The reference ground voltage of the LDO module is the same as the reference ground voltage of the computing chip, so that there is no difference in core voltage between the computing chip signal power supply and the computing chip, so even if the computing chip core The uneven voltage division will not affect the signal voltage of the computing chip, thus improving the signal transmission quality and transmission rate, avoiding the reduction of signal transmission quality caused by uneven voltage division of the computing chip, and avoiding the increase of the computing chip due to the split of the chip. Signal transmission interruption caused by severe uneven pressure.

(2) The computing device and computing system of the present invention increase the voltage value of the signal power supply. Since the core voltage of the computing chip increases, the power supply amplitude that can be used to replace the LDO increases.

(3) The present invention adopts a pluggable computing device, and the pluggable computing device has a pluggable connector or interface. According to the needs of the calculation amount, the computing device can be added, and the computing chip can be added correspondingly, so that the overall computing can be improved. Force and capability density, facilitate replacement and maintenance of computing devices, and facilitate machine upgrades based on advances in chip technology.

(4) The computing devices in the computing system of this embodiment can work independently, and can also freely assemble different numbers of computing devices according to different power density requirements to form a computing system, which is easy to operate and fully meets the needs of users. need.

Description of drawings

FIG. 1 is a schematic structural diagram of a computing device according to the present invention.

FIG. 2 is a schematic structural diagram of a computing device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of another structure of a computing device according to an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a computing device according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of another structure of a computing device according to another embodiment of the present invention.

FIG. 6 is a schematic structural diagram of a computing device according to another embodiment of the present invention.

FIG. 7 is a schematic structural diagram of a computing system according to an embodiment of the present invention.

FIG. 8 is a schematic structural diagram of a computing system according to another embodiment of the present invention.

FIG. 9 is a schematic structural diagram of a heat sink according to yet another embodiment of the present invention.

10 is a schematic diagram of another structure of a heat sink according to still another embodiment of the present invention.

FIG. 11 is a schematic diagram of another structure of a heat sink according to another embodiment of the present invention.

FIG. 12 is a schematic diagram of a structure of a heat sink according to still another embodiment of the present invention.

13 is a schematic diagram of another structure of a heat sink according to still another embodiment of the present invention.

FIG. 14 is a schematic diagram of another structure of a heat sink according to still another embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

As shown in FIG. 1, a computing device includes: three computing chips A1, A2, A3 and three LDO modules M1, M2, M3. The three computing chips A1, A2, and A3 are connected in series. Specifically, the output terminal of the computing chip A1 is connected to the input terminal of the computing chip A2, and the output terminal of the computing chip A2 is connected to the computing chip A2. The input terminal of chip A3 is connected. The three LDO modules M1, M2, and M3 are respectively connected to the three computing chips A1, A2, and A3. Specifically, the output terminal of the LDO module M1 is connected to the signal output terminal of the computing chip A1. The output terminal of the LDO module M2 is connected to the signal output terminal of the computing chip A2, and the output terminal of the LDO module M3 is connected to the signal output terminal of the computing chip A3. Among them, an LDO is a low dropout voltage regulator, which produces a regulated output voltage by regulating a higher voltage input (subtracting the excess voltage from the applied input voltage). LDO devices have many different characteristics, such as low noise, wide input voltage, small size, low Iq and processor connections.

The signal power supply mode of the computing device shown in FIG. 1 is to supply power to the output signal, that is, the output of the LDO module of this stage is used to supply power to the output signal of the computing chip of this stage. The output signal power supply method is adopted. The reference ground of the LDO module powered by the signal is the ground of the previous stage signal. When the signal is transmitted to the subsequent stage, the reference ground of the signal is the core voltage of the previous stage signal. Then the voltage of the input signal is the same as that of the computing chip. There is a difference in nuclear voltage between the voltages. For example, the signal transmission direction is from the output terminal of computing chip A1 to the input terminal of computing chip A2, and then from the output terminal of computing chip A2 to the input terminal of computing chip A3. Since the chips are connected in series, the voltage output voltage of computing chip A1 Vcc is the reference ground voltage of the A2 chip. In this case, the LDO module is used to supply power to the IO of the computing chip A1. After the signal is transmitted to the computing chip A2, since the reference ground voltage of the computing chip A2 is the output voltage of the computing chip A1, so the signal The voltage range will decrease from 0V to 1.8V (the LDO power supply voltage is 1.8V) to the threshold value of the Vcc to 1.8V signal. The high level of the signal cannot meet the high level threshold of the input terminal of the next chip and is mistakenly regarded as a low level, which may cause an error in signal transmission.

In view of this, the present invention provides a computing device whose signal power supply mode is the input signal power supply, and by changing the signal power supply mode of the computing chip, the uneven voltage division of the chip can be avoided to reduce the signal transmission quality.

In an embodiment, as shown in FIG. 2 , the computing device includes: three computing chips A1 , A2 , and A3 and three LDO modules M1 , M2 , and M3 . The three computing chips A1, A2, and A3 are connected in series. Specifically, the output terminal of the computing chip A1 is connected to the input terminal of the computing chip A2, and the output terminal of the computing chip A2 is connected to the computing chip A2. The input terminal of chip A3 is connected. The three LDO modules M1, M2, and M3 are respectively connected to the three computing chips A1, A2, and A3. Specifically, the output terminal of the LDO module M1 is connected to the signal input terminal of the computing chip A1. The output end of the LDO module M2 is connected to the signal input end of the computing chip A2, and the output end of the LDO module M3 is connected to the signal input end of the computing chip A3.

The input signal of the computing chip is powered by the LDO module. The reference ground voltage of the LDO is the same as the reference ground voltage of the chip, so that there is no difference between the power supply of the chip signal and the core voltage of the chip, so even if the voltage of the chip core is unevenly divided, it will not be affected. The chip signal voltage, thereby improving the signal transmission quality and transmission rate.

Further, as shown in FIG. 3 , the LDO module also has a reference ground input terminal and a power input terminal. Specifically, the reference ground input terminal of the LDO module M1 is connected to the input terminal of the computing chip A1, and the reference ground input terminal of the LDO module M2 is connected to the input terminal (A1 output terminal) of the computing chip A2. The reference ground input terminal of the LDO module M3 is connected to the input terminal (A2 output terminal) of the computing chip A3.

In another implementation, as shown in FIG. 4 , the computing device includes: n computing chips A1, A2, A3, . . . , An-1, An and n LDO modules M1, M2, M3, ..., Mn-1, Mn. The n computing chips A1, A2, A3, ..., An-1 are connected in series, the output end of the computing chip A1 is connected to the input end of the computing chip A2, and the computing chip The output terminal of A2 is connected to the input terminal of the computing chip A3, . . . , the output terminal of the computing chip An-1 is connected to the input terminal of the computing chip An. The n LDO modules M1, M2, M3, ..., Mn-1, Mn are respectively connected to the n computing chips A1, A2, A3, ..., An-1, Specifically, the output terminal of the LDO module M1 is connected to the signal input terminal of the computing chip A1, the output terminal of the LDO module M2 is connected to the signal input terminal of the computing chip A2, and the output terminal of the LDO module M3 is connected to the signal input terminal of the computing chip A2. The terminal is connected to the signal input terminal of the computing chip A3, ..., the output terminal of the LDO module Mn-1 is connected to the signal input terminal of the computing chip An-1, and the LDO module Mn The output end is connected to the signal input end of the computing chip An.

Further, as shown in FIG. 5 , the reference ground input terminal of the LDO module M1 is connected to the input terminal of the computing chip A1, and the reference ground input terminal of the LDO module M2 is connected to the input terminal of the computing chip A2 (A1 output terminal). terminal) connection, the reference ground input terminal of the LDO module M3 is connected to the computing chip A3 input terminal (A2 output terminal), ..., the reference ground input terminal of the LDO module Mn-1 is connected to the The computing chip An-1 input terminal (An-2 output terminal) is connected, and the reference ground input terminal of the LDO module Mn is connected to the computing chip An input terminal (An-1 output terminal).

Please continue to refer to FIGS. 4-5. In general, in the first to nth computing chips, the input terminal of any kth computing chip is connected to the output terminal of the k-1th computing chip, and the signal of the kth computing chip is connected. The input terminal is connected to the output terminal of the kth LDO module; n≥2, 1≤k≤n; when k is 1, the reference ground input terminal of the kth LDO module is connected to the input of the kth computing chip end connection. When k is 2˜n, the reference ground input terminal of the kth LDO module is connected to the output terminal of the k−1th computing chip.

Of course, the number of the computing chips and the number of the LDO modules in the present invention are not limited to the numbers given in the foregoing embodiments, and those skilled in the art can appropriately adjust them according to computing requirements.

In yet another embodiment, as shown in FIG. 6 , the computing device further includes: a plurality of power supply modules connected to the power supply input terminals of the plurality of LDO modules. The power input voltage of the LDO module is 3-4 times the core voltage of the computing chip.

The present invention also provides a computing system, which includes one or more of the computing devices, and the signal power supply mode of the one or more computing devices is to supply power for an input signal.

In one embodiment, the computing system further includes an input data device for receiving cloud data and transmitting the data to the computing device.

Specifically, as shown in FIG. 7 , the computing system includes P computing devices, which are a first computing device, a second computing device, a third computing device, ..., the P-1th computing device, The P-th computing device, wherein the first to P-th computing devices are connected in sequence, that is, the first computing device is connected to the second computing device, and the second computing device is connected to the third computing device. ....., the P-1th computing device is connected to the Pth computing device, and the input data device is connected to the first computing device. The input data device sends a plurality of input data to the first computing device, the first computing device extracts the first data from the plurality of input data, and divides the first data from the plurality of data The data other than the data is transmitted to the second computing device, the second computing device extracts the second data from the received data, and transmits the remaining data to the third computing device, . . . and so on , the P-1th computing device extracts the P-1th data from the received data, and transmits the remaining data to the Pth computing device.

In another embodiment, the computing system further includes an output data device, which is connected to the computing device and is used for transmitting the calculation result of the computing device to the cloud.

Specifically, as shown in FIG. 8 , the computing system includes P computing devices, which are the first computing device, the second computing device, the third computing device, ......, the P-1th computing device, The P-th computing device, wherein the first to P computing devices are connected in sequence, that is, the first computing device is connected to the second computing device, the second computing device is connected to the third computing device, ... ...., the P-1th computing device is connected to the Pth computing device, and the output data device is connected to the Pth computing device. The first computing device transmits its calculation result to the second computing device, and the second computing device and the first computing device transmit the calculation result to the third computing device, . . . By analogy, the P-1th computing device transmits the calculation results of the 1st to P-1th computing devices to the Pth computing device, and the Pth computing device sends the calculation results of the 1st to Pth computing devices to the output data The device is sent to the cloud by the output data device.

In yet another embodiment, the computing system further includes one or more heat sinks, and the one or more heat sinks may be arranged outside the computing device or inside the computing device, that is, , each computing device can be dissipated independently, or the entire system can be dissipated. Specifically, as shown in FIG. 9 , the radiator may include a liquid-cooled heat dissipation unit. Alternatively, as shown in FIG. 10 , the heat sink may include an air-cooled heat dissipation unit. Alternatively, as shown in FIG. 11 , the radiator may include a liquid-cooled heat dissipation unit and an air-cooled heat dissipation unit at the same time.

In yet another embodiment, as shown in FIG. 12 , the computing system further includes a control device connected to the computing device for controlling the operation of the computing device. The number of control devices and computing devices included in the computing system can be appropriately adjusted as required.

Further, as shown in FIG. 13 , the computing device in the computing system is a pluggable computing device, which has a pluggable connector, and the control device has a pluggable connector matched with the pluggable connector. unplug the interface. Alternatively, as shown in FIG. 14 , the pluggable computing device has a pluggable interface, and the control device has a pluggable connector matched with the pluggable interface. The pluggable connector is connected to the pluggable interface by, for example, a gold finger-socket, a cable-socket, a plug-socket or the like.

The computing device and the control device of the present invention are connected to a pluggable interface through a pluggable connector, thereby facilitating the adjustment of the number of pluggable computing devices to be connected according to the amount of computation, and facilitating the pluggable computing devices maintenance and replacement, as well as facilitate the upgrading of computing systems based on advances in chip technology.

The computing devices in the computing system of this embodiment can work independently, and can also freely assemble different numbers of computing devices according to different power density requirements to form a computing system, which is easy to operate and fully meets the needs of users.

To sum up, the computing device and computing system provided by the present invention avoid the degradation of signal transmission quality caused by uneven voltage division of the computing chip core, improve the signal transmission rate, and better meet the usage requirements.

So far, the computing device and computing system according to the embodiments of the present invention have been described in detail with reference to the accompanying drawings. From the above description, those skilled in the art should have a clear understanding of the present invention.

It should be noted that, in the accompanying drawings or the text of the description, the implementations that are not shown or described are in the form known to those of ordinary skill in the technical field, and are not described in detail. In addition, the above definitions of each element are not limited to various specific structures, shapes or manners mentioned in the embodiments, and those of ordinary skill in the art can simply modify or replace them.

Of course, according to actual needs, the computing device and computing system of the present invention may also include other parts, which are not related to the innovation of the present invention, and will not be repeated here.

Similarly, it is to be understood that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or its description. However, this method of the invention should not be construed to reflect the intention that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single preceding embodiment of the invention. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. The modules or units or components in the embodiments may be combined into one module or unit or component, and further they may be divided into multiple sub-modules or sub-units or sub-assemblies. All features of the invention in this specification (including accompanying claims, abstract and drawings) and any method so invented may be employed in any combination, unless at least some of such features and/or procedures or elements are mutually exclusive. All processes or units of equipment are combined. Each feature of the invention in this specification (including the accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the relevant apparatus according to the embodiments of the present invention. The present invention can also be implemented as apparatus or apparatus programs (eg, computer programs and computer program products) for performing part or all of the methods described herein. Such a program implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such signals may be downloaded from Internet sites, or provided on carrier signals, or in any other form.

Furthermore, the ordinal numbers such as "1st", "2nd", "3rd" and other terms used in the description and the claims are used to modify the corresponding elements, and they do not imply and represent that the elements have any The ordinal numbers do not represent the order of a certain element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make an element with a certain name and another element with the same name can make it clear distinguish.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned specific embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principle of the present invention, any modifications, equivalent replacements, improvements, etc. made should be included within the protection scope of the present invention.

Claims (10)

1. a kind of computing device characterized by comprising

The multiple computing chips being connected in series；And

Multiple LDO modules, connect with the multiple computing chip respectively；

Wherein, the signal input part of each computing chip is connect with the output end of a LDO module.

2. computing device according to claim 1, which is characterized in that

The multiple computing chip is respectively as follows: the 1st computing chip to the n-th computing chip, wherein kth computing chip input terminal with The connection of -1 computing chip output end of kth；

The multiple LDO module is respectively as follows: the 1st LDO module to the n-th LDO module, wherein the signal of kth computing chip inputs End is connect with the output end of kth LDO module；N >=2,1≤k≤n；

The LDO module has a reference ground input terminal and a power input.

3. computing device according to claim 2, which is characterized in that the reference of kth LDO module ground input terminal with The input terminal of the kth computing chip connects, and k value is 1.

4. computing device according to claim 2, which is characterized in that the reference of kth LDO module ground input terminal with The output end of -1 computing chip of kth connects, and k value is 2~n.

5. computing device according to claim 2, which is characterized in that further include: power module, with the LDO module The power input connection.

6. computing device according to claim 5, which is characterized in that the power input voltage of the kth LDO module is 3~4 times of the core voltage of the kth computing chip.

7. a kind of computing system, which is characterized in that including one or more such as calculating described in any one of claims 1 to 6 Device；Further include:

Input data device is connect with the computing device, for receiving cloud data and being transmitted to the computing device；And

Output data device is connect with the computing device, for the calculated result of the computing device to be transmitted to cloud.

8. computing system according to claim 7, which is characterized in that further include: radiator, the radiator include that liquid cooling dissipates Hot cell and/or wind-cooling heat dissipating unit.

9. computing system according to claim 7, which is characterized in that the computing device is pluggable computing device.

10. computing system according to claim 9, which is characterized in that the pluggable computing device has pluggable connect Head and/or pluggable interface.