CN206557766U - Calculate every group of chip cascade communication control unit of power plate - Google Patents

Calculate every group of chip cascade communication control unit of power plate Download PDF

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Publication number
CN206557766U
CN206557766U CN201720180956.3U CN201720180956U CN206557766U CN 206557766 U CN206557766 U CN 206557766U CN 201720180956 U CN201720180956 U CN 201720180956U CN 206557766 U CN206557766 U CN 206557766U
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China
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chip
power
group
power chip
control unit
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CN201720180956.3U
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Inventor
胡东
包兴刚
吴树兴
周辉
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Zhejiang billion state communications technology Co., Ltd.
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Zhejiang E-Bang Communication Science And Technology Co Ltd
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Abstract

The utility model provides a kind of every group of chip cascade communication control unit of power plate of calculating and calculates power chip, at least one diode and at least one pull-up resistor including previous stage calculation power chip, rear stage.Rear stage calculation power chip structure is identical with previous stage calculation power chip and is in series with previous stage calculation power chip, and serial communication is carried out between the two.At least one diodes in reverse series is calculated power chip in previous stage and calculated to rear stage on the communication line of power chip transmission signal.The communication line that at least one pull-up resistor calculates power chip to rear stage calculation power chip transmission signal with previous stage respectively is connected.

Description

Calculate every group of chip cascade communication control unit of power plate
Technical field
The utility model is related to the communications field, and more particularly to a kind of calculation every group of chip cascade communication control unit of power plate.
Background technology
Calculating power plate design aspect, due to the electric current of every group of chip it is very big, it is necessary to group number it is a lot, therefore, every group of chip Power supply is cascaded down by way of series connection.Before the reference ground voltage for causing rear stage calculation power chip is equal to by this power supply mode One-level calculates the CORE voltages (processor voltage) of power chip so that there is electrical potential difference between the reference ground between group and group.Equally , between each group the voltage of same type there is also the electrical potential difference of equivalent so that between group and group communication interface peak peak Value there is also the electrical potential difference of equivalent, between chipset can not proper communication, chip interface is easily burned.
Utility model content
The utility model in order to overcome the deficiencies in the prior art there is provided a kind of reference voltage not equipotentiality in the case of can guarantee that Every group of chip cascade communication control unit of calculation power plate of the adjacent interface proper communication for calculating power chipset.
To achieve these goals, the utility model provides a kind of every group of chip cascade communication control unit of power plate of calculating and included Previous stage calculates power chip, rear stage and calculates power chip, at least one diode and at least one pull-up resistor.Rear stage calculates power chip Structure is identical with previous stage calculation power chip and is in series with previous stage calculation power chip, and serial communication is carried out between the two.At least one Individual diodes in reverse series is calculated power chip in previous stage and calculated to rear stage on the communication line of power chip transmission signal.At least one The communication line that pull-up resistor calculates power chip to rear stage calculation power chip transmission signal with previous stage respectively is connected.
In the embodiment of the utility model one, calculating every group of chip cascade communication control unit of power plate also includes multiple electric capacity, Multiple electric capacity are connected in parallel on the two ends of multiple diodes correspondingly.
In the embodiment of the utility model one, previous stage calculates power chip and calculates the order wire that power chip transmits signal to rear stage Road has three, respectively communication clock signals communication line, data signal communication line road and CORE clock signal communication lines road, Calculating every group of chip cascade communication control unit of power plate includes setting three pull-up resistors on three communication lines respectively.
In the embodiment of the utility model one, the voltage being connected with pull-up resistor is equal to the interface that rear stage calculates power chip Voltage.
In the embodiment of the utility model one, the quantity of diode is multiple, and differential concatenation calculates power core in previous stage respectively Piece and rear stage calculate the communication line phase of transmission signal between power chip;
In the embodiment of the utility model one, calculating every group of chip cascade communication control unit of power plate also includes under at least one Pull-up resistor, the communication line that at least one pull down resistor calculates power chip to previous stage calculation power chip transmission signal with rear stage is connected Connect.
In the embodiment of the utility model one, the voltage being connected with pull down resistor is equal to the reference that previous stage calculates power chip Ground voltage.
In the embodiment of the utility model one, the multiple diode is Schottky diode.
In summary, every group of chip cascade communication control unit of calculation power plate that the utility model is provided in previous stage by calculating Power chip is calculated power chip and transmitted to rear stage increases a differential concatenation diode and one on each communication line of signal Pull-up resistor, when previous stage, which calculates power chip, calculates power chip output high level to rear stage, diode reverse cut-off, pull-up resistor Signal is pulled to high level, rear stage calculates power chip and receives high level, and when previous stage calculates power chip output low level, Diode current flow, rear stage calculates power chip and receives low level, is realized just in the case of reference potential is unequal between the two Normal open is believed.
For above and other objects, features and advantages of the present utility model can be become apparent, preferable reality cited below particularly Example is applied, and coordinates accompanying drawing, is described in detail below.
Brief description of the drawings
Fig. 1 show the circuit of calculation every group of chip cascade communication control unit of power plate of the embodiment of the utility model one offer Schematic diagram.
Embodiment
In traditional calculation power plate, identical voltage is present between the power supply mode of series connection to calculate every group of chip of power plate The electrical potential difference of equivalent, the electrical potential difference will cause the logical value that rear stage calculates power chip to make a mistake, so as to cause every group of chip Between can not proper communication.In view of this, the utility model provides one kind and remains to realize in the case of reference potential is unequal Every group of chip cascade communication control unit of calculation power plate of proper communication.
As shown in figure 1, every group of chip cascade communication control unit of calculation power plate that the present embodiment is provided, which includes previous stage, calculates power Chip 1, rear stage calculate power chip 2, at least one diode 3 and at least one pull-up resistor 4.Rear stage calculates the structure of power chip 2 Power chip 1 is calculated with previous stage identical and calculate power chip 1 with previous stage and be in series, serial communication is carried out between the two.At least one The differential concatenation of diode 2 is calculated power chip 1 in previous stage and calculated to rear stage on the communication line of the transmission signal of power chip 2.At least one The communication line that individual pull-up resistor 4 calculates power chip 1 to the transmission signal of rear stage calculation power chip 2 with previous stage respectively is connected.
In Fig. 1, VDDn is the CORE voltages that previous stage calculates power chip, and VDDIOn is the interface electricity that previous stage calculates power chip Pressure, VDDn-1 is the reference ground voltage that previous stage calculates power chip;VDDn+1 is the CORE voltages that rear stage calculates power chip, VDDIO N+1 is the interface voltage that rear stage calculates power chip.
Every group of chip cascade communication control unit previous stage of calculation power plate that the present embodiment is provided is calculated power chip 1 and calculated to rear stage The communication line of the transmission signal of power chip 2 has three, respectively communication clock signals communication line, (in Fig. 1 marked as SCK), data signal communication line road (marked as DO in Fig. 1) and CORE clock signal communication lines road (marked as XCK in Fig. 1), after One-level calculation power chip 2 calculates power chip to previous stage and transmits the communication line of signal for one (marked as D1 in Fig. 1).In this implementation In example, diode 3 is additionally arranged at rear stage calculation power chip 2 and calculated to previous stage on the communication line D1 of power chip transmission signal.Therefore The quantity of diode 3 is four, and the quantity of pull-up resistor 4 is three.However, the utility model is not limited in any way to this.With The voltage that pull-up resistor 4 is connected is equal to the interface voltage that rear stage calculates power chip 2.
Every group of chip cascade communication control unit of calculation power plate that the utility model is provided by previous stage calculate power chip 1 to Rear stage calculates power chip 2 and transmits one differential concatenation diode 3 of increase and a pull-up resistor on three communication lines of signal 4, when previous stage, which calculates power chip 1, exports high level signal, diode 3 reversely ends, and rear stage is calculated power chip 2 by pull-up resistor Interface signal be pulled to high level;And when previous stage calculates power chip 1 and exports low level signal, diode forward conducting, after One-level calculates power chip 2 and receives low level signal, and both realize proper communication.In actual use, for cause rear stage calculate power Chip 2, which can accurately receive low level signal requirement diode, has faster response speed, it is preferred that set diode 3 be Schottky diode.However, the utility model is not limited in any way to this.
When rear stage, which calculates power chip 2, calculates power 1 output signal of chip to previous stage, for ensure the accuracy of data communication with And the uniformity of circuit, equally calculate power chip 2 in rear stage and calculated to previous stage increases on the communication line of the output signal of power chip 1 The diode of differential concatenation, now no matter it is high level or low level that rear stage, which calculates the output of power chip, previous stage calculates power chip The signal received is respectively provided with the positive pressure difference of a diode.Further to improve the accuracy of data transfer, in this implementation In example, set and calculate every group of chip cascade communication control unit of power plate also including calculating power core to previous stage with rear stage calculation power chip 2 The pull down resistor 5 that the communication line of the transmission signal of piece 1 is connected, the voltage being connected with pull down resistor 5 is equal to previous stage Calculate the reference ground voltage of power chip 1.However, the utility model is not limited in any way to this.In other embodiments, work as rear stage When the communication line that calculation power chip 2 calculates the transmission signal of power chip 1 to previous stage has a plurality of, the quantity of corresponding pull down resistor 5 Also to be multiple.When rear stage, which calculates power chip 2, exports low level, no matter whether diode 3 turns on, pull down resistor 5 will output The signal for calculating power chip 1 to previous stage pulls down to the reference ground (receive for low level signal) that previous stage calculates power chip 1.On The setting of pull-up resistor 4 and pull down resistor 5 increases the amplitude of oscillation of voltage, improves the logic fault-tolerant ability of chip.
In the present embodiment, to eliminate the vibration of the reverse charging electric charge of diode 3, influence of the noise to signal is reduced, is calculated Every group of chip cascade communication control unit of power plate also includes multiple electric capacity 6, and multiple electric capacity 6 are connected in parallel on multiple two poles correspondingly The two ends of pipe 3.In the present embodiment, calculating every group of chip cascade communication control unit of power plate includes being connected in parallel on four 3 liang of diodes Four electric capacity 6 at end.However, the utility model is not limited in any way to this.
In summary, every group of chip cascade communication control unit of calculation power plate that the utility model is provided in previous stage by calculating Power chip is calculated power chip and transmitted to rear stage increases a differential concatenation diode and one on each communication line of signal Pull-up resistor, when previous stage, which calculates power chip, calculates power chip output high level to rear stage, diode reverse cut-off, pull-up resistor Signal is pulled to high level, rear stage calculates power chip and receives high level, and when previous stage calculates power chip output low level, Diode current flow, rear stage calculates power chip and receives low level, is realized just in the case of reference potential is unequal between the two Normal open is believed.
Although the utility model is disclosed above by preferred embodiment, but the utility model is not limited to, it is any Know this those skilled in the art, do not departing from spirit and scope of the present utility model, a little change and retouching, therefore this practicality can be made New protection domain is worked as to be defined depending on claims scope claimed.

Claims (8)

1. one kind calculates every group of chip cascade communication control unit of power plate, it is characterised in that including:
Previous stage calculates power chip;
Rear stage calculates power chip, and structure is identical with previous stage calculation power chip and is in series with previous stage calculation power chip, between the two Carry out serial communication;
At least one diode, differential concatenation calculates the communication line that power chip calculates power chip transmission signal to rear stage in previous stage On;
At least one pull-up resistor, calculates power chip with previous stage respectively and calculates the communication line phase that power chip transmits signal to rear stage Connection.
2. calculation every group of chip cascade communication control unit of power plate according to claim 1, it is characterised in that the calculation power plate Every group of chip cascade communication control unit also includes multiple electric capacity, and the multiple electric capacity is connected in parallel on multiple diodes correspondingly Two ends.
3. calculation every group of chip cascade communication control unit of power plate according to claim 1, it is characterised in that previous stage calculates power The communication line that chip calculates power chip transmission signal to rear stage has three, respectively communication clock signals communication line, number It is believed that signal communication circuit and CORE clock signal communication lines road, calculating every group of chip cascade communication control unit of power plate includes setting respectively Put three pull-up resistors on three communication lines.
4. calculation every group of chip cascade communication control unit of power plate according to claim 3, it is characterised in that with pull-up resistor The voltage being connected is equal to the interface voltage that rear stage calculates power chip.
5. calculation every group of chip cascade communication control unit of power plate according to claim 1, it is characterised in that the number of diode Measure as multiple, the communication line of difference differential concatenation transmission signal between previous stage calculates power chip and rear stage calculates power chip Between.
6. calculation every group of chip cascade communication control unit of power plate according to claim 1, it is characterised in that the calculation power plate Every group of chip cascade communication control unit also includes at least one pull down resistor, and at least one described pull down resistor is calculated with rear stage The communication line that power chip calculates power chip transmission signal to previous stage is connected.
7. calculation every group of chip cascade communication control unit of power plate according to claim 1, it is characterised in that with pull down resistor The voltage being connected is equal to the reference ground voltage that previous stage calculates power chip.
8. calculation every group of chip cascade communication control unit of power plate according to claim 1, it is characterised in that the diode For Schottky diode.
CN201720180956.3U 2017-02-27 2017-02-27 Calculate every group of chip cascade communication control unit of power plate Active CN206557766U (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109932964A (en) * 2019-04-13 2019-06-25 上海亿算科技有限公司 A kind of calculation power chip and calculation power chip system of connecting
CN109992081A (en) * 2019-04-04 2019-07-09 杭州嘉楠耘智信息科技有限公司 Computing device and computer server
WO2024083240A1 (en) * 2022-10-20 2024-04-25 上海嘉楠捷思信息技术有限公司 Signal transmission circuit, circuit board, and electronic device
CN109992081B (en) * 2019-04-04 2024-06-07 杭州嘉楠耘智信息科技有限公司 Computing device and computer server

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109992081A (en) * 2019-04-04 2019-07-09 杭州嘉楠耘智信息科技有限公司 Computing device and computer server
CN109992081B (en) * 2019-04-04 2024-06-07 杭州嘉楠耘智信息科技有限公司 Computing device and computer server
CN109932964A (en) * 2019-04-13 2019-06-25 上海亿算科技有限公司 A kind of calculation power chip and calculation power chip system of connecting
WO2024083240A1 (en) * 2022-10-20 2024-04-25 上海嘉楠捷思信息技术有限公司 Signal transmission circuit, circuit board, and electronic device

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Address after: Yuhang District Linping Street South River Road Hangzhou City, Zhejiang province 311100 No. 5 Building 7

Patentee after: Zhejiang billion state communications technology Co., Ltd.

Address before: Hangzhou City, Zhejiang province 310000 Moganshan Road No. 1418-36

Patentee before: Zhejiang E-BANG communication Science and Technology Co., Ltd.

CP03 Change of name, title or address