CN107947566A - Series-fed circuit, method and computing device - Google Patents

Series-fed circuit, method and computing device Download PDF

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Publication number
CN107947566A
CN107947566A CN201711402437.8A CN201711402437A CN107947566A CN 107947566 A CN107947566 A CN 107947566A CN 201711402437 A CN201711402437 A CN 201711402437A CN 107947566 A CN107947566 A CN 107947566A
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CN
China
Prior art keywords
chip
powered
voltage
series
terminal
Prior art date
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Pending
Application number
CN201711402437.8A
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Chinese (zh)
Inventor
常鑫
陈文杰
詹克团
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Beijing Bitmain Technology Co Ltd
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Beijing Bitmain Technology Co Ltd
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Application filed by Beijing Bitmain Technology Co Ltd filed Critical Beijing Bitmain Technology Co Ltd
Priority to CN201711402437.8A priority Critical patent/CN107947566A/en
Publication of CN107947566A publication Critical patent/CN107947566A/en
Priority to PCT/CN2018/122793 priority patent/WO2019120295A1/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

The embodiment of the invention discloses a kind of series-fed circuit, method and computing device.The series-fed circuit carries out at least two groups of chipsets to be powered the series-fed of main operating voltage, at the same time using main operating voltage in series chip path voltage difference be chip in Auxiliary Functioning Unit progress partial pressure power supply, and by voltage clamp circuit by main stable operating voltage between chipset in fixed value.The embodiment of the present invention both ensure that the operating voltage uniformity on each chip, add chip operation performance, while improve power supply conversion efficiency, simplifies power supply lines, saves device cost.

Description

Series-fed circuit, method and computing device
Technical field
The present invention relates to the power supply power supply technique of IC chip, more particularly to a kind of series-fed circuit, method And computing device.
Background technology
With cloud computing and the large-scale calculations sustained and rapid development of server rank, and the whole world is to environmental protection and section The lifting that can be realized, energy use efficiency become a very important index in hardware counting system.
Being currently based on the computing device of large scale integrated circuit, there are electric current is excessive, the energy using conventional parallel power supply structure The significant drawbacks such as service efficiency is low, and add the cost of requirement and the production design of chip circuit design.With semiconductor The development of technique, the working power voltage of integrated circuit (IC) chip is more and more lower, and operating current is increasing, in order to maximize The transfer efficiency of power supply, the prior art begin to take on the power supply mode of chip-in series, i.e., multigroup core on printed circuit board (PCB) (PCB) Piece forms the voltage domain of plural serial stage by the way of being serially connected between power input and ground terminal.This series connection supplies Electric framework can effectively reduce circuit bulk supply electric current, improve power supply conversion efficiency, and can reduce power supply converter section The cost of parallel circuit device.
But existing IC chip there is also some problems using this series-fed framework.On the one hand, existing series connection Outer power voltage VCC is converted to output voltage VDD by DC-DC power module and is supplied to the IC chip of series connection by power supply circuit Electricity, but the internal resistance of each chip is not completely the same, the internal resistance difference of each chip can cause to supply each chip Operating voltage is inconsistent, therefore, to ensure that all chips can work normally, generally requires to heighten output voltage VDD to ensure The operating voltage of all chips of series connection is attained by normal working voltage, when the number of chips of series connection is more, is added in each core The voltage uniformity at piece both ends is poorer, to ensure that it is higher that all chips can work normally required output voltage VDD, This overall power that can cause power supply circuit becomes larger, and reduces power supply conversion efficiency.On the other hand, IC chip necessary not only for Arithmetic element and/or storage unit are powered, it is also necessary to which other functional components such as I/O components, PLL phase-locked loops are carried out Power supply, the required operating voltage of these components is often different, these components are carried out with extra power supply power supply can increase power supply The line layout and device cost of circuit, can also reduce the power supply conversion efficiency of circuit entirety.
Therefore, it is necessary to a kind of series-fed scheme of new optimization is designed, to reduce the IC chip to series connection Overall supply current, lifts power supply conversion efficiency, simplifies wiring, reduces circuit devcie cost.
The content of the invention
To solve the above-mentioned problems, the present invention proposes a kind of series-fed circuit, method and computing device.
According to an aspect of the invention, it is proposed that a kind of series-fed circuit, including：
At least two groups of chipsets being connected in series, each chipset include the chip to be powered of m series connection, each wait to supply Electrical chip has main operating voltage input terminal, back work voltage input end and a ground terminal, and described at least two groups are connected in series Chipset carries out series-fed, DC-DC power source input terminal connection externally fed end, DC- between DC-DC power source output terminal and ground The main operating voltage input terminal of the highest chip to be powered of D/C power output terminal connection, ground terminal per level-one chip to be powered with The main operating voltage input terminal of next stage chip to be powered is connected, so as to be to be powered per level-one via main operating voltage input terminal Chip provides main operating voltage respectively；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal point per level-one Auxiliary Power Units The ground terminal of the chip to be powered of peer is not connected to, and the to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units The back work voltage input end of chip, the input terminal of wherein at least level-one Auxiliary Power Units are connected to the progress of externally fed end Power supply, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to the corresponding series from highest chip to be powered down The main operating voltage input terminal of chip to be powered, so as to be carried via back work voltage input end for the chip to be powered connected For back work voltage.
In some embodiments, voltage clamp circuit, the voltage are connected between DC-DC power source output terminal and ground Clamping down on circuit includes at least one voltage output end, and the voltage output end is respectively connected to the main work between adjacent chips group Voltage input end, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed voltage；Wherein m is big In or equal to 1 integer.
In some embodiments, the series-fed circuit further includes booster circuit, the input terminal of the booster circuit Externally fed end is connected to, output terminal is connected to the input of Auxiliary Power Units corresponding with the superlative degree chip to be powered End.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered Enter end and PLL voltage input ends, include I/O power supply units and PLL power supply units, the I/ respectively per level-one Auxiliary Power Units The output terminal of O power supply units is connected to the I/O voltage input ends of the chip to be powered of peer, the output of the PLL power supply units End is connected to the PLL voltage input ends of the chip to be powered of peer；The ground terminal of the I/O power supply units and PLL power supply units It is respectively connected to the input of the ground terminal, wherein at least level-one I/O power supply units and PLL power supply units of the chip to be powered of peer End is connected to externally fed end and is powered, and the input terminal of remaining I/O power supply units and PLL power supply units at different levels is sequentially connected to From the main operating voltage input terminal of the chip to be powered of the corresponding series of highest chip to be powered down, so that respectively via I/ O voltage input ends and PLL voltage input ends provide I/O voltages and PLL voltages for the chip to be powered connected.
In some embodiments, the voltage clamp circuit includes voltage transformation module, voltage attenuation module, may be programmed Control module and drive module, the voltage transformation module are used to be converted to the input voltage of the DC-DC power source output terminal At least one output voltage, the voltage attenuation module are used to receive the input voltage and at least one output voltage, The programmable control module is inputted after being depressured respectively；The programmable control module is used at least one output Voltage carries out separate-blas estimation, and output pwm signal；The drive module is used to control the voltage to turn according to the pwm signal At least one output voltage for changing the mold block output is fixed voltage.
In some embodiments, one is connected between two chips to be powered adjacent in the series-fed circuit respectively A level conversion unit, the level conversion unit are used to carry out signal level turn between two chips to be powered being connected Change.
According to another aspect of the invention, it is proposed that a kind of series-fed circuit, including：
At least two groups of chipsets being connected in series, each chipset include at least two row chip to be powered in parallel, often Arranging chip to be powered includes the chip to be powered of m series connection, and each chip to be powered has main operating voltage input terminal, backman Make voltage input end and ground terminal, at least two groups of chipsets being connected in series between DC-DC power source output terminal and ground into Row series-fed, main the operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, DC-DC power source input terminal Externally fed end is connected, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection, is treated per level-one The ground terminal of power supply chip is connected with the main operating voltage input terminal of next stage chip to be powered, so that defeated via main operating voltage It is to provide main operating voltage respectively per level-one chip to be powered to enter end；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal point per level-one Auxiliary Power Units The ground terminal of the chip to be powered of peer is not connected to, and the to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units The back work voltage input end of chip, the input terminal of wherein at least level-one Auxiliary Power Units are connected to the progress of externally fed end Power supply, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to the corresponding series from highest chip to be powered down The main operating voltage input terminal of chip to be powered, so as to be carried via back work voltage input end for the chip to be powered connected For back work voltage.
In some embodiments, voltage clamp circuit, the voltage are connected between DC-DC power source output terminal and ground Clamping down on circuit includes at least one voltage output end, and the voltage output end is respectively connected to the main work between adjacent chips group Voltage input end, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed voltage；Wherein m is big In or equal to 1 integer.
In some embodiments, the series-fed circuit further includes booster circuit, the input terminal of the booster circuit Externally fed end is connected to, output terminal is connected to the input of Auxiliary Power Units corresponding with the superlative degree chip to be powered End.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered Enter end and PLL voltage input ends, include I/O power supply units and PLL power supply units, the I/ respectively per level-one Auxiliary Power Units The output terminal of O power supply units is connected to the I/O voltage input ends of the chip to be powered of peer, the output of the PLL power supply units End is connected to the PLL voltage input ends of the chip to be powered of peer；The ground terminal of the I/O power supply units and PLL power supply units It is respectively connected to the input of the ground terminal, wherein at least level-one I/O power supply units and PLL power supply units of the chip to be powered of peer End is connected to externally fed end and is powered, and the input terminal of remaining I/O power supply units and PLL power supply units at different levels is sequentially connected to From the main operating voltage input terminal of the chip to be powered of the corresponding series of highest chip to be powered down, so that respectively via I/ O voltage input ends and PLL voltage input ends provide I/O voltages and PLL voltages for the chip to be powered connected.
In some embodiments, the voltage clamp circuit includes voltage transformation module, voltage attenuation module, may be programmed Control module and drive module, the voltage transformation module are used to be converted to the input voltage of the DC-DC power source output terminal At least one output voltage, the voltage attenuation module are used to receive the input voltage and at least one output voltage, The programmable control module is inputted after being depressured respectively；The programmable control module is used at least one output Voltage carries out separate-blas estimation, and output pwm signal；The drive module is used to control the voltage to turn according to the pwm signal At least one output voltage for changing the mold block output is fixed voltage.
In some embodiments, one is connected between two chips to be powered adjacent in the series-fed circuit respectively A level conversion unit, the level conversion unit are used to carry out signal level turn between two chips to be powered being connected Change.
According to another aspect of the invention, it is proposed that a kind of series-fed method, for being at least two groups of cores being connected in series Piece group is powered, and each chipset includes the chip to be powered of m series connection, and each chip to be powered has main operating voltage Input terminal, back work voltage input end and ground terminal, this method include：
At least two groups of chipsets being connected in series are subjected to series-fed between DC-DC power source output terminal and ground, DC-DC power source input terminal connection externally fed end, the main operating voltage of the highest chip to be powered of DC-DC power source output terminal connection Input terminal, the ground terminal per level-one chip to be powered are connected with the main operating voltage input terminal of next stage chip to be powered, so that It is to provide main operating voltage respectively per level-one chip to be powered via main operating voltage input terminal；
The ground terminal for the Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to treating for peer The ground terminal of power supply chip, the back work electricity of the chip to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units Input terminal is pressed, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered, remaining is at different levels auxiliary Help power supply unit input terminal be sequentially connected to corresponding series from highest chip to be powered down chip to be powered master Operating voltage input terminal, so as to provide back work electricity via back work voltage input end for the chip to be powered connected Pressure.
In some embodiments, a voltage clamp circuit is connected between DC-DC power source output terminal and ground, by described in At least one voltage output end of voltage clamp circuit is respectively connected to the main operating voltage input terminal between adjacent chips group, is Main operating voltage input terminal between the adjacent chips group provides corresponding fixed voltage；Wherein m is whole more than or equal to 1 Number.
In some embodiments, the method is further included is connected to externally fed end by the input terminal of a booster circuit, Output terminal is connected to the input terminal of Auxiliary Power Units corresponding with the superlative degree chip to be powered.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered Enter end and PLL voltage input ends, include I/O power supply units and PLL power supply units, the I/ respectively per level-one Auxiliary Power Units The output terminal of O power supply units is connected to the I/O voltage input ends of the chip to be powered of peer, the output of the PLL power supply units End is connected to the PLL voltage input ends of the chip to be powered of peer；The ground terminal of the I/O power supply units and PLL power supply units It is respectively connected to the input of the ground terminal, wherein at least level-one I/O power supply units and PLL power supply units of the chip to be powered of peer End is connected to externally fed end and is powered, and the input terminal of remaining I/O power supply units and PLL power supply units at different levels is sequentially connected to From the main operating voltage input terminal of the chip to be powered of the corresponding series of highest chip to be powered down, so that respectively via I/ O voltage input ends and PLL voltage input ends provide I/O voltages and PLL voltages for the chip to be powered connected.
In some embodiments, the voltage clamp circuit includes voltage transformation module, voltage attenuation module, may be programmed Control module and drive module, the voltage transformation module are used to be converted to the input voltage of the DC-DC power source output terminal At least one output voltage, the voltage attenuation module are used to receive the input voltage and at least one output voltage, The programmable control module is inputted after being depressured respectively；The programmable control module is used at least one output Voltage carries out separate-blas estimation, and output pwm signal；The drive module is used to control the voltage to turn according to the pwm signal At least one output voltage for changing the mold block output is fixed voltage.
In some embodiments, the method is connected one respectively between being additionally included in two adjacent chips to be powered Level conversion unit, the level conversion unit are used to carry out signal level turn between two chips to be powered being connected Change.
According to another aspect of the invention, it is proposed that a kind of series-fed method, for being at least two groups of cores being connected in series Piece group is powered, and each chipset includes at least two row chip to be powered in parallel, and each column chip to be powered includes m string The chip to be powered of connection, each chip to be powered have main operating voltage input terminal, back work voltage input end and ground terminal, This method includes：
At least two groups of chipsets being connected in series are subjected to series-fed between DC-DC power source output terminal and ground, Main the operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, and the connection of DC-DC power source input terminal is exterior to supply Electric end, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection, per level-one chip to be powered Ground terminal is connected with the main operating voltage input terminal of next stage chip to be powered, so as to be each via main operating voltage input terminal Level chip to be powered provides main operating voltage respectively；
The ground terminal for the Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to treating for peer The ground terminal of power supply chip, the back work electricity of the chip to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units Input terminal is pressed, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered, remaining is at different levels auxiliary Help power supply unit input terminal be sequentially connected to corresponding series from highest chip to be powered down chip to be powered master Operating voltage input terminal, so as to provide back work electricity via back work voltage input end for the chip to be powered connected Pressure.
In some embodiments, a voltage clamp circuit is connected between DC-DC power source output terminal and ground, by described in At least one voltage output end of voltage clamp circuit is respectively connected to the main operating voltage input terminal between adjacent chips group, is Main operating voltage input terminal between the adjacent chips group provides corresponding fixed voltage；Wherein m is whole more than or equal to 1 Number.
In some embodiments, the method is further included is connected to externally fed end by the input terminal of a booster circuit, Output terminal is connected to the input terminal of Auxiliary Power Units corresponding with the superlative degree chip to be powered.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered Enter end and PLL voltage input ends, include I/O power supply units and PLL power supply units, the I/ respectively per level-one Auxiliary Power Units The output terminal of O power supply units is connected to the I/O voltage input ends of the chip to be powered of peer, the output of the PLL power supply units End is connected to the PLL voltage input ends of the chip to be powered of peer；The ground terminal of the I/O power supply units and PLL power supply units It is respectively connected to the input of the ground terminal, wherein at least level-one I/O power supply units and PLL power supply units of the chip to be powered of peer End is connected to externally fed end and is powered, and the input terminal of remaining I/O power supply units and PLL power supply units at different levels is sequentially connected to From the main operating voltage input terminal of the chip to be powered of the corresponding series of highest chip to be powered down, so that respectively via I/ O voltage input ends and PLL voltage input ends provide I/O voltages and PLL voltages for the chip to be powered connected.
In some embodiments, the voltage clamp circuit includes voltage transformation module, voltage attenuation module, may be programmed Control module and drive module, the voltage transformation module are used to be converted to the input voltage of the DC-DC power source output terminal At least one output voltage, the voltage attenuation module are used to receive the input voltage and at least one output voltage, The programmable control module is inputted after being depressured respectively；The programmable control module is used at least one output Voltage carries out separate-blas estimation, and output pwm signal；The drive module is used to control the voltage to turn according to the pwm signal At least one output voltage for changing the mold block output is fixed voltage.
In some embodiments, the method is connected one respectively between being additionally included in two adjacent chips to be powered Level conversion unit, the level conversion unit are used to carry out signal level turn between two chips to be powered being connected Change.
In accordance with a further aspect of the present invention, it is also proposed that a kind of computing device, the computing device include any of the above-described implementation The series-fed circuit of example.
It is miscellaneous function in chip that the embodiment of the present invention, which makes full use of the voltage difference of main operating voltage in series chip path, Component carries out partial pressure power supply, and carries out voltage between chipset using voltage clamp circuit and fix, so as to both ensure that Operating voltage uniformity on each chip, adds chip operation performance, while also improves power supply conversion efficiency, simplifies Power supply lines, save device cost.
Brief description of the drawings
Fig. 1 is the structure diagram of an embodiment of series-fed circuit of the present invention；
Fig. 2 is the structure diagram of the another embodiment of series-fed circuit of the present invention；
Fig. 3 is the structure diagram of the another embodiment of series-fed circuit of the present invention；
Fig. 4 is the structure diagram of an embodiment of level conversion unit in series-fed circuit of the present invention；
Fig. 5 is the structure diagram of an embodiment of voltage clamp circuit of the present invention；
Fig. 6 is the partial circuit schematic diagram of an embodiment of voltage clamp circuit of the present invention；
Fig. 7 is the flow diagram of an embodiment of series-fed method of the present invention；
Fig. 8 is the flow diagram of the another embodiment of series-fed method of the present invention；
Fig. 9 is the structure diagram of an embodiment of computing device of the present invention.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference Attached drawing, the present invention is described in more detail.
Fig. 1 is the structure diagram of an embodiment of series-fed circuit of the present invention.As shown in Figure 1, the present invention is real Applying the series-fed circuit of example includes at least two groups chipsets being connected in series (3 groups of chipsets are only schematically presented in Fig. 1), often A chipset includes the chip to be powered of m series connection, and each chip to be powered has main operating voltage input terminal, back work Voltage input end and ground terminal, at least two groups of chipsets being connected in series are between DC-DC power source output terminal and ground (VSS) Series-fed, DC-DC power source input terminal connection externally fed end (VCC) are carried out, the DC-DC power source output terminal connection superlative degree is waited to supply The main operating voltage input terminal of electrical chip, the main work electricity of ground terminal and next stage chip to be powered per level-one chip to be powered Pressure input terminal is connected, so as to be to provide main operating voltage respectively per level-one chip to be powered via main operating voltage input terminal；
The series-fed circuit further includes the Auxiliary Power Units with being correspondingly arranged per level-one chip to be powered, per level-one The ground terminal of Auxiliary Power Units is respectively connected to the ground terminal of the chip to be powered of peer, per the defeated of level-one Auxiliary Power Units Outlet is connected to the input of the back work voltage input end, wherein at least level-one Auxiliary Power Units of the chip to be powered of peer End is connected to externally fed end and is powered, and the input terminal of remaining Auxiliary Power Units at different levels is sequentially connected to wait to supply from the superlative degree The main operating voltage input terminal of the chip to be powered of the corresponding series of electrical chip down, so that via back work voltage input end Chip to be powered to be connected provides back work voltage.
In some embodiments, the series-fed circuit is additionally included between DC-DC power source output terminal and ground (VSS) The voltage clamp circuit being connected in parallel, the voltage clamp circuit include at least one voltage output end, the voltage output end The main operating voltage input terminal being respectively connected between adjacent chips group, the main operating voltage between the adjacent chips group are defeated Enter end and corresponding fixed voltage is provided.Wherein, m is the integer more than or equal to 1.
In some embodiments, (the i.e. feelings of m=2 exemplified by 2 series chips are included with 3 chipsets, each chipset Shape), the main operating voltage of each IC chip is generally 1.6V, and externally fed end VCC provides 12V DC voltage, and the present invention is implemented 12V DC voltage conversion is used as the master of the 6th grade of (superlative degree) chip to be powered by example by DC-DC power module for 9.6V first Operating voltage, it is assumed that the internal resistance of each chip is identical, then inputs to the magnitude of voltage of the main operating voltage input terminal of each chip Successively decrease successively, i.e. 9.6V, 8V, 6.4V, 4.8V, 3.2V, 1.6V, the balanced main work of 1.6V can be provided so on each chip Make voltage.
Secondly, the power supply for the special feature such as input and output I/O interfaces, PLL phase-locked loops in each chip comes Say, the embodiment of the present invention is powered by being correspondingly arranged an Auxiliary Power Units with chip at the same level, the work of accessory power supply Voltage is generally 6V or so, and more than the operating voltage 1.6V of each chip, for what preceding accessory power supply, it can be borrowed Externally fed voltage 12V is helped to be powered, and for what rear accessory power supply, it can be by the main work of what preceding chip Make voltage and carry out partial pressure power supply, so that ensure that each accessory power supply can input the operating voltage of 6V or so, it is each auxiliary to ensure Power supply is helped to work normally.For example, for the 5th grade and the 4th grade of accessory power supply, its input terminal is respectively connected to externally fed voltage 12V, thus the 5th grade and the 4th grade of accessory power supply can input the operating voltage of 12-6.4=5.6V and 12-4.8=7.2V respectively, Within the operating voltage range of permission；And for 3rd level accessory power supply, its power input accesses the main work of the 6th grade of chip Make voltage input end, so provide the voltage of 9.6V in the input terminal of the accessory power supply, and the ground terminal of the accessory power supply connects The main operating voltage 3.2V of 2nd grade of chip, therefore, can input the operating voltage of 9.6-3.2=6.4V on the accessory power supply； Similarly, for the 2nd grade of accessory power supply, its input terminal accesses the main operating voltage input terminal of the 5th grade of chip, so in auxiliary electricity The operating voltage of 8-1.6=6.4V is provided on source at the same time；And for the 6th grade of accessory power supply, due to externally fed voltage 12V with Enough voltage differences can not be formed between the ground connection terminal voltage 8V of 6th grade of accessory power supply, so needing extra one boosting of increase Circuit can also provide 12V boost in voltage to the operating voltage of 6V for 14V to ensure the accessory power supply, thus can guarantee that each auxiliary Power supply is helped to work normally.The advantages of this power supply mode is to improve power supply conversion efficiency, reduces circuit-line wiring, Device cost is saved.
Furthermore since the internal resistance of series-fed chip is not fully identical, when series chip increasing number, it can not ensure Operating voltage on each chip is completely the same, and the partial pressure power supply on accessory power supply will be further influenced in tandem paths The stability of the operating voltage of chip.The embodiment of the present invention by increase a voltage clamp circuit, adjacent chipset it Between be respectively connected to the fixed voltage of voltage clamp circuit output so that have input stable operating voltage between adjacent chipset Value, so as to ensure that the stable operating voltage inputted in this group of chip on each chip is balanced.For example, for above-mentioned 3 chips Group, each chipset include the example of 2 series chips, and voltage clamp circuit inputs 6.4V between adjacent chipset respectively With the fixed voltage of 3.2V, so that ensure that the operating voltage of 2 chips in each group can reach the burning voltage of 1.6V, carry The working performance of each chip of series connection is risen.
Voltage clamp circuit is only symbolically presented in Fig. 1 includes the embodiment of 2 voltage output ends, practical application In, the quantity of the voltage output end of voltage clamp circuit depends on the quantity of chipset, with ensure adjacent two groups of chip group it Between be all connected with the voltage output end of a voltage clamp circuit, this ensure that in every group of chip each chip operating voltage it is consistent Property.
Fig. 2 is the structure diagram of the another embodiment of series-fed circuit of the present invention.It is as shown in Fig. 2, of the invention The series-fed circuit of embodiment further expands to the chipset of each series connection more on the basis of embodiment illustrated in fig. 1 Mode in parallel is arranged, which includes：
At least two groups of chipsets being connected in series, each chipset include at least two row chip to be powered in parallel, often Arranging chip to be powered includes the chip to be powered of m series connection, and each chip to be powered has main operating voltage input terminal, backman Make voltage input end and ground terminal, at least two groups of chipsets being connected in series between DC-DC power source output terminal and ground into Row series-fed, main the operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, DC-DC power source input terminal Externally fed end is connected, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection, is treated per level-one The ground terminal of power supply chip is connected with the main operating voltage input terminal of next stage chip to be powered, so that defeated via main operating voltage It is to provide main operating voltage respectively per level-one chip to be powered to enter end；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal point per level-one Auxiliary Power Units The ground terminal of the chip to be powered of peer is not connected to, and the to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units The back work voltage input end of chip, the input terminal of wherein at least level-one Auxiliary Power Units are connected to the progress of externally fed end Power supply, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to the corresponding series from highest chip to be powered down The main operating voltage input terminal of chip to be powered, so as to be carried via back work voltage input end for the chip to be powered connected For back work voltage.
In some embodiments, voltage clamp circuit is connected in parallel between DC-DC power source output terminal and ground, it is described Voltage clamp circuit includes at least one voltage output end, and the voltage output end is respectively connected to the master between adjacent chips group Operating voltage input terminal, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed voltage；Wherein m For the integer more than or equal to 1.
Specifically, present embodiment is identical with Fig. 1 illustrated embodiments to the power supply mode of each chip, herein no longer Repeat.
Fig. 3 is the structure diagram of the another embodiment of series-fed circuit of the present invention.The way of example is in Fig. 1 Or on the basis of the embodiment of Fig. 2, Auxiliary Power Units are improved, i.e., it is each to be powered in described series-fed circuit The back work voltage input end of chip includes I/O voltage input ends and PLL voltage input ends, per level-one Auxiliary Power Units point Not Bao Kuo I/O power supply units and PLL power supply units, the output terminals of the I/O power supply units is connected to the chip to be powered of peer I/O voltage input ends, the output terminals of the PLL power supply units is connected to the PLL voltage input ends of the chip to be powered of peer； The ground terminal of the I/O power supply units and PLL power supply units is respectively connected to the ground terminal of the chip to be powered of peer, wherein extremely The input terminal of few level-one I/O power supply units and PLL power supply units is connected to externally fed end and is powered, remaining I/O electricity at different levels The input terminal of source unit and PLL power supply units is sequentially connected to the to be powered of the corresponding series from highest chip to be powered down The main operating voltage input terminal of chip, so as to wait to supply for what is connected via I/O voltage input ends and PLL voltage input ends respectively Electrical chip provides I/O voltages and PLL voltages.
Fig. 3 only symbolically presents the improvement on the basis of Fig. 2 illustrated embodiments, for Fig. 1 illustrated embodiments Improved procedure it is same.
The series-fed circuit of the embodiment of the present invention uses main operating voltage series-fed, due on the different chips of series connection The voltage domain of formation is of different sizes, and in order to ensure the signal communication between chip, the embodiment of the present invention is further adjacent two A level conversion unit is connected in series between a chip to be powered.Fig. 4 is level conversion list in series-fed circuit of the present invention The structure diagram of one embodiment of member.As shown in figure 4, the series-fed circuit of the embodiment of the present invention is in foregoing any reality On the basis of applying example, a level conversion unit, the level are connected in series respectively between two adjacent units to be powered Converting unit is used to carry out signal level conversion between two units to be powered being connected.
Specifically, level conversion unit for example can use capacitive couplings, differential signal transmission method and or diode Pressure decline method is realized.Each chip to be powered passes through the low to high signal level modular converter and upper one in level conversion unit respectively Chip to be powered connection in step voltage domain, by the high to Low signal level modular converter in signal level converting unit with Chip to be powered connection in voltage order one domain.Since the voltage domain formed on the different chips to be powered of series connection is of different sizes, Upper level voltage domain is higher than this step voltage domain, this step voltage domain is higher than next stage voltage domain again, to be powered per step voltage domain The signal that this grade of chip to be powered is sent is converted to upper level voltage domain by chip by low to high signal level modular converter Upper level chip to be powered is sent to after signal；Chip to be powered per step voltage domain passes through high to Low signal level modular converter Next stage chip to be powered is sent to after the signal that this grade of chip to be powered is sent is converted to the signal of next stage voltage domain, from And the signal communication between different voltages domain is realized between the chip to be powered of series connection.
Fig. 5 is the structure diagram of an embodiment of voltage clamp circuit in series-fed circuit of the present invention.Such as Fig. 5 Shown, the voltage clamp circuit of the embodiment of the present invention includes voltage transformation module 10, voltage attenuation module 20, programmable control molding Block 30, drive module 40.
Input voltage vin is carried out DC-DC conversions by voltage transformation module 10, is obtained at least one output voltage, is shown in Fig. 5 Illustrate to meaning property the situation of two output voltages Vout1 and Vout2.Voltage attenuation module 20 is respectively by two output voltages Vout1, Vout2 and input voltage vin carry out decompression decay, respectively obtain evanescent voltage signal AN0, AN1 and AN2, Ran Houfen Shu Ru not programmable control module 30.Programmable control module 30 carries out voltage according to AN0, AN1 and AN2 voltage signal of input Separate-blas estimation, so as to give driving mould according to result output pulse width modulation (PWM) the signal PWM1 and PWM2 that voltage deviation detects Block 40.The pwm signal that programmable control module 30 exports is respectively converted into voltage transformation module 10 and switchs by drive module 40 The drive signal of circuit, to control in voltage transformation module 10 on-off circuit on and off being boosted to output voltage or Decompression, so that it is guaranteed that the output voltage stabilization of voltage transformation module is in a fixed value.
In the embodiment of the present invention, programmable control module 30 can use MCU microcontrollers or other programmable logic device Such as FPGA realizes, its by programmable program code be adapted to different range input and output voltage separate-blas estimation and Voltage stabilizing controls, and without changing the structure of circuit, has stronger configurability and flexibility.
Fig. 6 is the circuit diagram of an embodiment of voltage transformation module 10 in voltage clamp circuit of the present invention.Such as Shown in Fig. 6, the voltage transformation module 10 of the embodiment of the present invention include mainly by two groups of metal-oxide-semiconductor field effect transistors MOS1, MOS2 and The on-off circuit of MOS3, MOS4 composition, the wherein source electrode of MOS1 are connected with the drain electrode of MOS2, the drain electrode of the source electrode and MOS4 of MOS3 It is connected, the source electrode ground connection of MOS2 and MOS4, input voltage vin input the drain electrode of MOS1 and the drain electrode of MOS3 respectively；The source of MOS1 Pole connects the source electrode of inductance L1, MOS3 with the drain electrode of MOS2 and the drain electrode of MOS4 connects inductance L2, the other end connection of inductance L1 The other end connection output voltage terminal Vout2 of output voltage terminal Vout1, inductance L2；Input voltage terminal Vin, output voltage terminal Multigroup shunt capacitance is passed sequentially through between Vout1, output voltage terminal Vout2 and ground GND to be connected in series, i.e. Input voltage terminal Capacitance C1-C4 is connected in parallel between Vin, output voltage terminal Vout1, between output voltage terminal Vout1, output voltage terminal Vout2 Capacitance C5-C8 is connected in parallel, capacitance C9-C12 is connected in parallel between output voltage terminal Vout2 and ground GND.The drain electrode of MOS1 and Connect a capacitance C14 between the source electrode of MOS2 between the drain electrode of series connection one capacitance C13, MOS3 and the source electrode of MOS3.
MOS1-MOS4 be based respectively on input grid drive signal DRVH1, DRVL1, DRVH2, DRVL2 turned on and Close.When programmable control module 30 detects that output voltage Vout1 is less than fixed value, output pulse width modulation (PWM) 1 is believed Number, drive signal DRVH1, DRVL1 are converted to through drive module 40, drive signal DRVH1, DRVL1 are used to control MOS1 respectively Conducting and MOS2 shut-offs so that form charge circuit in inductance L1, boost to output voltage Vout1；Work as PLC technology When module 30 detects that output voltage Vout1 is higher than fixed value, 1 signal of output pulse width modulation (PWM), through 40 turns of drive module Drive signal DRVH1, DRVL1 are changed to, drive signal DRVH1, DRVL1 are used to control MOS1 shut-offs and MOS2 conductings respectively, make Obtain in inductance L1 and form discharge loop, output voltage Vout1 is depressured.Similarly, when programmable control module 30 detects When output voltage Vout2 is below or above fixed value, its 2 signal of output pulse width modulation (PWM), is converted to through drive module 40 Drive signal DRVH2, DRVL2, drive signal DRVH2, DRVL2 are used to control MOS3 and MOS4 on or off respectively so that Charge or discharge circuit is formed in inductance L2, output voltage Vout2 is boosted or is depressured.
In the embodiment of the present invention, capacitance C1-C3, C5-C7, C9-C11 choose the resistance to voltage capacitances of 22uf/25V, C4, C8, C12 choosing High power capacity 470uf/16V, low-impedance electrolytic capacitor are taken, this parallel combination has lower impedance path, can play When voltage regulation filtering acts on, the output voltage ripple of Vout1, Vout2 are effectively reduced.
In the embodiment of the present invention, when the input voltage vin being powered to 3 series chip groups is 9.6V, voltage clamp Two output end vos ut1 and Vout2 of circuit processed connect the main operating voltage input terminal between adjacent chips group respectively, wherein Vout1 is connected between chipset 3 and chipset 2, and Vout2 is connected between chipset 2 and chipset 1, exports 6.4V respectively And 3.2V, so that the input terminal voltage of chipset 2 and chipset 1 is clamped down on the burning voltage in 6.4V and 3.2V, ensure that each The stable work in work of series chip.
Fig. 7 is the flow diagram of an embodiment of series-fed method of the present invention.As shown in fig. 7, the present invention is real The series-fed method for applying example is used to be that at least two groups of chipsets being connected in series are powered, and each chipset includes m The chip to be powered of series connection, each chip to be powered have main operating voltage input terminal, back work voltage input end and ground connection End, this method include：
At least two groups of chipsets being connected in series are carried out series connection confession by step S11 between DC-DC power source output terminal and ground Electricity, DC-DC power source input terminal connection externally fed end, the main work of the highest chip to be powered of DC-DC power source output terminal connection Voltage input end, the ground terminal per level-one chip to be powered are connected with the main operating voltage input terminal of next stage chip to be powered, So as to provide main operating voltage respectively per level-one chip to be powered via main operating voltage input terminal；
Step S12, the ground terminal for the Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to The ground terminal of chip to be powered at the same level, the auxiliary of chip to be powered at the same level is connected to per the output terminal of level-one Auxiliary Power Units Assistant engineer makees voltage input end, and the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered, its The input terminal of remaining Auxiliary Power Units at different levels is sequentially connected to the to be powered of the corresponding series from highest chip to be powered down The main operating voltage input terminal of chip, so as to provide auxiliary via back work voltage input end for the chip to be powered connected Operating voltage.
In some embodiments, the series-fed method further includes step：
A voltage clamp circuit is connected in parallel between DC-DC power source output terminal and ground, by the voltage clamp circuit At least one voltage output end be respectively connected to main operating voltage input terminal between adjacent chips group, be the adjacent chips Main operating voltage input terminal between group provides corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
In some embodiments, the series-fed method is further included is connected to outside by the input terminal of a booster circuit Feeder ear, output terminal are connected to the input terminal of Auxiliary Power Units corresponding with the superlative degree chip to be powered.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered Enter end and PLL voltage input ends, include I/O power supply units and PLL power supply units, the side respectively per level-one Auxiliary Power Units Method further comprises：The output terminal of the I/O power supply units is connected to the I/O voltage input ends of the chip to be powered of peer, The output terminal of the PLL power supply units is connected to the PLL voltage input ends of the chip to be powered of peer, by the I/O power supplys The ground terminal of unit and PLL power supply units is respectively connected to the ground terminal of the chip to be powered of peer, wherein at least level-one I/O electricity The input terminal of source unit and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL at different levels The input terminal of power supply unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down Make voltage input end, so as to be provided respectively via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected I/O voltages and PLL voltages.
In some embodiments, the embodiment of the voltage clamp circuit is as previously described.
In some embodiments, the series-fed method is additionally included between two adjacent chips to be powered respectively One level conversion unit of series connection, the embodiment of the level conversion unit is as previously described.
Fig. 8 is the flow diagram of an embodiment of series-fed method of the present invention.As shown in figure 8, the present invention is real The series-fed method for applying example is used to be that at least two groups of chipsets being connected in series are powered, and each chipset is included at least Two row chip to be powered in parallel, each column chip to be powered include the chip to be powered of m series connection, and each chip to be powered has Main operating voltage input terminal, back work voltage input end and ground terminal, this method include：
At least two groups of chipsets being connected in series are carried out series connection confession by step S21 between DC-DC power source output terminal and ground Electricity, main the operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, and the connection of DC-DC power source input terminal is exterior Feeder ear, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection, per level-one chip to be powered Ground terminal be connected with the main operating voltage input terminal of next stage chip to be powered, so as to be every via main operating voltage input terminal Level-one chip to be powered provides main operating voltage respectively；
Step S22, the ground terminal for the Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to The ground terminal of chip to be powered at the same level, the auxiliary of chip to be powered at the same level is connected to per the output terminal of level-one Auxiliary Power Units Assistant engineer makees voltage input end, and the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered, its The input terminal of remaining Auxiliary Power Units at different levels is sequentially connected to the to be powered of the corresponding series from highest chip to be powered down The main operating voltage input terminal of chip, so as to provide auxiliary via back work voltage input end for the chip to be powered connected Operating voltage.
In some embodiments, the series-fed method further includes step：
A voltage clamp circuit is connected in parallel between DC-DC power source output terminal and ground, by the voltage clamp circuit At least one voltage output end be respectively connected to main operating voltage input terminal between adjacent chips group, be the adjacent chips Main operating voltage input terminal between group provides corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
In some embodiments, the series-fed method is further included is connected to outside by the input terminal of a booster circuit Feeder ear, output terminal are connected to the input terminal of Auxiliary Power Units corresponding with the superlative degree chip to be powered.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered Enter end and PLL voltage input ends, include I/O power supply units and PLL power supply units, the side respectively per level-one Auxiliary Power Units Method further comprises：The output terminal of the I/O power supply units is connected to the I/O voltage input ends of the chip to be powered of peer, The output terminal of the PLL power supply units is connected to the PLL voltage input ends of the chip to be powered of peer, by the I/O power supplys The ground terminal of unit and PLL power supply units is respectively connected to the ground terminal of the chip to be powered of peer, wherein at least level-one I/O electricity The input terminal of source unit and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL at different levels The input terminal of power supply unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down Make voltage input end, so as to be provided respectively via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected I/O voltages and PLL voltages.
In some embodiments, the embodiment of the voltage clamp circuit is as previously described.
In some embodiments, the series-fed method is additionally included between two adjacent chips to be powered respectively One level conversion unit of series connection, the embodiment of the level conversion unit is as previously described.
Fig. 9 is the structure diagram of an embodiment of computing device of the present invention.As shown in figure 9, the embodiment of the present invention Computing device 100 include the series-fed circuit of foregoing any embodiment.
Particular embodiments described above, has carried out the purpose of the present invention, technical solution and beneficial effect further in detail Describe in detail it is bright, it should be understood that the foregoing is merely the present invention specific embodiment, be not intended to limit the invention, it is all Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done, should be included in the guarantor of the present invention Within the scope of shield.

Claims (25)

  1. A kind of 1. series-fed circuit, it is characterised in that including：
    At least two groups of chipsets being connected in series, each chipset include the chip to be powered of m series connection, each core to be powered Piece has main operating voltage input terminal, back work voltage input end and ground terminal, at least two groups of chips being connected in series Group carries out series-fed, DC-DC power source input terminal connection externally fed end, DC-DC electricity between DC-DC power source output terminal and ground The main operating voltage input terminal of the highest chip to be powered of source output terminal connection, ground terminal per level-one chip to be powered with it is next The main operating voltage input terminal of level chip to be powered is connected, so as to be per level-one chip to be powered via main operating voltage input terminal Main operating voltage is provided respectively；
    The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal per level-one Auxiliary Power Units connect respectively The ground terminal of the chip to be powered of peer is connected to, the chip to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units Back work voltage input end, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and supplied Electricity, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to treating for the corresponding series from highest chip to be powered down The main operating voltage input terminal of power supply chip, so as to be provided via back work voltage input end for the chip to be powered connected Back work voltage.
  2. 2. series-fed circuit according to claim 1, it is characterised in that connect between DC-DC power source output terminal and ground Voltage clamp circuit is connected to, the voltage clamp circuit includes at least one voltage output end, and the voltage output end connects respectively The main operating voltage input terminal being connected between adjacent chips group, the main operating voltage input terminal between the adjacent chips group carry For corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
  3. 3. series-fed circuit according to claim 1, it is characterised in that the series-fed circuit further includes boosting electricity Road, the input terminal of the booster circuit are connected to externally fed end, and output terminal is connected to and the superlative degree chip pair to be powered The input terminal for the Auxiliary Power Units answered.
  4. 4. series-fed circuit according to claim 1, it is characterised in that the back work voltage of each chip to be powered Input terminal includes I/O voltage input ends and PLL voltage input ends, includes I/O power supply units respectively per level-one Auxiliary Power Units With PLL power supply units, the output terminal of the I/O power supply units is connected to the I/O voltage input ends of the chip to be powered of peer, institute The output terminal for stating PLL power supply units is connected to the PLL voltage input ends of chip to be powered at the same level；The I/O power supply units and The ground terminal of PLL power supply units is respectively connected to the ground terminal of the chip to be powered of peer, wherein at least level-one I/O power supply units Externally fed end is connected to the input terminal of PLL power supply units to be powered, remaining I/O power supply units and PLL power supply list at different levels The input terminal of member is sequentially connected to the main operating voltage of the chip to be powered of the corresponding series from highest chip to be powered down Input terminal, so as to provide I/O electricity via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected respectively Pressure and PLL voltages.
  5. 5. series-fed circuit according to claim 2, it is characterised in that the voltage clamp circuit includes voltage conversion Module, voltage attenuation module, programmable control module and drive module, the voltage transformation module are used for DC-DC electricity The input voltage of source output terminal is converted at least one output voltage, and the voltage attenuation module is used to receive the input voltage With at least one output voltage, the programmable control module is inputted after being depressured respectively；The programmable control molding Block is used to carry out separate-blas estimation, and output pwm signal at least one output voltage；The drive module is used for according to institute It is fixed voltage to state pwm signal and control at least one output voltage of the voltage transformation module output.
  6. 6. series-fed circuit according to claim 4, it is characterised in that adjacent two in the series-fed circuit Connect respectively between chip to be powered a level conversion unit, the level conversion unit is used to wait to supply in two to be connected Signal level conversion is carried out between electrical chip.
  7. A kind of 7. series-fed circuit, it is characterised in that including：
    At least two groups of chipsets being connected in series, each chipset include at least two row chip to be powered in parallel, and each column is treated Power supply chip includes the chip to be powered of m series connection, and each chip to be powered has main operating voltage input terminal, back work electricity Pressure input terminal and ground terminal, at least two groups of chipsets being connected in series are gone here and there between DC-DC power source output terminal and ground Alliance electricity, main the operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, the connection of DC-DC power source input terminal Externally fed end, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection are to be powered per level-one The ground terminal of chip is connected with the main operating voltage input terminal of next stage chip to be powered, so that via main operating voltage input terminal Main operating voltage is provided respectively for every level-one chip to be powered；
    The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal per level-one Auxiliary Power Units connect respectively The ground terminal of the chip to be powered of peer is connected to, the chip to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units Back work voltage input end, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and supplied Electricity, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to treating for the corresponding series from highest chip to be powered down The main operating voltage input terminal of power supply chip, so as to be provided via back work voltage input end for the chip to be powered connected Back work voltage.
  8. 8. series-fed circuit according to claim 7, it is characterised in that connect between DC-DC power source output terminal and ground Voltage clamp circuit is connected to, the voltage clamp circuit includes at least one voltage output end, and the voltage output end connects respectively The main operating voltage input terminal being connected between adjacent chips group, the main operating voltage input terminal between the adjacent chips group carry For corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
  9. 9. series-fed circuit according to claim 7, it is characterised in that the series-fed circuit further includes boosting electricity Road, the input terminal of the booster circuit are connected to externally fed end, and output terminal is connected to and the superlative degree chip pair to be powered The input terminal for the Auxiliary Power Units answered.
  10. 10. series-fed circuit according to claim 7, it is characterised in that the back work electricity of each chip to be powered Pressure input terminal includes I/O voltage input ends and PLL voltage input ends, includes I/O power supply lists respectively per level-one Auxiliary Power Units Member and PLL power supply units, the output terminal of the I/O power supply units are connected to the I/O voltage input ends of the chip to be powered of peer, The output terminal of the PLL power supply units is connected to the PLL voltage input ends of the chip to be powered of peer；The I/O power supply units The ground terminal of the chip to be powered of peer, wherein at least level-one I/O power supplys list are respectively connected to the ground terminal of PLL power supply units The input terminal of member and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL power supplys at different levels The input terminal of unit is sequentially connected to the main work electricity of the chip to be powered of the corresponding series from highest chip to be powered down Input terminal is pressed, so as to provide I/O via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected respectively Voltage and PLL voltages.
  11. 11. series-fed circuit according to claim 7, it is characterised in that the voltage clamp circuit turns including voltage Block, voltage attenuation module, programmable control module and drive module are changed the mold, the voltage transformation module is used for the DC-DC The input voltage of power output end is converted at least one output voltage, and the voltage attenuation module is used to receive the input electricity Pressure and at least one output voltage, input the programmable control module after being depressured respectively；The PLC technology Module is used to carry out separate-blas estimation, and output pwm signal at least one output voltage；The drive module is used for basis It is fixed voltage that the pwm signal, which controls at least one output voltage of the voltage transformation module output,.
  12. 12. series-fed circuit according to claim 11, it is characterised in that adjacent two in the series-fed circuit Connect respectively between a chip to be powered a level conversion unit, the level conversion unit is used to treat in two to be connected Signal level conversion is carried out between power supply chip.
  13. 13. a kind of series-fed method, for being that at least two groups of chipsets being connected in series are powered, each chipset wraps Include the chip to be powered of m series connection, each chip to be powered have main operating voltage input terminal, back work voltage input end and Ground terminal, it is characterised in that this method includes：
    At least two groups of chipsets being connected in series are subjected to series-fed, DC-DC between DC-DC power source output terminal and ground Power input connection externally fed end, the main operating voltage input of the highest chip to be powered of DC-DC power source output terminal connection End, the ground terminal per level-one chip to be powered are connected with the main operating voltage input terminal of next stage chip to be powered, so that via Main operating voltage input terminal is to provide main operating voltage respectively per level-one chip to be powered；
    The ground terminal for the Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to the to be powered of peer The ground terminal of chip, the back work voltage that the chip to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units are defeated Enter end, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered, remaining auxiliary electricity at different levels The input terminal of source unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down Voltage input end, so as to provide back work voltage via back work voltage input end for the chip to be powered connected.
  14. 14. series-fed method according to claim 13, it is characterised in that between DC-DC power source output terminal and ground A voltage clamp circuit is connected, at least one voltage output end of the voltage clamp circuit is respectively connected to adjacent chips Main operating voltage input terminal between group, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed Voltage；Wherein m is the integer more than or equal to 1.
  15. 15. series-fed method according to claim 14, it is characterised in that the method is further included a booster circuit Input terminal be connected to externally fed end, output terminal is connected to Auxiliary Power Units corresponding with the superlative degree chip to be powered Input terminal.
  16. 16. series-fed method according to claim 14, it is characterised in that the backman of each chip to be powered Making voltage input end includes I/O voltage input ends and PLL voltage input ends, includes I/O electricity respectively per level-one Auxiliary Power Units Source unit and PLL power supply units, the I/O voltages that the output terminal of the I/O power supply units is connected to the chip to be powered of peer are defeated Enter end, the output terminal of the PLL power supply units is connected to the PLL voltage input ends of the chip to be powered of peer；The I/O power supplys The ground terminal of unit and PLL power supply units is respectively connected to the ground terminal of the chip to be powered of peer, wherein at least level-one I/O electricity The input terminal of source unit and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL at different levels The input terminal of power supply unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down Make voltage input end, so as to be provided respectively via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected I/O voltages and PLL voltages.
  17. 17. series-fed method according to claim 16, it is characterised in that the voltage clamp circuit turns including voltage Block, voltage attenuation module, programmable control module and drive module are changed the mold, the voltage transformation module is used for the DC-DC The input voltage of power output end is converted at least one output voltage, and the voltage attenuation module is used to receive the input electricity Pressure and at least one output voltage, input the programmable control module after being depressured respectively；The PLC technology Module is used to carry out separate-blas estimation, and output pwm signal at least one output voltage；The drive module is used for basis It is fixed voltage that the pwm signal, which controls at least one output voltage of the voltage transformation module output,.
  18. 18. series-fed method according to claim 17, it is characterised in that the method is additionally included in adjacent two Connect respectively between chip to be powered a level conversion unit, the level conversion unit is used to wait to supply in two to be connected Signal level conversion is carried out between electrical chip.
  19. 19. a kind of series-fed method, for being that at least two groups of chipsets being connected in series are powered, each chipset wraps At least two row chip to be powered in parallel is included, each column chip to be powered includes the chip to be powered of m series connection, each core to be powered Piece has main operating voltage input terminal, back work voltage input end and ground terminal, it is characterised in that this method includes：
    At least two groups of chipsets being connected in series are subjected to series-fed between DC-DC power source output terminal and ground, it is at the same level Main the operating voltage input terminal and ground terminal of chip to be powered are respectively connected with, DC-DC power source input terminal connection externally fed end, The main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection, per the ground connection of level-one chip to be powered End is connected with the main operating voltage input terminal of next stage chip to be powered, so as to be to be treated per level-one via main operating voltage input terminal Power supply chip provides main operating voltage respectively；
    The ground terminal for the Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to the to be powered of peer The ground terminal of chip, the back work voltage that the chip to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units are defeated Enter end, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered, remaining auxiliary electricity at different levels The input terminal of source unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down Voltage input end, so as to provide back work voltage via back work voltage input end for the chip to be powered connected.
  20. 20. series-fed method according to claim 19, it is characterised in that between DC-DC power source output terminal and ground A voltage clamp circuit is connected, at least one voltage output end of the voltage clamp circuit is respectively connected to adjacent chips Main operating voltage input terminal between group, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed Voltage；Wherein m is the integer more than or equal to 1.
  21. 21. series-fed method according to claim 19, it is characterised in that the method is further included a booster circuit Input terminal be connected to externally fed end, output terminal is connected to Auxiliary Power Units corresponding with the superlative degree chip to be powered Input terminal.
  22. 22. series-fed method according to claim 19, it is characterised in that the backman of each chip to be powered Making voltage input end includes I/O voltage input ends and PLL voltage input ends, includes I/O electricity respectively per level-one Auxiliary Power Units Source unit and PLL power supply units, the I/O voltages that the output terminal of the I/O power supply units is connected to the chip to be powered of peer are defeated Enter end, the output terminal of the PLL power supply units is connected to the PLL voltage input ends of the chip to be powered of peer；The I/O power supplys The ground terminal of unit and PLL power supply units is respectively connected to the ground terminal of the chip to be powered of peer, wherein at least level-one I/O electricity The input terminal of source unit and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL at different levels The input terminal of power supply unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down Make voltage input end, so as to be provided respectively via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected I/O voltages and PLL voltages.
  23. 23. series-fed method according to claim 22, it is characterised in that the voltage clamp circuit turns including voltage Block, voltage attenuation module, programmable control module and drive module are changed the mold, the voltage transformation module is used for the DC-DC The input voltage of power output end is converted at least one output voltage, and the voltage attenuation module is used to receive the input electricity Pressure and at least one output voltage, input the programmable control module after being depressured respectively；The PLC technology Module is used to carry out separate-blas estimation, and output pwm signal at least one output voltage；The drive module is used for basis It is fixed voltage that the pwm signal, which controls at least one output voltage of the voltage transformation module output,.
  24. 24. series-fed method according to claim 23, it is characterised in that the method is additionally included in adjacent two Connect respectively between chip to be powered a level conversion unit, the level conversion unit is used to wait to supply in two to be connected Signal level conversion is carried out between electrical chip.
  25. 25. a kind of computing device, it is characterised in that the computing device includes the series connection of claim 1-12 any one of them and supplies Circuit.
CN201711402437.8A 2017-12-21 2017-12-21 Series-fed circuit, method and computing device Pending CN107947566A (en)

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