CN209842553U - Chip series circuit and computing equipment - Google Patents
Chip series circuit and computing equipment Download PDFInfo
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- CN209842553U CN209842553U CN201920746174.0U CN201920746174U CN209842553U CN 209842553 U CN209842553 U CN 209842553U CN 201920746174 U CN201920746174 U CN 201920746174U CN 209842553 U CN209842553 U CN 209842553U
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Abstract
The utility model relates to a mains operated technical field just discloses a chip series circuit, include: n-stage chips connected in series; each stage of chip is provided with a main working voltage input end, a grounding end and an I/O voltage input end; the grounding end of the 1 st-level chip is grounded, the main working voltage input end of the nth-level chip is connected with a power supply, the main working voltage input end of the ith-level chip is connected with the grounding end of the (i + 1) th-level chip, and i belongs to [1, n ]; the I/O voltage input end of the j level chip is connected with the main working voltage input end of the j + m-1 level chip, wherein m is determined according to the main working voltage standard value and the I/O voltage standard value of the chip, and j belongs to [1, n-m +1 ]. According to the chip series circuit and the computing equipment, the efficiency loss between the pressure differences caused by the LDO voltage reduction is eliminated in the I/O power supply mode, and the power conversion efficiency of the product is improved.
Description
Technical Field
The utility model relates to a power supply technical field specifically is a chip series circuit and computing equipment.
Background
The special computer is a computing device based on a large-scale integrated circuit, the computational power chip is a core component of the special computer, and the performance of the chip determines the computing performance of the special computer. At present, a power supply mode of connecting chips in series is adopted on a traditional computational circuit board, namely, a plurality of groups of chips are connected in series, and a multi-stage series voltage domain is formed between a power supply input end and a grounding end.
In the prior art, an external power supply VIN supplies power to a plurality of chips connected in series, and since each chip has internal resistance, the chips connected in series form a power supply voltage division link. The number of chips is related to the voltage magnitude of VIN; because the internal resistances of the chips are very different, in an ideal state, the main working voltages of the chips are equal, and the main working voltages mainly supply power to an arithmetic unit and a storage unit in the chips; in the prior art, based on the requirement of design consistency, the same power supply voltage is usually used for conversion processing and then supplies power to I/O and PLL of different chips.
Each level of chip in the existing power supply link needs the LDO circuit to supply power for the I/O part and the PLL part, and the LDO circuit serving as an auxiliary power supply can bring about voltage drop, which brings about loss of power conversion efficiency; in addition, due to the existence of the LDO circuit, the PCBA of the computation circuit board is complex, the product performance is influenced, and the product cost is increased.
SUMMERY OF THE UTILITY MODEL
Technical problem to be solved
To prior art not enough, the utility model provides a chip series circuit and computing equipment possesses and has saved the efficiency loss between the pressure differential brought through LDO step-down, has promoted advantages such as power conversion efficiency of product, has solved that chips at different levels in the current supply link need the LDO circuit to supply power for IO part and PLL part, and the LDO circuit can bring the pressure drop as auxiliary power source itself, and this kind of pressure drop has brought the problem of power conversion efficiency's loss.
(II) technical scheme
For realize the aforesaid save the efficiency loss between the pressure differential that brings through LDO step-down, promoted purposes such as power conversion efficiency of product, the utility model provides a following technical scheme: a chip series circuit, comprising: n-stage chips connected in series; each stage of chip is provided with a main working voltage input end, a grounding end and an I/O voltage input end;
the grounding end of the 1 st-level chip is grounded, the main working voltage input end of the nth-level chip is connected with a power supply, the main working voltage input end of the ith-level chip is connected with the grounding end of the (i + 1) th-level chip, and i belongs to [1, n ];
the I/O voltage input end of the j level chip is connected with the main working voltage input end of the j + m-1 level chip, wherein m is determined according to the main working voltage standard value and the I/O voltage standard value of the chip, and j belongs to [1, n-m +1 ].
Preferably, the product of m and the standard value of the main working voltage is between the minimum standard value of the I/O voltage and the maximum standard value of the I/O voltage.
Preferably, each stage of chips further has a PLL voltage input terminal; the PLL voltage input end of each stage of chip is connected with the I/O voltage input end of each stage of chip through a voltage division circuit.
Preferably, the voltage at the I/O voltage input terminal of any one of the n-m +2 th to nth chips is provided through an auxiliary circuit.
Preferably, the auxiliary circuit is connected to a power supply, or the auxiliary circuit is connected to a power supply terminal other than the power supply.
Preferably, the auxiliary circuit is connected with the power supply through a booster circuit; the input end of the booster circuit is connected with a power supply, and the output end of the booster circuit is connected with the auxiliary circuit; wherein, the auxiliary circuit is an LDO circuit.
Preferably, the series circuit further includes: and the voltage regulating circuit is connected between the power supply and the ground terminal and is connected with the n-stage chip in parallel.
Preferably, the series circuit further includes: and the voltage regulating circuit is connected with the primary chip or the multi-stage chip in parallel.
Preferably, the voltage regulating circuit includes: a resistor and a capacitor connected in parallel.
According to a chip series circuit, a computing device is proposed, comprising a chip series circuit as described in any of the above.
(III) advantageous effects
Compared with the prior art, the utility model provides a chip series circuit and computing equipment possesses following beneficial effect: according to the chip series circuit and the computing equipment, the provided chip series circuit directly supplies power to the I/O voltage input ends of the previous stages by using the voltages of the main working voltage input ends of the next stages, and by adopting the I/O power supply mode, an LDO circuit does not need to be added into a power supply link of each I/O voltage input end, so that the difficulty of PCBA of the computing power circuit board is reduced, the product performance is improved, and the product cost is reduced; in addition, the I/O power supply mode saves efficiency loss between voltage differences caused by LDO voltage reduction, and improves the power conversion efficiency of products.
Drawings
FIG. 1 is a schematic diagram of a series connection of force computing chips in the prior art;
fig. 2 is a schematic diagram of the connection mode of the first several stages of chips according to an embodiment of the serial chip circuit of the present invention;
fig. 3 is a schematic diagram of the connection mode of the chips of the latter stages according to an embodiment of the serial chip circuit of the present invention;
fig. 4 is a schematic diagram of a connection mode of a partial-level chip according to another embodiment of the serial chip circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention and the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
A chip series circuit, comprising: n-stage chips connected in series; each stage of chip is provided with a main working voltage input end, a grounding end and an I/O voltage input end;
the grounding end of the 1 st-level chip is grounded, the main working voltage input end of the nth-level chip is connected with a power supply, the main working voltage input end of the ith-level chip is connected with the grounding end of the (i + 1) th-level chip, and i belongs to [1, n ];
the I/O voltage input end of the j level chip is connected with the main working voltage input end of the j + m-1 level chip, wherein m is determined according to the main working voltage standard value and the I/O voltage standard value of the chip, and j belongs to [1, n-m +1 ].
The utility model discloses in, the product of m and main operating voltage standard value is between IO voltage minimum standard value and IO voltage maximum standard value.
In the utility model, each stage of chip is also provided with a PLL voltage input end; the PLL voltage input end of each stage of chip is connected with the I/O voltage input end of each stage of chip through a voltage division circuit.
In the present invention, the voltage of the I/O voltage input terminal of any one of the n-m +2 th chip to the n-th chip is provided through the auxiliary circuit.
The utility model discloses in, auxiliary circuit is connected with power supply, perhaps auxiliary circuit with except that other feeder ear outside power supply is connected.
In the utility model, the auxiliary circuit is connected with the power supply through the booster circuit; the input end of the booster circuit is connected with a power supply, and the output end of the booster circuit is connected with the auxiliary circuit; wherein, the auxiliary circuit is an LDO circuit.
The utility model discloses in, series circuit still includes: and the voltage regulating circuit is connected between the power supply and the ground terminal and is connected with the n-stage chip in parallel.
The utility model discloses in, series circuit still includes: and the voltage regulating circuit is connected with the primary chip or the multi-stage chip in parallel.
The utility model discloses in, voltage regulation circuit includes: a resistor and a capacitor connected in parallel.
Example (b):
as shown in fig. 2, the chip series circuit includes: n-stage chips connected in series; an external power supply VIN supplies power to the n-level chip, so that the n-level chip forms a power supply voltage division link. Wherein each stage of chip has a main working voltage input terminal and a ground terminal. The grounding end of the 1 st-level chip is grounded, the main working voltage input end of the nth-level chip is connected with a power supply VIN, the main working voltage input end of the ith-level chip is connected with the grounding end of the (i + 1) th-level chip, and i belongs to [1, n ]. Taking the first 8-level chip shown in fig. 2 as an example, the ground terminal of the 1 st-level chip is grounded, the main working voltage input terminal of the 1 st-level chip is connected to the ground terminal of the 2 nd-level chip, the main working voltage input terminal of the 2 nd-level chip is connected to the ground terminal of the 3 rd-level chip, and so on.
The main operating voltage (core voltage) is mainly used for supplying power to the operation unit and the storage unit in the chip, and under an ideal state, the main operating voltages of the chip are equal. In this embodiment, the main operating voltage value of the chip in the ideal state is referred to as a main operating voltage standard value. Taking the standard value of the main working voltage of each chip as 0.45V as an example, the voltage value noted at the upper part of each chip in fig. 2 is the standard value of the voltage at the main working voltage input end of the chip. Therefore, the voltage standard value of the main working voltage input end of each stage of chip is increased by taking 0.45V as a voltage domain in the sequence from front to back.
In addition to the power supply for the arithmetic and memory units inside the chip, the power supply for the I/O components inside the chip is also required. Each chip also has an I/O voltage input end, and the I/O voltage value of the chip under an ideal state is called an I/O voltage standard value. This example will be described with reference to the I/O voltage standard value of 1.8V.
Based on the characteristics of the variation of the standard voltage values at the main working voltage input ends of the chips at different levels, the present embodiment directly supplies power to the I/O voltage input ends of the previous stages by using the voltage at the main working voltage input end of the next stage. Specifically, the I/O voltage input end of the j-th chip is connected with the main working voltage input end of the j + m-1 chip, namely, the voltage of the main working voltage input end of the j + m-1 chip is used for supplying power to the I/O voltage input end of the j-th chip. Here, m is determined from the main operating voltage standard value and the I/O voltage standard value of the chip, and j ∈ [1, n-m +1 ].
In this embodiment, the I/O voltage input terminal of the j-th chip is preferably directly connected to the main working voltage input terminal of the j + m-1-th chip.
In the practical application process, due to the influence of the chip manufacturing performance, the performance parameters of the chip are not necessarily ideal parameters, that is, the main operating voltage and the I/O voltage of the chip may float within a certain range of the standard value. For example, the main operating voltage of some chips is slightly lower than 0.45V, and the main operating voltage of some chips is slightly higher than 0.45V. In practice, when screening chips, quality control is performed according to the floating condition, and the floating of the chip really selected for use in the actual circuit is within the allowable floating range, for example, the main operating voltage is within ± 10%, i.e., the main operating voltage range of the chip is [0.45V-0.045V,0.45V +0.045V ].
Similarly, in practice, the I/O voltage of the chip is allowed to float within a certain range, specifically, the I/O voltage minimum standard value and the I/O voltage maximum standard value are set, and the I/O voltage of the chip is allowed to float between the I/O voltage minimum standard value and the I/O voltage maximum standard value. For example, the I/O voltage is floated by + -10%, i.e., the I/O voltage of the chip is floated in the range of [1.8V-0.18V,1.8V +0.18V ].
Because the main working voltage floating range of the chips is controllable during actual chip screening, if the chips with the main working voltage being the standard value cannot be screened completely, one group of chips with the main working voltage being lower than the standard value of the main working voltage can be selected, the other group of chips with the main working voltage being higher than the standard value of the main working voltage can be selected, and the serial connection sequence of the two groups of chips in the whole serial circuit is adjusted according to the conditions during serial connection, so that the voltage division of the final serial circuit can be kept balanced and consistent. That is, the effect of the main operating voltage floating of the chip is practically negligible.
Therefore, in this embodiment, m is determined according to: the product of m and the standard value of the main working voltage is between the minimum standard value of the I/O voltage and the maximum standard value of the I/O voltage. By utilizing the characteristic that the voltage standard value of the main working voltage input end of each stage of chip is increased by taking the main working voltage standard value as a voltage domain, a certain integral value of which the product with the main working voltage standard value is between the I/O voltage minimum standard value and the I/O voltage maximum standard value is determined as a value of m. In a specific example, the I/O voltage minimum criterion value is 1.8V-0.18V =1.62V, the I/O voltage maximum criterion value is 1.8V +0.18V =1.98V, and the integer value having a product of 0.45 between 1.62 and 1.98 is taken to be 4, i.e., m = 4. As can be seen in FIG. 2, the I/O voltage input of the level 1 chip is connected to the main operating voltage input of the level 4 chip, the I/O voltage input of the level 2 chip is connected to the main operating voltage input of the level 5 chip, the I/O voltage input of the level 3 chip is connected to the main operating voltage input of the level 6 chip, and so on. If some or some j-th-stage chip exists, the voltage value of the main working voltage input end of the corresponding j + m-1-stage chip exceeds the I/O voltage floating range, and aiming at the j + m-1-stage chip, an auxiliary circuit can be added into a connection link of the I/O voltage input end of the j + m-1-stage chip and the main working voltage input end of the j + m-1-stage chip for voltage drop so as to ensure the I/O normal working voltage of the j-1-stage chip.
The 1 st chip to the (n-m + 1) th chip in the series circuit can directly introduce the I/O voltage from the main working voltage input end of a certain stage of chip after each stage of chip. For the n-m +2 th chip to the nth chip, the voltage at the I/O voltage input end of any one of the chips needs to be provided through an auxiliary circuit.
In the example shown in fig. 3, the series circuit includes 24 stages of chips, wherein the 1 st to 21 st stages of chips may directly introduce an I/O voltage from the main operating voltage input terminal of a certain stage of chip after each stage of chip, while for the 22 nd to 24 th stages of chips, since the voltage difference between the present stage of chip and any subsequent stage of chip is not high enough, an I/O voltage needs to be introduced from the supply voltage VIN provided by the power supply. The supply voltage VIN is also the input voltage of the main operating voltage input terminal of the nth chip. In order to enable the voltage values of the I/O voltage input ends of the 22 nd-24 th chips to meet the requirements, an auxiliary circuit LDO needs to be added into the link, and further, in order to ensure the voltage difference of the LDO during normal operation, after VIN needs to be boosted, the VIN is fed back to the I/O voltage input ends of the 22 nd-24 th chips through the LDO. Namely, the voltage at the I/O voltage input end of the 22 nd-24 th chip is provided by the LDO, and the LDO is connected with the power supply through the booster circuit.
As another embodiment of the present invention, if the power supply voltage of the power supply is high enough, the auxiliary circuit connected to the I/O voltage input terminal of any one of the n-m +2 th chip to the n-th chip can be directly connected to the power supply without being connected to the power supply through the boost circuit. In this case, since the power supply of the power supply is high, the voltage can be divided appropriately by the voltage dividing circuit, and the divided voltage is used as the input voltage of the main operating voltage input terminal of the nth chip.
As another embodiment of the present invention, the auxiliary circuit connected to the I/O voltage input terminal of any one of the n-m +2 th chip to the n-th chip may be connected to a power supply terminal other than the power supply source, instead of the power supply source. For example, voltage is introduced from other power supply terminals of the circuit board including the chip series circuit to the auxiliary circuit, so that the auxiliary circuit performs voltage drop processing on the voltage and then supplies the voltage to the I/O voltage input terminal of any one of the (n-m + 2) th-stage chip to the nth-stage chip.
Furthermore, each stage of chip also has a PLL voltage input end, and the PLL voltage input end of each stage of chip is connected with the I/O voltage input end of each stage of chip through a voltage division circuit. Generally, the supply voltage at the voltage input of the PLL is smaller than the supply voltage at the voltage input of the I/O, and the supply voltage at the voltage input of the I/O can be divided by the voltage divider circuit and then provided to the voltage input of the PLL.
The chip series circuit provided by the embodiment directly supplies power to the I/O voltage input ends of the previous stages by using the voltage of the main working voltage input ends of the next stages, and by adopting the I/O power supply mode, an LDO circuit does not need to be added in a power supply link of each I/O voltage input end, so that the difficulty of PCBA of the computational power circuit board is reduced, the product performance is improved, and the product cost is reduced. In addition, the I/O power supply mode saves efficiency loss between voltage differences caused by LDO voltage reduction, and improves the power conversion efficiency of products.
In the above embodiments shown in fig. 2 and 3, each stage of chips connected in series is illustrated by taking one chip as an example. In another embodiment of the present invention, any one or any plurality of the n-level chips may include a plurality of chips connected in parallel. For a plurality of chips whose main operating voltage is not an ideal value, some chips may be connected in parallel as one of the n-level chips. After parallel connection, the main working voltage of the primary chip is more towards an ideal value, and therefore the primary chip is more consistent.
Furthermore, in order to make the main working voltages of the chips at each stage in the power supply voltage division link more consistent, a voltage regulating circuit can be added in the series circuit. Fig. 4 is a schematic diagram illustrating a connection mode of a partial-level chip according to another embodiment of the serial circuit of chips provided by the present invention. As shown in fig. 4, the present embodiment further adds two voltage regulating circuits on the basis of the above embodiments. One of the voltage regulating circuits is connected with the 21 st-level chip and the 22 nd-level chip after being connected in parallel, and the other voltage regulating circuit is connected with the 23 rd-level chip and the 24 th-level chip after being connected in parallel. The voltage regulating circuit comprises a circuit and a capacitor which are connected in parallel, and the voltage regulating circuit is connected in parallel in the two-stage chip to play a role in voltage equalization and filtering.
Optionally, the present invention may also have a voltage regulating circuit connected in parallel in any of the chips. The voltage regulating circuit is connected in parallel to the chips at which level or the chips which are not good enough in main working voltage consistency. The designer can arbitrarily select the chip with poor consistency of the main working voltage to connect the voltage regulating circuit in parallel.
Optionally, the utility model discloses also can increase the voltage regulation circuit parallelly connected with n grades of chips between power supply and earthing terminal, also can keep supplying power the uniformity of the partial pressure of chips at different levels in the partial pressure link.
The utility model also provides a computing device, this computing device includes the chip series circuit that any above-mentioned embodiment described. Alternatively, the computing device may be a special purpose computer.
According to the chip series circuit and the computing equipment, the provided chip series circuit directly supplies power to the I/O voltage input ends of the previous stages by using the voltages of the main working voltage input ends of the next stages, and by adopting the I/O power supply mode, an LDO circuit does not need to be added into a power supply link of each I/O voltage input end, so that the difficulty of PCBA of the computing power circuit board is reduced, the product performance is improved, and the product cost is reduced; in addition, the I/O power supply mode saves efficiency loss between voltage differences caused by LDO voltage reduction, and improves the power conversion efficiency of products.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A chip series circuit, comprising: n-stage chips connected in series; each stage of chip is provided with a main working voltage input end, a grounding end and an I/O voltage input end;
the grounding end of the 1 st-level chip is grounded, the main working voltage input end of the nth-level chip is connected with a power supply, the main working voltage input end of the ith-level chip is connected with the grounding end of the (i + 1) th-level chip, and i belongs to [1, n ];
the I/O voltage input end of the j level chip is connected with the main working voltage input end of the j + m-1 level chip, wherein m is determined according to the main working voltage standard value and the I/O voltage standard value of the chip, and j belongs to [1, n-m +1 ].
2. The chip series circuit according to claim 1, wherein the product of m and the main operating voltage standard value is between the I/O voltage minimum standard value and the I/O voltage maximum standard value.
3. The chip series circuit of claim 1, wherein each stage of chips further has a PLL voltage input; the PLL voltage input end of each stage of chip is connected with the I/O voltage input end of each stage of chip through a voltage division circuit.
4. The chip series circuit according to any one of claims 1 to 3, wherein the voltage at the I/O voltage input terminal of any one of the n-m +2 th-order chip to the n-th-order chip is provided by an auxiliary circuit.
5. The chip series circuit according to claim 4, wherein the auxiliary circuit is connected to a power supply, or the auxiliary circuit is connected to a power supply terminal other than the power supply.
6. The chip series circuit according to claim 5, wherein the auxiliary circuit is connected to a power supply through a boost circuit; the input end of the booster circuit is connected with a power supply, and the output end of the booster circuit is connected with the auxiliary circuit; wherein, the auxiliary circuit is an LDO circuit.
7. The chip series circuit of claim 1, wherein the series circuit further comprises: and the voltage regulating circuit is connected between the power supply and the ground terminal and is connected with the n-stage chip in parallel.
8. The chip series circuit of claim 1, wherein the series circuit further comprises: and the voltage regulating circuit is connected with the primary chip or the multi-stage chip in parallel.
9. The chip series circuit according to claim 7 or 8, wherein the voltage regulating circuit comprises: a resistor and a capacitor connected in parallel.
10. A computing device comprising a chip series circuit as claimed in any one of claims 1 to 9.
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| CN201920746174.0U CN209842553U (en) | 2019-05-23 | 2019-05-23 | Chip series circuit and computing equipment |
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| CN201920746174.0U CN209842553U (en) | 2019-05-23 | 2019-05-23 | Chip series circuit and computing equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112073083A (en) * | 2020-08-21 | 2020-12-11 | 南京矽力微电子技术有限公司 | Multi-chip integrated circuit and interactive communication method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112073083A (en) * | 2020-08-21 | 2020-12-11 | 南京矽力微电子技术有限公司 | Multi-chip integrated circuit and interactive communication method thereof |
| CN112073083B (en) * | 2020-08-21 | 2022-03-25 | 南京矽力微电子技术有限公司 | Multi-chip integrated circuit and interactive communication method thereof |
| US11601154B2 (en) | 2020-08-21 | 2023-03-07 | Silergy Semiconductor Technology (Hangzhou) Ltd | Multi-chip integrated circuit and interactive communication method for the same |
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Effective date of registration: 20220531 Granted publication date: 20191224 |