CN207603445U - Series-fed circuit and computing device - Google Patents
Series-fed circuit and computing device Download PDFInfo
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- CN207603445U CN207603445U CN201721813513.XU CN201721813513U CN207603445U CN 207603445 U CN207603445 U CN 207603445U CN 201721813513 U CN201721813513 U CN 201721813513U CN 207603445 U CN207603445 U CN 207603445U
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Abstract
The utility model embodiment discloses a kind of series-fed circuit and computing device.The series-fed circuit carries out at least two groups of chipsets to be powered the series-fed of main operating voltage, carry out partial pressure power supply for Auxiliary Functioning Unit in chip using the voltage difference of main operating voltage in series chip path simultaneously, and by voltage clamp circuit by stable operating voltage main between chipset in fixed value.The utility model embodiment both ensure that the operating voltage consistency on each chip, increases chip operation performance, while improve power supply conversion efficiency, simplifies power supply lines, saves device cost.
Description
Technical field
The utility model is related to the power supply power supply technique of IC chip, more particularly to a kind of series-fed circuit and
Computing device.
Background technology
As cloud computing and the large-scale calculations sustained and rapid development of server rank and the whole world are to environmental protection and section
The promotion that can be realized, energy use efficiency become a very important index in hardware counting system.
Currently based on the computing device of large scale integrated circuit, using conventional parallel power supply structure, there are electric current is excessive, the energy
The significant drawbacks such as service efficiency is low, and increase the cost of requirement and the production design of chip circuit design.With semiconductor
The development of technique, the working power voltage of integrated circuit (IC) chip is lower and lower, and operating current is increasing, in order to maximize
The transfer efficiency of power supply, the prior art begin to take on the power supply mode of chip-in series, i.e., multigroup core on printed circuit board (PCB)
Piece forms the voltage domain of plural serial stage by the way of being serially connected between power input and ground terminal.This series connection supplies
Electric framework can effectively reduce circuit bulk supply electric current, improve power supply conversion efficiency, and can reduce power supply converter section
The cost of parallel circuit device.
But existing IC chip there is also some problems using this series-fed framework.On the one hand, existing series connection
Outer power voltage VCC is converted to output voltage VDD by DC-DC power module and is supplied to the IC chip of series connection by power supply circuit
Electricity, but the internal resistance of each chip is not completely the same, the internal resistance difference of each chip can cause to supply each chip
Operating voltage is inconsistent, therefore, to ensure that all chips can work normally, generally requires that output voltage VDD is turned up to ensure
The operating voltage of all chips of series connection is attained by normal working voltage, when the number of chips of series connection is more, is added in each core
The voltage consistency at piece both ends is poorer, to ensure that it is higher that all chips can work normally required output voltage VDD,
This overall power that can cause power supply circuit becomes larger, and reduces power supply conversion efficiency.On the other hand, IC chip necessary not only for
Arithmetic element and/or storage unit are powered, it is also necessary to which other functional components such as I/O components, PLL phase-locked loops are carried out
Power supply, the required operating voltage of these components is often different, these components are carried out with additional power supply power supply can increase power supply
The line layout and device cost of circuit can also reduce the power supply conversion efficiency of circuit entirety.
Therefore, it is necessary to a kind of series-fed scheme of new optimization is designed, to reduce the IC chip to series connection
Whole supply current promotes power supply conversion efficiency, simplifies wiring, reduces circuit devcie cost.
Utility model content
To solve the above-mentioned problems, the utility model proposes a kind of series-fed circuit and computing devices.
One side according to the present utility model proposes a kind of series-fed circuit, including：
At least two groups of chipsets being connected in series with, each chipset include the chip to be powered of m series connection, each wait to supply
Electrical chip has main operating voltage input terminal, back work voltage input end and ground terminal, and described at least two groups are connected in series with
Chipset carries out series-fed, DC-DC power source input terminal connection externally fed end, DC- between DC-DC power source output terminal and ground
The main operating voltage input terminal of the highest chip to be powered of DC power supply output terminal connection, ground terminal per level-one chip to be powered with
The main operating voltage input terminal of next stage chip to be powered is connected, so as to be to be powered per level-one via main operating voltage input terminal
Chip provides main operating voltage respectively；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal point per level-one Auxiliary Power Units
It is not connected to the ground terminal of chip to be powered at the same level, the to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units
The back work voltage input end of chip, the input terminal of wherein at least level-one Auxiliary Power Units are connected to the progress of externally fed end
Power supply, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to the corresponding series from highest chip to be powered down
The main operating voltage input terminal of chip to be powered, so as to be carried via back work voltage input end for the chip to be powered connected
For back work voltage.
In some embodiments, voltage clamp circuit, the voltage are connected between DC-DC power source output terminal and ground
It clamps down on circuit and includes at least one voltage output end, the voltage output end is respectively connected to the main work between adjacent chips group
Voltage input end, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed voltage；Wherein m is big
In or equal to 1 integer.
In some embodiments, the series-fed circuit further includes booster circuit, the input terminal of the booster circuit
Externally fed end is connected to, output terminal is connected to the input of Auxiliary Power Units corresponding with the superlative degree chip to be powered
End.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered
Enter end and PLL voltage input ends, I/O power supply units and PLL power supply units, the I/ are respectively included per level-one Auxiliary Power Units
The output terminal of O power supply units is connected to the I/O voltage input ends of chip to be powered at the same level, the output of the PLL power supply units
End is connected to the PLL voltage input ends of chip to be powered at the same level；The ground terminal of the I/O power supply units and PLL power supply units
It is respectively connected to the input of the ground terminal, wherein at least level-one I/O power supply units and PLL power supply units of chip to be powered at the same level
End is connected to externally fed end and is powered, and the input terminal of remaining I/O power supply units and PLL power supply units at different levels is sequentially connected to
From the main operating voltage input terminal of the chip to be powered of the corresponding series of highest chip to be powered down, so as to respectively via I/
O voltage input ends and PLL voltage input ends provide I/O voltages and PLL voltages for the chip to be powered connected.
In some embodiments, the voltage clamp circuit includes voltage transformation module, voltage attenuation module, may be programmed
Control module and drive module, the voltage transformation module are used to be converted to the input voltage of the DC-DC power source output terminal
At least one output voltage, the voltage attenuation module are used to receive the input voltage and at least one output voltage,
The programmable control module is inputted after being depressured respectively；The programmable control module is used for at least one output
Voltage carries out separate-blas estimation, and output pwm signal；The drive module is used to the voltage be controlled to turn according to the pwm signal
At least one output voltage for changing the mold block output is fixed voltage.
In some embodiments, one is connected between two chips to be powered adjacent in the series-fed circuit respectively
A level conversion unit, the level conversion unit are used to carry out signal level turn between two chips to be powered being connected
It changes.
Another aspect according to the present utility model proposes a kind of series-fed circuit, including：
At least two groups of chipsets being connected in series with, each chipset include at least two row chip to be powered in parallel, often
The chip to be powered that chip to be powered includes m series connection is arranged, each chip to be powered has main operating voltage input terminal, backman
Make voltage input end and ground terminal, at least two groups of chipsets being connected in series between DC-DC power source output terminal and ground into
Row series-fed, the main operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, DC-DC power source input terminal
Externally fed end is connected, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection is treated per level-one
The ground terminal of power supply chip is connected with the main operating voltage input terminal of next stage chip to be powered, so as to defeated via main operating voltage
It is to provide main operating voltage respectively per level-one chip to be powered to enter end；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal point per level-one Auxiliary Power Units
It is not connected to the ground terminal of chip to be powered at the same level, the to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units
The back work voltage input end of chip, the input terminal of wherein at least level-one Auxiliary Power Units are connected to the progress of externally fed end
Power supply, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to the corresponding series from highest chip to be powered down
The main operating voltage input terminal of chip to be powered, so as to be carried via back work voltage input end for the chip to be powered connected
For back work voltage.
In some embodiments, voltage clamp circuit, the voltage are connected between DC-DC power source output terminal and ground
It clamps down on circuit and includes at least one voltage output end, the voltage output end is respectively connected to the main work between adjacent chips group
Voltage input end, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed voltage；Wherein m is big
In or equal to 1 integer.
In some embodiments, the series-fed circuit further includes booster circuit, the input terminal of the booster circuit
Externally fed end is connected to, output terminal is connected to the input of Auxiliary Power Units corresponding with the superlative degree chip to be powered
End.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered
Enter end and PLL voltage input ends, I/O power supply units and PLL power supply units, the I/ are respectively included per level-one Auxiliary Power Units
The output terminal of O power supply units is connected to the I/O voltage input ends of chip to be powered at the same level, the output of the PLL power supply units
End is connected to the PLL voltage input ends of chip to be powered at the same level；The ground terminal of the I/O power supply units and PLL power supply units
It is respectively connected to the input of the ground terminal, wherein at least level-one I/O power supply units and PLL power supply units of chip to be powered at the same level
End is connected to externally fed end and is powered, and the input terminal of remaining I/O power supply units and PLL power supply units at different levels is sequentially connected to
From the main operating voltage input terminal of the chip to be powered of the corresponding series of highest chip to be powered down, so as to respectively via I/
O voltage input ends and PLL voltage input ends provide I/O voltages and PLL voltages for the chip to be powered connected.
In some embodiments, the voltage clamp circuit includes voltage transformation module, voltage attenuation module, may be programmed
Control module and drive module, the voltage transformation module are used to be converted to the input voltage of the DC-DC power source output terminal
At least one output voltage, the voltage attenuation module are used to receive the input voltage and at least one output voltage,
The programmable control module is inputted after being depressured respectively；The programmable control module is used for at least one output
Voltage carries out separate-blas estimation, and output pwm signal；The drive module is used to the voltage be controlled to turn according to the pwm signal
At least one output voltage for changing the mold block output is fixed voltage.
In some embodiments, one is connected between two chips to be powered adjacent in the series-fed circuit respectively
A level conversion unit, the level conversion unit are used to carry out signal level turn between two chips to be powered being connected
It changes.
Another further aspect according to the present utility model, it is also proposed that a kind of computing device, the computing device include any of the above-described
The series-fed circuit of embodiment.
The utility model embodiment makes full use of the voltage difference of main operating voltage in series chip path to be assisted in chip
Functional component carries out partial pressure power supply, and carries out voltage between chipset using voltage clamp circuit and fix, so as to both ensure
Operating voltage consistency on each chip, increases chip operation performance, while also improve power supply conversion efficiency, letter
Change power supply lines, save device cost.
Description of the drawings
Fig. 1 is the structure diagram of an embodiment of the utility model series-fed circuit；
Fig. 2 is the structure diagram of the another embodiment of the utility model series-fed circuit；
Fig. 3 is the structure diagram of the another embodiment of the utility model series-fed circuit；
Fig. 4 is the structure diagram of an embodiment of level conversion unit in the utility model series-fed circuit；
Fig. 5 is the structure diagram of an embodiment of the utility model voltage clamp circuit；
Fig. 6 is the partial circuit schematic diagram of an embodiment of the utility model voltage clamp circuit；
Fig. 7 is the flow diagram of an embodiment of the utility model series-fed method；
Fig. 8 is the flow diagram of the another embodiment of the utility model series-fed method；
Fig. 9 is the structure diagram of an embodiment of the utility model computing device.
Specific embodiment
For the purpose of this utility model, technical solution and advantage is more clearly understood, below in conjunction with specific embodiment, and
With reference to attached drawing, the utility model is further described.
Fig. 1 is the structure diagram of an embodiment of the utility model series-fed circuit.As shown in Figure 1, this reality
Include at least two groups chipsets being connected in series with the series-fed circuit of new embodiment and (3 groups of cores are only schematically presented in Fig. 1
Piece group), each chipset includes the chip to be powered of m series connection, each chip to be powered with main operating voltage input terminal,
Back work voltage input end and ground terminal, at least two groups of chipsets being connected in series with are on DC-DC power source output terminal and ground
(VSS) series-fed, DC-DC power source input terminal connection externally fed end (VCC), the connection of DC-DC power source output terminal are carried out between
The main operating voltage input terminal of highest chip to be powered, ground terminal and next stage chip to be powered per level-one chip to be powered
Main operating voltage input terminal be connected, so as to be to provide main work respectively per level-one chip to be powered via main operating voltage input terminal
Make voltage；
The series-fed circuit further includes the Auxiliary Power Units with being correspondingly arranged per level-one chip to be powered, per level-one
The ground terminal of Auxiliary Power Units is respectively connected to the ground terminal of chip to be powered at the same level, per the defeated of level-one Auxiliary Power Units
Outlet is connected to the input of the back work voltage input end, wherein at least level-one Auxiliary Power Units of chip to be powered at the same level
End is connected to externally fed end and is powered, and the input terminal of remaining Auxiliary Power Units at different levels is sequentially connected to wait to supply from the superlative degree
The main operating voltage input terminal of the chip to be powered of the corresponding series of electrical chip down, so as to via back work voltage input end
Chip to be powered to be connected provides back work voltage.
In some embodiments, the series-fed circuit is additionally included between DC-DC power source output terminal and ground (VSS)
The voltage clamp circuit being connected in parallel, the voltage clamp circuit include at least one voltage output end, the voltage output end
The main operating voltage input terminal being respectively connected between adjacent chips group, the main operating voltage between the adjacent chips group are defeated
Enter end and corresponding fixed voltage is provided.Wherein, m is the integer more than or equal to 1.
In some embodiments, with 3 chipsets, each chipset includes (the i.e. feelings of m=2 for 2 series chips
Shape), the main operating voltage of each IC chip is generally 1.6V, and externally fed end VCC provides 12V DC voltage, the utility model
12V DC voltage is converted to 9.6V by DC-DC power module first and is used as the 6th grade of (superlative degree) chip to be powered by embodiment
Main operating voltage, it is assumed that the internal resistance of each chip is identical, then inputs to the electricity of the main operating voltage input terminal of each chip
Pressure value is successively decreased successively, i.e. 9.6V, 8V, 6.4V, 4.8V, 3.2V, 1.6V, can provide the equilibrium of 1.6V on each chip in this way
Main operating voltage.
Secondly, the power supply of the special features such as input and output I/O interfaces, PLL phase-locked loops in each chip is come
It says, the utility model embodiment is powered by being correspondingly arranged an Auxiliary Power Units with chip at the same level, accessory power supply
Operating voltage is generally 6V or so,, can for what preceding accessory power supply more than the operating voltage 1.6V of each chip
, can be by what preceding chip to be powered by externally fed voltage 12V, and for what rear accessory power supply
Main operating voltage carries out partial pressure power supply, every to ensure so as to ensure that each accessory power supply can input the operating voltage of 6V or so
A accessory power supply can work normally.For example, for the 5th grade and the 4th grade of accessory power supply, input terminal is respectively connected to externally fed
Voltage 12V, thus the 5th grade and the 4th grade of accessory power supply can input the work of 12-6.4=5.6V and 12-4.8=7.2V respectively
Voltage, within the operating voltage range of permission；And for 3rd level accessory power supply, power input accesses the 6th grade of chip
Main operating voltage input terminal, the in this way voltage in the input terminal of accessory power supply offer 9.6V, and the ground terminal of the accessory power supply
The main operating voltage 3.2V of the 2nd grade of chip is connected, therefore, the work of 9.6-3.2=6.4V can be inputted on the accessory power supply
Voltage；Similarly, for the 2nd grade of accessory power supply, input terminal accesses the main operating voltage input terminal of the 5th grade of chip, in this way at this
The operating voltage of 8-1.6=6.4V is provided on accessory power supply simultaneously；And for the 6th grade of accessory power supply, due to externally fed electricity
Enough voltage differences can not be formed between the ground connection terminal voltage 8V of 12V and the 6th grade of accessory power supply of pressure, so needing additional increase by one
A booster circuit can also provide 12V boost in voltage to the operating voltage of 6V for 14V to ensure the accessory power supply, thus can guarantee
Each accessory power supply can work normally.The advantages of this power supply mode is to improve power supply conversion efficiency, reduces circuit line
Road connects up, and has saved device cost.
Furthermore since the internal resistance of series-fed chip is not fully identical, when series chip quantity increases, can not ensure
Operating voltage on each chip is completely the same, and the partial pressure power supply of accessory power supply will be further influenced in tandem paths
The stability of the operating voltage of chip.The utility model embodiment is by increasing a voltage clamp circuit, in adjacent chip
The fixed voltage of voltage clamp circuit output is respectively connected between group so that stable work is had input between adjacent chipset
Voltage value, so as to ensure that the stable operating voltage inputted on each chip in this group of chip is balanced.For example, for above-mentioned 3
Chipset, each chipset include the example of 2 series chips, and voltage clamp circuit inputs between adjacent chipset respectively
The fixed voltage of 6.4V and 3.2V, so as to ensure that it is electric that the operating voltage of 2 chips in each group can reach stablizing for 1.6V
Pressure improves the working performance of each chip of series connection.
The embodiment that voltage clamp circuit includes 2 voltage output ends, practical application are only symbolically presented in Fig. 1
In, the quantity of the voltage output end of voltage clamp circuit depends on the quantity of chipset, with ensure adjacent two groups of chip group it
Between be all connected with the voltage output end of a voltage clamp circuit, this ensure that in every group of chip each chip operating voltage it is consistent
Property.
Fig. 2 is the structure diagram of the another embodiment of the utility model series-fed circuit.As shown in Fig. 2, this
On the basis of the series-fed circuit embodiment shown in Fig. 1 of utility model embodiment, further by the chipset of each series connection
The mode of multiple row parallel connection is extended to, which includes：
At least two groups of chipsets being connected in series with, each chipset include at least two row chip to be powered in parallel, often
The chip to be powered that chip to be powered includes m series connection is arranged, each chip to be powered has main operating voltage input terminal, backman
Make voltage input end and ground terminal, at least two groups of chipsets being connected in series between DC-DC power source output terminal and ground into
Row series-fed, the main operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, DC-DC power source input terminal
Externally fed end is connected, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection is treated per level-one
The ground terminal of power supply chip is connected with the main operating voltage input terminal of next stage chip to be powered, so as to defeated via main operating voltage
It is to provide main operating voltage respectively per level-one chip to be powered to enter end；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal point per level-one Auxiliary Power Units
It is not connected to the ground terminal of chip to be powered at the same level, the to be powered of peer is connected to per the output terminal of level-one Auxiliary Power Units
The back work voltage input end of chip, the input terminal of wherein at least level-one Auxiliary Power Units are connected to the progress of externally fed end
Power supply, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to the corresponding series from highest chip to be powered down
The main operating voltage input terminal of chip to be powered, so as to be carried via back work voltage input end for the chip to be powered connected
For back work voltage.
In some embodiments, voltage clamp circuit is connected in parallel between DC-DC power source output terminal and ground, it is described
Voltage clamp circuit includes at least one voltage output end, and the voltage output end is respectively connected to the master between adjacent chips group
Operating voltage input terminal, the main operating voltage input terminal between the adjacent chips group provide corresponding fixed voltage；Wherein m
To be greater than or equal to 1 integer.
Specifically, present embodiment is identical with Fig. 1 illustrated embodiments to the power supply mode of each chip, herein no longer
It repeats.
Fig. 3 is the structure diagram of the another embodiment of the utility model series-fed circuit.The way of example
On the basis of the embodiment of Fig. 1 or Fig. 2, Auxiliary Power Units are improved, i.e., it is each in described series-fed circuit
The back work voltage input end of chip to be powered includes I/O voltage input ends and PLL voltage input ends, per level-one accessory power supply
Unit respectively includes I/O power supply units and PLL power supply units, and the output terminals of the I/O power supply units, which is connected to, at the same level to be waited to supply
The I/O voltage input ends of electrical chip, the output terminal of the PLL power supply units are connected to the PLL voltages of chip to be powered at the same level
Input terminal；The ground terminal of the I/O power supply units and PLL power supply units is respectively connected to the ground connection of chip to be powered at the same level
End, wherein at least the input terminal of level-one I/O power supply units and PLL power supply units is connected to externally fed end and is powered, remaining
The input terminal of I/O power supply units and PLL power supply units at different levels is sequentially connected to the corresponding stage from highest chip to be powered down
The main operating voltage input terminal of several chips to be powered, so as to be respectively institute via I/O voltage input ends and PLL voltage input ends
The chip to be powered of connection provides I/O voltages and PLL voltages.
Fig. 3 only symbolically presents the improvement on the basis of embodiment shown in Fig. 2, for Fig. 1 illustrated embodiments
Improved procedure it is same.
The series-fed circuit of the utility model embodiment uses main operating voltage series-fed, due to the not same core of series connection
The voltage domain that on piece is formed is of different sizes, and in order to ensure the signal communication between chip, the utility model embodiment further exists
A level conversion unit is connected in series between two adjacent chips to be powered.Fig. 4 is the utility model series-fed circuit
The structure diagram of one embodiment of middle level conversion unit.As shown in figure 4, the series-fed of the utility model embodiment
Circuit between two adjacent units to be powered is connected in series with a level and turns respectively on the basis of aforementioned any embodiment
Unit is changed, the level conversion unit is used to carry out signal level conversion between two units to be powered being connected.
Specifically, level conversion unit for example may be used capacitive couplings, differential signal transmission method and or diode
Pressure decline method is realized.Each chip to be powered passes through the low to high signal level modular converter and upper one in level conversion unit respectively
Chip to be powered connection in step voltage domain, by the high to Low signal level modular converter in signal level converting unit under
Chip to be powered connection in voltage order one domain.Since the voltage domain formed on the difference chip to be powered of series connection is of different sizes,
Upper level voltage domain is higher than this step voltage domain, this step voltage domain is to be powered per step voltage domain again higher than next stage voltage domain
The signal that this grade of chip to be powered is sent is converted to upper level voltage domain by chip by low to high signal level modular converter
Upper level chip to be powered is sent to after signal；Chip to be powered per step voltage domain passes through high to Low signal level modular converter
Next stage chip to be powered is sent to after the signal that this grade of chip to be powered is sent is converted to the signal of next stage voltage domain, from
And the signal communication between different voltages domain is realized between the chip to be powered of series connection.
Fig. 5 is the structure diagram of an embodiment of voltage clamp circuit in the utility model series-fed circuit.
As shown in figure 5, the voltage clamp circuit of the utility model embodiment include voltage transformation module 10, voltage attenuation module 20, can
Programming Control module 30, drive module 40.
Input voltage vin is carried out DC-DC conversions by voltage transformation module 10, is obtained at least one output voltage, is shown in Fig. 5
Illustrate to meaning property the situation of two output voltages Vout1 and Vout2.Voltage attenuation module 20 is respectively by two output voltages
Vout1, Vout2 and input voltage vin carry out decompression attenuation, respectively obtain evanescent voltage signal AN0, AN1 and AN2, Ran Houfen
It Shu Ru not programmable control module 30.Programmable control module 30 carries out voltage according to AN0, AN1 and AN2 voltage signal of input
Separate-blas estimation, so as to give driving mould according to result output pulse width modulation (PWM) the signal PWM1 and PWM2 that voltage deviation detects
Block 40.The pwm signal that programmable control module 30 exports is respectively converted into voltage transformation module 10 and switchs by drive module 40
The drive signal of circuit, to control in voltage transformation module 10 switching circuit on and off being boosted to output voltage or
Decompression, so that it is guaranteed that the output voltage stabilization of voltage transformation module is in a fixed value.
In the utility model embodiment, MCU microcontrollers or other programmable logic may be used in programmable control module 30
Device such as FPGA etc. realizes that the input and output voltage deviation that different range is adapted to by programmable program code is examined
It surveys and voltage stabilizing controls, without changing the structure of circuit, there is stronger configurability and flexibility.
Fig. 6 is the circuit signal of an embodiment of voltage transformation module 10 in the utility model voltage clamp circuit
Figure.As shown in fig. 6, the voltage transformation module 10 of the utility model embodiment include mainly by two groups of metal-oxide-semiconductor field effect transistor MOS1,
The switching circuit of MOS2 and MOS3, MOS4 composition, the wherein source electrode of MOS1 is connected with the drain electrode of MOS2, the source electrode of MOS3 and
The drain electrode of MOS4 is connected, and the source electrode ground connection of MOS2 and MOS4, input voltage vin input the drain electrode of MOS1 and the leakage of MOS3 respectively
Pole；The source electrode that the source electrode of MOS1 connects inductance L1, MOS3 with the drain electrode of MOS2 connects inductance L2 with the drain electrode of MOS4, inductance L1's
The other end connects output voltage terminal Vout1, the other end connection output voltage terminal Vout2 of inductance L2；It is Input voltage terminal Vin, defeated
Go out to pass sequentially through multigroup shunt capacitance between voltage end Vout1, output voltage terminal Vout2 and ground GND and be connected in series, i.e., it is defeated
Enter and capacitance C1-C4 is connected in parallel between voltage end Vin, output voltage terminal Vout1, output voltage terminal Vout1, output voltage terminal
Capacitance C5-C8 is connected in parallel between Vout2, capacitance C9-C12 is connected in parallel between output voltage terminal Vout2 and ground GND.MOS1
Drain electrode and MOS2 source electrode between connect between the drain electrode of series connection one capacitance C13, MOS3 and the source electrode of MOS3 a capacitance
C14。
MOS1-MOS4 be based respectively on input grid drive signal DRVH1, DRVL1, DRVH2, DRVL2 be connected and
It closes.When programmable control module 30 detects that output voltage Vout1 is less than fixed value, output pulse width modulation (PWM) 1 is believed
Number, drive signal DRVH1, DRVL1 are converted to through drive module 40, drive signal DRVH1, DRVL1 are used to control MOS1 respectively
Conducting and MOS2 shutdowns so that form charge circuit in inductance L1, boost to output voltage Vout1；Work as PLC technology
When module 30 detects that output voltage Vout1 is higher than fixed value, 1 signal of output pulse width modulation (PWM), through 40 turns of drive module
Drive signal DRVH1, DRVL1 are changed to, drive signal DRVH1, DRVL1 make for control MOS1 shutdowns respectively and MOS2 conductings
It obtains in inductance L1 and forms discharge loop, output voltage Vout1 is depressured.Similarly, when programmable control module 30 detects
When output voltage Vout2 is below or above fixed value, 2 signal of output pulse width modulation (PWM) is converted to through drive module 40
Drive signal DRVH2, DRVL2, drive signal DRVH2, DRVL2 are for control MOS3 and MOS4 on or off respectively so that
Charge or discharge circuit is formed in inductance L2, boost or depressurization is carried out to output voltage Vout2.
In the utility model embodiment, capacitance C1-C3, C5-C7, C9-C11 selection resistance to voltage capacitances of 22uf/25V, C4, C8,
C12 chooses high power capacity 470uf/16V, low-impedance electrolytic capacitor, and this parallel combination has lower impedance path, Neng Gou
When playing the role of voltage regulation filtering, the output voltage ripple of Vout1, Vout2 are effectively reduced.
In the utility model embodiment, when the input voltage vin being powered to 3 series chip groups is 9.6V, electricity
Two output end vos ut1 and Vout2 of pressing tongs circuit connect the main operating voltage input terminal between adjacent chips group respectively,
Middle Vout1 is connected between chipset 3 and chipset 2, and Vout2 is connected between chipset 2 and chipset 1, is exported respectively
6.4V and 3.2V so as to which the input terminal voltage of chipset 2 and chipset 1 to be clamped down on to the burning voltage in 6.4V and 3.2V, ensures
The stable work in work of each series chip.
Fig. 7 is the flow diagram of an embodiment of the utility model series-fed method.As shown in fig. 7, this reality
With the series-fed method of new embodiment for being that at least two groups of chipsets being connected in series with are powered, each chipset is equal
Include the chip to be powered of m series connection, each chip to be powered has main operating voltage input terminal, back work voltage input end
And ground terminal, this method include：
At least two groups of chipsets being connected in series with are carried out series connection confession by step S11 between DC-DC power source output terminal and ground
Electricity, DC-DC power source input terminal connection externally fed end, the main work of the highest chip to be powered of DC-DC power source output terminal connection
Voltage input end, the ground terminal per level-one chip to be powered are connected with the main operating voltage input terminal of next stage chip to be powered,
So as to be to provide main operating voltage respectively per level-one chip to be powered via main operating voltage input terminal；
The ground terminal of Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to by step S12
The ground terminal of chip to be powered at the same level is connected to the auxiliary of chip to be powered at the same level per the output terminal of level-one Auxiliary Power Units
Assistant engineer makees voltage input end, and the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered,
The input terminal of remaining Auxiliary Power Units at different levels is sequentially connected to the to be powered of the corresponding series from highest chip to be powered down
The main operating voltage input terminal of chip, so as to provide auxiliary for the chip to be powered connected via back work voltage input end
Operating voltage.
In some embodiments, the series-fed method further includes step：
A voltage clamp circuit is connected in parallel between DC-DC power source output terminal and ground, by the voltage clamp circuit
At least one voltage output end be respectively connected to main operating voltage input terminal between adjacent chips group, be the adjacent chips
Main operating voltage input terminal between group provides corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
In some embodiments, the series-fed method is further included is connected to outside by the input terminal of a booster circuit
Feeder ear, output terminal are connected to the input terminal of Auxiliary Power Units corresponding with the superlative degree chip to be powered.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered
Enter end and PLL voltage input ends, I/O power supply units and PLL power supply units, the side are respectively included per level-one Auxiliary Power Units
Method further comprises：The output terminal of the I/O power supply units is connected to the I/O voltage input ends of chip to be powered at the same level,
The output terminal of the PLL power supply units is connected to the PLL voltage input ends of chip to be powered at the same level, by the I/O power supplys
The ground terminal of unit and PLL power supply units is respectively connected to the ground terminal of chip to be powered at the same level, wherein at least level-one I/O electricity
The input terminal of source unit and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL at different levels
The input terminal of power supply unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down
Make voltage input end, so as to be provided respectively via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected
I/O voltages and PLL voltages.
In some embodiments, the embodiment of the voltage clamp circuit is as previously described.
In some embodiments, the series-fed method is additionally included between two adjacent chips to be powered respectively
One level conversion unit of series connection, the embodiment of the level conversion unit is as previously described.
Fig. 8 is the flow diagram of an embodiment of the utility model series-fed method.As shown in figure 8, this reality
With the series-fed method of new embodiment for being that at least two groups of chipsets being connected in series with are powered, each chipset is equal
Including at least two row chip to be powered in parallel, each column chip to be powered includes the chip to be powered of m series connection, each to be powered
There is chip main operating voltage input terminal, back work voltage input end and ground terminal, this method to include：
At least two groups of chipsets being connected in series with are carried out series connection confession by step S21 between DC-DC power source output terminal and ground
Electricity, the main operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, and the connection of DC-DC power source input terminal is external
Feeder ear, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection, per level-one chip to be powered
Ground terminal be connected with the main operating voltage input terminal of next stage chip to be powered, so as to via main operating voltage input terminal be every
Level-one chip to be powered provides main operating voltage respectively；
The ground terminal of Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered is respectively connected to by step S22
The ground terminal of chip to be powered at the same level is connected to the auxiliary of chip to be powered at the same level per the output terminal of level-one Auxiliary Power Units
Assistant engineer makees voltage input end, and the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and is powered,
The input terminal of remaining Auxiliary Power Units at different levels is sequentially connected to the to be powered of the corresponding series from highest chip to be powered down
The main operating voltage input terminal of chip, so as to provide auxiliary for the chip to be powered connected via back work voltage input end
Operating voltage.
In some embodiments, the series-fed method further includes step：
A voltage clamp circuit is connected in parallel between DC-DC power source output terminal and ground, by the voltage clamp circuit
At least one voltage output end be respectively connected to main operating voltage input terminal between adjacent chips group, be the adjacent chips
Main operating voltage input terminal between group provides corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
In some embodiments, the series-fed method is further included is connected to outside by the input terminal of a booster circuit
Feeder ear, output terminal are connected to the input terminal of Auxiliary Power Units corresponding with the superlative degree chip to be powered.
In some embodiments, it is defeated to include I/O voltages for the back work voltage input end of each chip to be powered
Enter end and PLL voltage input ends, I/O power supply units and PLL power supply units, the side are respectively included per level-one Auxiliary Power Units
Method further comprises：The output terminal of the I/O power supply units is connected to the I/O voltage input ends of chip to be powered at the same level,
The output terminal of the PLL power supply units is connected to the PLL voltage input ends of chip to be powered at the same level, by the I/O power supplys
The ground terminal of unit and PLL power supply units is respectively connected to the ground terminal of chip to be powered at the same level, wherein at least level-one I/O electricity
The input terminal of source unit and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL at different levels
The input terminal of power supply unit is sequentially connected to the main work of the chip to be powered of the corresponding series from highest chip to be powered down
Make voltage input end, so as to be provided respectively via I/O voltage input ends and PLL voltage input ends for the chip to be powered connected
I/O voltages and PLL voltages.
In some embodiments, the embodiment of the voltage clamp circuit is as previously described.
In some embodiments, the series-fed method is additionally included between two adjacent chips to be powered respectively
One level conversion unit of series connection, the embodiment of the level conversion unit is as previously described.
Fig. 9 is the structure diagram of an embodiment of the utility model computing device.As shown in figure 9, this practicality is new
The computing device 100 of type embodiment includes the series-fed circuit of aforementioned any embodiment.
Particular embodiments described above has carried out into one the purpose of this utility model, technical solution and advantageous effect
Step is described in detail, it should be understood that the foregoing is merely specific embodiment of the utility model, is not limited to this
Utility model, within the spirit and principle of the utility model, any modification, equivalent substitution, improvement and etc. done should all wrap
Containing being within the protection scope of the utility model.
Claims (13)
1. a kind of series-fed circuit, which is characterized in that including：
At least two groups of chipsets being connected in series with, each chipset include the chip to be powered of m series connection, each core to be powered
Piece has main operating voltage input terminal, back work voltage input end and ground terminal, at least two groups of chips being connected in series with
Group carries out series-fed, DC-DC power source input terminal connection externally fed end, DC-DC electricity between DC-DC power source output terminal and ground
The main operating voltage input terminal of the highest chip to be powered of source output terminal connection, ground terminal per level-one chip to be powered with it is next
The main operating voltage input terminal of grade chip to be powered is connected, so as to be per level-one chip to be powered via main operating voltage input terminal
Main operating voltage is provided respectively；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal per level-one Auxiliary Power Units connect respectively
The ground terminal of chip to be powered at the same level is connected to, chip to be powered at the same level is connected to per the output terminal of level-one Auxiliary Power Units
Back work voltage input end, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and supplied
Electricity, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to treating for the corresponding series from highest chip to be powered down
The main operating voltage input terminal of power supply chip, so as to be provided via back work voltage input end for the chip to be powered connected
Back work voltage.
2. series-fed circuit according to claim 1, which is characterized in that connect between DC-DC power source output terminal and ground
Voltage clamp circuit is connected to, the voltage clamp circuit includes at least one voltage output end, and the voltage output end connects respectively
The main operating voltage input terminal being connected between adjacent chips group, the main operating voltage input terminal between the adjacent chips group carry
For corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
3. series-fed circuit according to claim 1, which is characterized in that the series-fed circuit further includes boosting electricity
Road, the input terminal of the booster circuit are connected to externally fed end, and output terminal is connected to and the superlative degree chip pair to be powered
The input terminal for the Auxiliary Power Units answered.
4. series-fed circuit according to claim 1, which is characterized in that the back work voltage of each chip to be powered
Input terminal includes I/O voltage input ends and PLL voltage input ends, and I/O power supply units are respectively included per level-one Auxiliary Power Units
With PLL power supply units, the output terminal of the I/O power supply units is connected to the I/O voltage input ends of chip to be powered at the same level, institute
The output terminal for stating PLL power supply units is connected to the PLL voltage input ends of chip to be powered at the same level；The I/O power supply units and
The ground terminal of PLL power supply units is respectively connected to the ground terminal of chip to be powered at the same level, wherein at least level-one I/O power supply units
Externally fed end is connected to the input terminal of PLL power supply units to be powered, remaining I/O power supply units and PLL power supply list at different levels
The input terminal of member is sequentially connected to the main operating voltage of the chip to be powered of the corresponding series from highest chip to be powered down
Input terminal, so as to provide I/O electricity for the chip to be powered connected via I/O voltage input ends and PLL voltage input ends respectively
Pressure and PLL voltages.
5. series-fed circuit according to claim 2, which is characterized in that the voltage clamp circuit is converted including voltage
Module, voltage attenuation module, programmable control module and drive module, the voltage transformation module are used for DC-DC electricity
The input voltage of source output terminal is converted at least one output voltage, and the voltage attenuation module is used to receive the input voltage
With at least one output voltage, the programmable control module is inputted after being depressured respectively；The programmable control molding
Block is used to carry out separate-blas estimation, and output pwm signal at least one output voltage；The drive module is used for according to institute
It is fixed voltage to state pwm signal and control at least one output voltage of the voltage transformation module output.
6. series-fed circuit according to claim 4, which is characterized in that adjacent two in the series-fed circuit
It connects respectively between chip to be powered a level conversion unit, the level conversion unit in two to be connected for waiting to supply
Signal level conversion is carried out between electrical chip.
7. a kind of series-fed circuit, which is characterized in that including：
At least two groups of chipsets being connected in series with, each chipset include at least two row chip to be powered in parallel, and each column is treated
Power supply chip includes the chip to be powered of m series connection, and each chip to be powered has main operating voltage input terminal, back work electricity
Pressure input terminal and ground terminal, at least two groups of chipsets being connected in series with are gone here and there between DC-DC power source output terminal and ground
Alliance electricity, the main operating voltage input terminal and ground terminal of chip to be powered at the same level are respectively connected with, the connection of DC-DC power source input terminal
Externally fed end, the main operating voltage input terminal of the highest chip to be powered of DC-DC power source output terminal connection are to be powered per level-one
The ground terminal of chip is connected with the main operating voltage input terminal of next stage chip to be powered, so as to via main operating voltage input terminal
Main operating voltage is provided respectively for every level-one chip to be powered；
The Auxiliary Power Units being correspondingly arranged with every level-one chip to be powered, the ground terminal per level-one Auxiliary Power Units connect respectively
The ground terminal of chip to be powered at the same level is connected to, chip to be powered at the same level is connected to per the output terminal of level-one Auxiliary Power Units
Back work voltage input end, the input terminal of wherein at least level-one Auxiliary Power Units is connected to externally fed end and supplied
Electricity, the input terminal of remaining Auxiliary Power Units at different levels are sequentially connected to treating for the corresponding series from highest chip to be powered down
The main operating voltage input terminal of power supply chip, so as to be provided via back work voltage input end for the chip to be powered connected
Back work voltage.
8. series-fed circuit according to claim 7, which is characterized in that connect between DC-DC power source output terminal and ground
Voltage clamp circuit is connected to, the voltage clamp circuit includes at least one voltage output end, and the voltage output end connects respectively
The main operating voltage input terminal being connected between adjacent chips group, the main operating voltage input terminal between the adjacent chips group carry
For corresponding fixed voltage；Wherein m is the integer more than or equal to 1.
9. series-fed circuit according to claim 7, which is characterized in that the series-fed circuit further includes boosting electricity
Road, the input terminal of the booster circuit are connected to externally fed end, and output terminal is connected to and the superlative degree chip pair to be powered
The input terminal for the Auxiliary Power Units answered.
10. series-fed circuit according to claim 7, which is characterized in that the back work electricity of each chip to be powered
Input terminal is pressed to include I/O voltage input ends and PLL voltage input ends, I/O power supply lists are respectively included per level-one Auxiliary Power Units
Member and PLL power supply units, the output terminal of the I/O power supply units are connected to the I/O voltage input ends of chip to be powered at the same level,
The output terminal of the PLL power supply units is connected to the PLL voltage input ends of chip to be powered at the same level；The I/O power supply units
The ground terminal of chip to be powered at the same level, wherein at least level-one I/O power supplys list are respectively connected to the ground terminal of PLL power supply units
The input terminal of member and PLL power supply units is connected to externally fed end and is powered, remaining I/O power supply units and PLL power supplys at different levels
The input terminal of unit is sequentially connected to the main work electricity of the chip to be powered of the corresponding series from highest chip to be powered down
Input terminal is pressed, so as to provide I/O for the chip to be powered connected via I/O voltage input ends and PLL voltage input ends respectively
Voltage and PLL voltages.
11. series-fed circuit according to claim 7, which is characterized in that the voltage clamp circuit turns including voltage
Block, voltage attenuation module, programmable control module and drive module are changed the mold, the voltage transformation module is used for the DC-DC
The input voltage of power output end is converted at least one output voltage, and the voltage attenuation module is electric for receiving the input
Pressure and at least one output voltage, input the programmable control module after being depressured respectively；The PLC technology
Module is used to carry out separate-blas estimation, and output pwm signal at least one output voltage；The drive module is used for basis
It is fixed voltage that the pwm signal, which controls at least one output voltage of the voltage transformation module output,.
12. series-fed circuit according to claim 11, which is characterized in that adjacent two in the series-fed circuit
It connects respectively between a chip to be powered a level conversion unit, the level conversion unit in two to be connected for treating
Signal level conversion is carried out between power supply chip.
13. a kind of computing device, which is characterized in that the computing device includes the series connection of claim 1-12 any one of them and supplies
Circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721813513.XU CN207603445U (en) | 2017-12-21 | 2017-12-21 | Series-fed circuit and computing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721813513.XU CN207603445U (en) | 2017-12-21 | 2017-12-21 | Series-fed circuit and computing device |
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| CN207603445U true CN207603445U (en) | 2018-07-10 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107947566A (en) * | 2017-12-21 | 2018-04-20 | 北京比特大陆科技有限公司 | Series-fed circuit, method and computing device |
| CN111857224A (en) * | 2020-07-31 | 2020-10-30 | 深圳君略科技有限公司 | Multistage chip series circuit and driving system |
| CN112256115A (en) * | 2020-09-21 | 2021-01-22 | 北京比特大陆科技有限公司 | Power supply circuit, chip and electronic equipment |
| US11016554B2 (en) | 2019-01-08 | 2021-05-25 | Digwise Technology Corporation, Ltd | Semiconductor apparatus |
| CN112968600A (en) * | 2021-02-19 | 2021-06-15 | 浙江曲速科技有限公司 | Limited dynamic power consumption chip system and task scheduling method for serial power supply thereof |
-
2017
- 2017-12-21 CN CN201721813513.XU patent/CN207603445U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107947566A (en) * | 2017-12-21 | 2018-04-20 | 北京比特大陆科技有限公司 | Series-fed circuit, method and computing device |
| WO2019120295A1 (en) * | 2017-12-21 | 2019-06-27 | Bitmain Technologies Inc. | Power supply circuit, series power supply method and computing system thereof |
| US11016554B2 (en) | 2019-01-08 | 2021-05-25 | Digwise Technology Corporation, Ltd | Semiconductor apparatus |
| CN111857224A (en) * | 2020-07-31 | 2020-10-30 | 深圳君略科技有限公司 | Multistage chip series circuit and driving system |
| CN112256115A (en) * | 2020-09-21 | 2021-01-22 | 北京比特大陆科技有限公司 | Power supply circuit, chip and electronic equipment |
| CN112968600A (en) * | 2021-02-19 | 2021-06-15 | 浙江曲速科技有限公司 | Limited dynamic power consumption chip system and task scheduling method for serial power supply thereof |
| CN112968600B (en) * | 2021-02-19 | 2022-07-08 | 浙江曲速科技有限公司 | Task scheduling method for serial power supply of limited dynamic power consumption chip system |
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Inventor after: Chang Xin Inventor after: Cheng Wenjie Inventor after: Zhan Ketuan Inventor before: Chang Xin Inventor before: Chen Wenjie Inventor before: Zhan Ketuan |