CN218183240U

CN218183240U - Variable output voltage control device based on duty ratio modulation

Info

Publication number: CN218183240U
Application number: CN202221751416.3U
Authority: CN
Inventors: 傅志军; 王远东
Original assignee: Shenzhen Qicaihong Yugong Information Technology Development Co ltd
Current assignee: Shenzhen Qicaihong Yugong Information Technology Development Co ltd
Priority date: 2022-07-08
Filing date: 2022-07-08
Publication date: 2022-12-30
Anticipated expiration: 2032-07-08

Abstract

The utility model provides a variable output voltage controlling means based on duty cycle modulation, include: the pulse width modulation circuit comprises an input control module, a pulse width modulation module and an output control module, wherein the pulse width modulation module comprises a pulse width modulation chip, a first logic gate and a second logic gate, an input signal is connected to a reference input end of the pulse width modulation module through the input control module, the pulse width modulation module is connected to the output control module through the first logic gate and the second logic gate respectively, and the output control module is further connected to a feedback end of the pulse width modulation module. The utility model discloses a hardware module design of optimizing only needs can realize output voltage's adjustable control through GPIO port and pulse width modulation buffer, and overall structure design is simple and high-efficient, and control is simple and convenient, and is with low costs, no longer restricts to main chip and power chip from taking the special agreement interface of adjusting voltage, can improve the general performance and the nimble degree of application of product well.

Description

Variable output voltage control device based on duty ratio modulation

Technical Field

The utility model relates to an output voltage controlling means especially relates to a variable output voltage controlling means based on duty cycle modulation.

Background

At present, the dynamic voltage regulation modes in the field of DC-DC BUCK switch power supplies mainly comprise the following 2 modes: the first and upper semiconductor industry customizes respective dynamic voltage regulation protocol interfaces, and power supply chip manufacturers support interface protocols such as PMBUS, SVID and SVI2 to realize dynamic voltage regulation output according to the unique protocol of the huge head of each industry. And secondly, the reference voltage division proportion of the multi-path parallel resistor is controlled through the GPIO port of the main chip, so that dynamic voltage regulation output of the fixed reference voltage power supply chip is realized, for example, 8 different voltage outputs can be realized through 3 GPIO ports, and 16 different voltage outputs can be realized through 4 GPIO ports.

If the first way of supporting the power chip of the specific interface protocol is adopted, the universality of the materials is greatly reduced, for example, the CPU of Intel must use the power chip of SVID protocol, the CPU of AMD must use the power chip of SVI2 protocol, and the two protocols are not compatible with each other. Meanwhile, the main control chips of other manufacturers do not have a dedicated voltage regulation interface, and even if the power supply chip has a voltage regulation interface protocol, the output voltage regulation cannot be realized directly through the interface protocol.

If a second mode of controlling the multi-path parallel resistor to divide the voltage of the fixed reference voltage source through a plurality of GPIO ports of the main chip is adopted, the required GPIO ports are more, the realized voltage order is more limited, for example, 3 GPIO ports are used, only the third power of two can be realized, and 8 voltage orders are totally realized, and if more voltage orders are realized, the number of the required GPIO ports, the number of the series voltage dividing resistors and the number of MOSFET switching tubes are increased sharply. If the number of GPIO ports carried by the main chip is not enough, or the PCB has structural and ID design limitations, the size of the PCB cannot be increased, and the design scheme is not feasible.

Disclosure of Invention

The utility model aims to solve the technical problem that a variable output voltage controlling means based on duty cycle modulation needs to be provided, aims at realizing only needing a GPIO port through hardware module ization design and can control, improves the general performance and the nimble application degree of product.

To this end, the utility model provides a variable output voltage controlling means based on duty cycle modulation, include: the pulse width modulation circuit comprises an input control module, a pulse width modulation module and an output control module, wherein the pulse width modulation module comprises a pulse width modulation chip, a first logic gate and a second logic gate, an input signal is connected to a reference input end of the pulse width modulation module through the input control module, the pulse width modulation module is connected to the output control module through the first logic gate and the second logic gate respectively, and the output control module is further connected to a feedback end of the pulse width modulation module.

The utility model discloses a further improvement lies in, output control module includes first switch tube, inductance, electric capacity and second switch tube, first logic gate respectively with first switch tube and the one end of inductance is connected, first switch tube is connected to the power end, the second logic gate passes through the second switch tube is connected to the one end of inductance, the other end of inductance passes through electric capacity ground connection.

The utility model discloses a further improvement lies in, the inductance is close to the one end of voltage output end and is connected to the feedback end of pulse width modulation module.

The utility model discloses a further improvement lies in, input control module is the fractional order input module based on the empty ratio modulation.

The utility model discloses a further improvement lies in, hierarchical input module includes resistance R1, electric capacity C1, resistance R2, resistance R3, resistance R4 and resistance R5, resistance R1 respectively with electric capacity C1's one end and resistance R2 and resistance R3's connected node A is connected, resistance R2 is connected to the reference voltage end, electric capacity C1's other end ground connection, resistance R3 keeps away from resistance R2's one end is passed through resistance R4 and resistance R5 ground connection, resistance R3 and resistance R4's connected node B be connected to the reference input of pulse width modulation module.

The utility model discloses a further improvement lies in, hierarchical input module still includes the pulse width modulation buffer, the output of pulse width modulation buffer is connected to resistance R1.

The utility model discloses a further improvement lies in, the voltage of reference voltage end is 2V.

The utility model discloses a further improvement lies in, variable output voltage controlling means's starting voltage is 0.8V.

Compared with the prior art, the beneficial effects of the utility model reside in that: through the design of the optimized hardware module, the adjustable control of the output voltage can be realized only through one GPIO port and the pulse width modulation buffer, the whole structure design is simple and efficient, the control is simple and convenient, the cost is low, the control is not limited to a protocol interface with a special voltage adjustment function of the main chip and the power chip, and a plurality of GPIO ports are not needed, so that the general performance and the flexible application degree of the product are well improved.

Drawings

Fig. 1 is a schematic diagram of a circuit module according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a circuit for realizing a limited-order output voltage by using shunt resistors.

Detailed Description

Preferred embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

According to the voltage control principle of the Buck switching power supply chip, generally, a feedback voltage FB fed back by a voltage Vout is compared with a voltage of a reference input end REFIN of the power supply chip, when the voltage of the Vout changes due to load change, the BUCK power supply chip can timely adjust the conducting time of upper and lower bridge MOSFETs, and finally the voltage of the Vout following the reference input end REFIN is achieved.

As shown in fig. 2, if the parallel voltage-dividing resistor is used to realize the limited-order output voltage, when the main chip needs to realize 4 voltage outputs during operation, it is necessary for the main chip to output a high level or a low level through two GPIO ports to control the on/off of the MOSFET, and finally to control whether the input-stage resistors form a parallel relationship. In this way, if 4 fixed output voltages are required for supplying power to one chip, two GPIO ports of the chip are required to implement a variable output voltage control function; if 8 different voltage outputs need to be realized, three GPIO ports are needed; if 16 different voltage outputs need to be realized, four GPIO ports are needed, therefore, fig. 2 utilizes a plurality of GPIO ports to control a plurality of shunt divider resistors, the adjustable output voltage of the fixed reference voltage power supply chip obviously has the defect of large number of GPIO ports, if the required output voltage order is large, the GPIO ports which need to occupy the main chip are large, in addition, the divider resistors need to be added, MOSFET switching tubes are large, and the required voltage order is large, the calculation of the divider resistor value becomes more complex, and the voltage divider circuit is only suitable for the technical scheme with few output voltage orders.

In view of this, as shown in fig. 1, the present embodiment provides a variable output voltage control apparatus based on duty modulation, including: the pulse width modulation circuit comprises an input control module 1, a pulse width modulation module 2 and an output control module 3, wherein the pulse width modulation module 2 comprises a pulse width modulation chip 201, a first logic gate 202 and a second logic gate 203, an input signal is connected to a reference input end REFIN of the pulse width modulation module 2 through the input control module 1, the pulse width modulation module 2 is connected to the output control module 3 through the first logic gate 202 and the second logic gate 203 respectively, and the output control module 3 is further connected to a feedback end FB of the pulse width modulation module 2.

As shown in fig. 1, the output control module 3 of this embodiment includes a first switch tube 301, an inductor 302, a capacitor 303, and a second switch tube 304, the first logic gate 202 is respectively connected to the first switch tube 301 and one end of the inductor 302, the first switch tube 301 is connected to a power supply terminal Vin, the second logic gate 203 is connected to one end of the inductor 302 through the second switch tube 304, and the other end of the inductor 302 is grounded through the capacitor 303. One end of the inductor 302 close to the voltage output terminal Vout is connected to the feedback terminal of the pwm module 2.

As shown in fig. 1, the input control module 1 of the present embodiment is preferably a hierarchical input module based on space-to-space ratio modulation. The stepped input module comprises a resistor R1, a capacitor 303C1, a resistor R2, a resistor R3, a resistor R4 and a resistor R5, wherein the resistor R1 is respectively connected with one end of the capacitor 303C1 and a connection node A of the resistor R2 and the resistor R3, the resistor R2 is connected to a reference voltage end Vref, the other end of the capacitor 303C1 is grounded, the resistor R3 is far away from one end of the resistor R2 and is grounded through the resistor R4 and the resistor R5, and a connection node B of the resistor R3 and the resistor R4 is connected to a reference input end REFIN of the pulse width modulation module 2. The stepped input module of this embodiment further preferably includes a pulse width modulation buffer, and an output terminal of the pulse width modulation buffer is connected to the resistor R1. The pulse width modulation buffer is referred to as PWM buffer shown in fig. 1.

The voltage of the reference voltage terminal Vref in this embodiment is preferably 2V. The starting voltage of the variable output voltage control means is preferably 0.8V.

The circuit working principle and description of the embodiment are as follows: the pulse width modulation buffer (PWM buffer) of this embodiment has 3 operating states, i.e., high level output, low level output, and high impedance output. When the PWM input is high, the output of the PWM buffer is 2V (Vref supply); when the PWM input is at a low level, the output of the pulse width modulation buffer is 0V; when the PWM input is flowing, the output of the PWM buffer is in a high impedance state. VREFIN can be calculated by using the superposition theorem, and the specific calculation formula is shown in the following figure, wherein D is the duty ratio of the PWM input, when the PWM input inputs a square wave with the duty ratio of D, the PWM buffer is equivalent to an independent voltage source outputting D × Vref, and the voltage of the node a is the voltage of D

The voltage at node B can be calculated by VA (R4 + R5)/(R3 + R4+ R5), so the reference input VREFIN is calculated as follows:

VREFIN generated when a separate voltage source of the reference voltage terminal Vref inside the voltage chip is used for the node B is

Then according to the superposition theorem, for any linear circuit, the voltage of any branch is equal to the algebraic sum of the voltages generated by the independent power supplies acting on the branch independently, so the VREFIN voltage calculation formula is as follows

When the main chip needs to output voltage from the range of 0.6V-1.3V, the output voltage can be adjusted. At the moment of power-on, when the GPIO port of the main chip is not initialized, the PMM control signal cannot be output, so that the boot voltage of 0.8V, i.e., the start voltage, is preset in this embodiment. After the GPIO port of the main chip is initialized, a PWM signal can be output, and the output voltage needs to be regulated according to the duty ratio output by the GPIO PWM. The starting voltage is firstly calculated, and at the moment of power-on, the pulse width modulation buffer outputs a high-resistance state. For simplifying the calculation parameters, the present embodiment assumes that the resistor R5=0 ohms, so that only the parallel relationship of the resistor R1, the resistor R2, the resistor R3, and the resistor R4 needs to be calculated, and Vboot = Vrefin = Vref × R4/(R2 + R3+ R4). Preferably, R1=6.19K Ω, R2=20.5K Ω, R3=4.32K Ω, R4=16.8K Ω, R5=0 ohm, vboot =0.8V; to reduce the input ripple voltage of Vrefin, the capacitance C1 may be filtered with a capacitance of 4.7nf 1uv. Vrefin is the voltage of the reference input terminal REFIN, and when the PWM input duty ratio is 0, the Vrefin =0.3V is calculated according to the calculation formula of Vrefin derived from the above superposition theorem; when the PWM input duty ratio is 100%, calculating according to the calculation formula of the Vrefin, wherein the Vrefin =1.3V; when the PWM input duty ratio is 0% -100%, vrefin = can be adjusted between 0.3V and 1.3V, and the voltage order of adjustment can be preset and adjusted according to actual conditions and requirements. The above description is for explaining the circuit principle shown in fig. 1, and the present application is to protect the technical solution of such a hardware module and its circuit shown in fig. 1.

Therefore, the embodiment can realize adjustable control of the output voltage only through one GPIO port and the pulse width modulation buffer through optimized hardware module design, has simple and efficient overall structure design, simple and convenient control and low cost, is not limited to the protocol interface with the special voltage adjustment of the main chip and the power chip, does not need a plurality of GPIO ports, and further improves the general performance and the flexible application degree of the product well.

The above-mentioned embodiments are preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, and the scope of the present invention includes but is not limited to the above-mentioned embodiments, and all equivalent variations made according to the shape and structure of the present invention are within the protection scope of the present invention.

Claims

1. A duty-cycle modulation based variable output voltage control apparatus, comprising: the pulse width modulation module comprises a pulse width modulation chip, a first logic gate and a second logic gate, an input signal is connected to a reference input end of the pulse width modulation module through the input control module, the pulse width modulation module is connected to the output control module through the first logic gate and the second logic gate respectively, and the output control module is further connected to a feedback end of the pulse width modulation module.

2. The duty cycle modulation-based variable output voltage control device according to claim 1, wherein the output control module comprises a first switch tube, an inductor, a capacitor and a second switch tube, the first logic gate is respectively connected to the first switch tube and one end of the inductor, the first switch tube is connected to a power supply end, the second logic gate is connected to one end of the inductor through the second switch tube, and the other end of the inductor is grounded through the capacitor.

3. The duty cycle modulation based variable output voltage control device of claim 2, wherein one end of the inductor near the voltage output end is connected to the feedback end of the pulse width modulation module.

4. The duty cycle modulation-based variable output voltage control device according to any one of claims 1 to 3, wherein the input control module is a fractional input module based on space-to-duty modulation.

5. The duty cycle modulation-based variable output voltage control device according to claim 4, wherein the stepped input module comprises a resistor R1, a capacitor C1, a resistor R2, a resistor R3, a resistor R4 and a resistor R5, the resistor R1 is respectively connected to one end of the capacitor C1 and a connection node a of the resistor R2 and the resistor R3, the resistor R2 is connected to a reference voltage end, the other end of the capacitor C1 is grounded, one end of the resistor R3 away from the resistor R2 is grounded through the resistor R4 and the resistor R5, and a connection node B of the resistor R3 and the resistor R4 is connected to the reference input end of the pulse width modulation module.

6. The duty cycle modulation based variable output voltage control device according to claim 5, wherein the stepped input module further comprises a pulse width modulation buffer, an output terminal of the pulse width modulation buffer being connected to the resistor R1.

7. The duty cycle modulation-based variable output voltage control device according to claim 5, wherein the voltage of the reference voltage terminal is 2V.

8. The duty cycle modulation-based variable output voltage control device according to any one of claims 1 to 3, wherein a start voltage of the variable output voltage control device is 0.8V.