CN109375757A - Circuit, computing equipment and task processing system - Google Patents
Circuit, computing equipment and task processing system Download PDFInfo
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- CN109375757A CN109375757A CN201811463019.4A CN201811463019A CN109375757A CN 109375757 A CN109375757 A CN 109375757A CN 201811463019 A CN201811463019 A CN 201811463019A CN 109375757 A CN109375757 A CN 109375757A
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- 238000012545 processing Methods 0.000 title claims abstract description 16
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 238000004891 communication Methods 0.000 claims description 14
- 238000004364 calculation method Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000001914 filtration Methods 0.000 claims 1
- 230000008054 signal transmission Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 18
- 230000009286 beneficial effect Effects 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 238000003860 storage Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
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- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000004520 electroporation Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The invention discloses a circuit, a computing device and a task processing system, which are used for increasing the number of chips under the condition of not increasing power supply voltage so as to improve the computing power of the computing device. The circuit comprises: a core power supply for supplying power to the circuit; n series chip groups, wherein each chip group comprises m parallel chips. By adopting the circuit provided by the invention, n chip groups are connected in series in the circuit, and each chip group comprises m chips connected in parallel, so that m chips can be integrated on each node in the series circuit, and the number of the chips is increased under the condition of not increasing the power supply voltage, thereby improving the computing power of the computing equipment.
Description
Technical field
The present invention relates to electroporation field, in particular to a kind of circuit calculates equipment and task processing system.
Background technique
With the development of the times, calculating task is higher and higher for the calculation force request for calculating equipment.It is wanted to meet calculation power
It asks, usually multiple chips is integrated in same calculating equipment, centrally connected power supply is carried out to chip by concatenated mode.
Multiple chips part in series solves the problems, such as that calculating equipment calculates power, and still, chip chamber series connection still has some ask
Topic: for example, chip-in series number is more, it is necessary to higher supply voltage, to meet the operating voltage of each chip, so,
Integrated chip should not be excessive.Therefore it provides a kind of circuit, to increase chip in the case where not increasing supply voltage
Quantity is a technical problem urgently to be resolved to improve the calculation power for calculating equipment.
Summary of the invention
The present invention provides a kind of circuit, calculates equipment and task processing system, to the case where not increasing supply voltage
Under, increase the quantity of chip, to improve the calculation power for calculating equipment.
The present invention provides a kind of circuit, comprising:
Core power, for powering for the circuit；
N series chip group includes the chip of m parallel connection in each chipset.
The beneficial effects of the present invention are: n chipset of connecting in circuit, each chipset include m chip in parallel,
Therefore, in the series circuit, m chip can be integrated on each node, therefore, in the case where not increasing supply voltage,
The quantity of chip is increased, and then improves the calculation power for calculating equipment.
In one embodiment, each chipset is connected at least one peripheral circuit.
The beneficial effect of the present embodiment is: each chipset can share the same peripheral circuit, be equivalent to m chip
The same peripheral circuit can be shared, therefore, saves cost.
In one embodiment, the peripheral circuit includes:
Clock power carries out clock control for the communication to each group chip and chip chamber；
Signal transmits power supply, for the signal communication between the signal communication and adjacent chips group between each group chip
Power supply.
The beneficial effect of the present embodiment is: clock control is carried out to the communication of each group chip and chip chamber, so as to
Enough make to keep synchronous with the signal transmitted between the signal and chipset transmitted between group chip.
In one embodiment, the peripheral circuit further includes signal wire, is connected between each adjacent chips group, for for
Each adjacent chips group transmits signal.
The beneficial effect of the present embodiment is: signal is transmitted by signal wire, without being returned by chip itself,
Chip loss is reduced, the duration of signal transmission is reduced.
In one embodiment, the circuit further include:
The relevant signal of calculating task for receiving the signal of the 1st chipset transmission, and is sent to n-th by control panel
A chipset；Wherein, the 1st chipset is the chipset closest to power supply one end, and n-th of chipset is the core closest to ground terminal
Piece group.
In one embodiment, the circuit further include:
Barrier assembly is connected to the 1st between chipset and the control panel, for the 1st chipset to be sent to institute
The signal for stating control panel is isolated.
In one embodiment, the circuit further include:
Booster circuit is connect with the core power, for core power to boost, to meet the 1st chipset
Required voltage when signal transmits between control panel.
In one embodiment, the circuit further include:
Power filter plate is connected between the core power and the 1st chipset, for the electricity to core power
Source is filtered, and the power supply after being filtered is supplied to the 1st chipset.
It is described to calculate the circuit that equipment includes any of the above-described embodiment the present invention also provides a kind of calculating equipment.
In one embodiment, the calculating equipment further include:
Preset number fan, for radiating for n chipset in the circuit；
Shell, for encapsulating the circuit and the fan.
The present invention also provides a kind of task processing system, the task processing system includes:
Calculate equipment；
Task server for issuing calculating task to the calculating equipment, and receives the institute of the calculating equipment feedback
State the calculated result of calculating task.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by written explanation
Specifically noted structure is achieved and obtained in book, claims and attached drawing.
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, with reality of the invention
It applies example to be used to explain the present invention together, not be construed as limiting the invention.In the accompanying drawings:
Figure 1A is a kind of structural schematic diagram of circuit in one embodiment of the invention；
Figure 1B is clock power 13 and signal transmits the schematic diagram that both power supplys 14 are connect with chip in chipset respectively；
Fig. 1 C is clock power 13 and signal transmits the schematic diagram that both power supplys 14 are connect with chip in chipset respectively；
Fig. 1 D is clock power 13 and signal transmits the schematic diagram that both power supplys 14 are connect with chip in chipset respectively；
Attachment structure schematic diagram when Fig. 1 E is 12 both ends of chipset incoming clock power supplys 13 and signal transmission power supply 14；
Attachment structure schematic diagram when Fig. 1 F is 12 both ends of chipset incoming clock power supplys 13 and signal transmission power supply 14；
Fig. 2 is electrical block diagram when control panel 15 is connect with external server 21 in one embodiment of the invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
In the present invention, since the structure of each chipset, chip, clock power is identical, introducing the present invention
When, mutually isostructural component is indicated using same drawing reference numeral.
Figure 1A is a kind of structural schematic diagram of circuit in one embodiment of the invention, which specifically includes with lower component:
Core power 11, for powering for the circuit；
N series chip group 12 includes the chip 121 of m parallel connection in each chipset 12.
In the present embodiment, circuit includes core power 11, which provides work institute for the chip 121 in circuit
Need voltage.It further include n concatenated chipsets 12 in the circuit, each chipset 12 includes m chip 121 in parallel.
For example, the core calculations logic required voltage of chip is 0.4V, due to the chip in each chipset 12
121 be it is in parallel, then each chipset 12 close to power supply one end and one end closely voltage difference be 0.4V.Therefore, when
When the voltage of power supply is 4V, then the voltage at the 1st 12 both ends of chipset is 4V and 3.6V, the voltage at second 12 both ends of chipset
For 3.6V and 3.2V, and so on, it can be deduced that, the work when supply voltage is 4V, after 10 chipsets series connection can be met
Voltage.
Based on above-mentioned example it is found that when supply voltage is 8V, then it can meet the operating voltage after 20 chipsets are connected.
Similarly, the operating voltage when supply voltage is 12V, then after can meeting 30 chipset series connection.
It is only used for it will be appreciated by persons skilled in the art that Figure 1A is shown in the concatenated scheme of 4 chipsets 12
It explains the present invention, is not intended to restrict the invention, in the present invention, the value of chipset number n is by the electricity of core power 11
Pressure determine, the voltage of core power 11 is higher, can concatenated chipset number it is more.In above-mentioned example, core power 11
The numerical value of voltage, the number of chipset 12 and each chip core calculations logic required for voltage numerical value, be
For clearer statement the intent of the present invention, rather than the limitation present invention, those skilled in the art are implementing institute of the present invention
When disclosed technical solution, can according to actual needs the numerical value of the voltage to core power 11, chipset 12 number and
The numerical value of voltage required for the core calculations logic of each chip is adjusted.
The beneficial effects of the present invention are: n chipset 12 of connecting in circuit, each chipset 12 include m in parallel
Therefore chip 121 in the series circuit, can integrate m chip 121 on each node, therefore, do not increasing power supply electricity
In the case where pressure, the quantity of chip 121 is increased, and then improves the calculation power for calculating equipment.
In one embodiment, each chipset 12 is connected at least one peripheral circuit.
The beneficial effect of the present embodiment is: each chipset 12 can share the same peripheral circuit, be equivalent to m core
Piece 121 can share the same peripheral circuit, therefore, save cost.
In one embodiment, the peripheral circuit includes:
Clock power 13 carries out clock control for the communication to each chipset and chip chamber；
Signal transmits power supply 14, logical for the signal between the signal communication and adjacent chips group between each group chip
Letter power supply.
In the present embodiment, peripheral circuit includes clock power 13, which is used to control chipset 12 and group
The frequency and phase of signal between interior chip 121, to make same organize between chip 121 between the signal transmitted and chipset 12
Signal keeps synchronizing.In addition, clock power 13 can also be used in the power supply of chip internal clock frequency multiplication and logic unit.And signal transmits
Power supply 14 is for the signal communication power supply between the signal communication and adjacent chips group between each group chip.
Clock power 13 is not specifically given in Figure 1A and signal transmission power supply 14 is specifically how to carry out with each group chip
Connection, in the following, providing clock power 13 and signal transmission power supply 14 and each group by Figure 1B, Fig. 1 C, Fig. 1 D, Fig. 1 E and Fig. 1 F
The specific connection type of chip, and in conjunction with attached drawing introduce clock power 13 and signal transmission power supply 14 specific power supply mode.
Clock power 13 and signal transmission power supply 14 use following three kinds of power supply modes:
Mode one
As shown in Figure 1B, clock power 13 and signal transmission power supply 14 pass through the institute into chipset respectively of Liang Tiao power supply line
There is chip to be powered, this two supply lines pass through the inside of all chips in chipset.
It is powered using aforesaid way one, since supply lines is laid in chip interior, so supply lines is not take up additional sky
Between, more chips can be laid in limited circuit board.Also, supply lines is hidden in chip interior, can also be certain
It avoids damaging in degree.
Mode two
As shown in Figure 1 C, clock power 13 connects the input of first chip in left side with the output end of signal transmission power supply 14
End is first chip power supply, and the input terminal of second chip in output end connection left side of first chip, is second chip
It is powered, and so on, m chip is sequentially connected in chipset, is transmitted power supply 14 by clock power 13 and signal and is powered.
Employing mode two is powered, and the chip in chipset is made to join end to end, can be the case where not laying supply lines
Under normally receive clock power 13 and signal transmission power supply 14 power supply, to further save cost.
Mode three
As shown in figure iD, clock power 13 connects a power bus, in chipset m chip all with 13 institute of clock power
The power bus of connection is connected, and signal transmission power supply 14 connects another power bus, in chipset m chip also all with signal
The power bus that power supply 14 connects is transmitted to be connected.
Employing mode three is powered, and power bus is laid in outside chip, when route damage occurs in power bus, is easy to
Maintenance and replacement.
Fig. 1 E be and Fig. 1 F be 12 both ends of chipset all incoming clock power supplys 13 and signal transmission power supply 14 when structure show
It is intended to.
Wherein, Fig. 1 E is that 12 both ends of chipset all incoming clock power supplys 13 and signal transmit power supply when pass-through mode one is powered
Structural schematic diagram when 14, Fig. 1 F are 12 both ends of chipset incoming clock power supplys 13 and signal transmission when pass-through mode two is powered
Structural schematic diagram when power supply 14.
When the core number in chipset 12 is more, only it is possible to can not meet chip in side incoming clock power supply 13
The power demands of interior logic unit similarly only are possible to can not meet inter-chip signals in side access signal transmission power supply 14
The power demands of communication therefore can be by scheme shown in Fig. 1 E and Fig. 1 F, in both-end all incoming clock electricity of chipset 12
Source 13 and signal transmit power supply 14.
It is double in the case that Fig. 1 E and Fig. 1 F are only shown above by the power supply of both power supply modes of mode one and mode two
Structural schematic diagram when end connection clock power 13 and signal transmission power supply 14, it will be appreciated by persons skilled in the art that
When core number in chipset 12 is more, aforesaid way three can also be using both-end connection clock power 13 and signal transmission electricity
Source 14, this will not be repeated here.
The beneficial effect of the present embodiment is: the clock when communication between each chipset 12 and organizing interior chip 121 carries out
System, it is synchronous with the signal holding transmitted between the signal and chipset 12 that transmit between chip 121 is organized so as to make.
In one embodiment, the peripheral circuit further includes signal wire 15, is connected between each adjacent chips group 12, is used
In for each adjacent chips group 12 transmit signal.
In the present invention, there are three voltage domains, respectively correspond different functions, for example, voltage domain A, B and C, voltage domain A
It is 0.75V for 1.8V, voltage domain B, voltage domain C is 0.35-0.4V, and the voltage of voltage domain A is suitable for the voltage of signal wire 15, letter
When the voltage of number line 15 is 1.8V, the redundancy of signal transmission can be enhanced, anti-interference ability is stronger when signal transmits, and is not easy out
It is wrong；The voltage of voltage domain B is suitable for the voltage of clock power 13, when 13 voltage of clock unit is 0.75V, can reduce logic electricity
The loss on road, and can be instruction, data and clock pass to the core circuit of chip interior.The voltage of voltage domain C is suitable for
The operating voltage of the core circuit of chip interior can be with when the operating voltage of the core circuit of chip interior is 0.35V-0.4V
The power consumption of chip, the calculating power and power dissipation ratio being optimal are reduced to greatest extent.
When signal to be transferred to inside voltage from signal wire, need for signal voltage to be reduced to 0.35V-0.4V, still,
Voltage is directly reduced to extremely low voltage (0.35V-0.4V) is relatively difficult, and therefore, clock power 13 can also be played from 1.8V
The signal for the 1.8V that signal wire 15 transmits can be transformed into 0.75V in time, is then reduced to again from 0.75V by Link role
0.35V or so calculates circuit communication to adapt to chip core scheming.
It will be appreciated by persons skilled in the art that in above-mentioned example, for value (the i.e. signal wire of voltage domain A, B and C
The value of the operating voltage of the core circuit of 15 voltage value, the voltage value of clock power 13 and chip interior), be
For clearer statement the intent of the present invention, rather than the limitation present invention.
The beneficial effect of the present embodiment is: signal is transmitted by signal wire 15, without being carried out by chip 121 itself
Passback reduces the loss of chip 121, reduces the duration of signal transmission.
In one embodiment, the circuit further include:
Control panel 16 for receiving the signal of the 1st chipset 12 transmission, and the relevant signal of calculating task is sent to
N-th of chipset 12；Wherein, the 1st chipset 12 is the chipset closest to power supply one end, and n-th of chipset 12 is most to connect
The chipset of near end.
In the present embodiment, control panel 16 is used to receive the signal of first chipset 12 transmission, and calculating task is related
Signal be sent to n-th of chipset 12, the 1st signified chipset 12 is the chip closest to power supply one end in the present invention
Group, and n-th of chipset 12 is the chipset closest to ground terminal.
In one embodiment, the circuit further include:
Barrier assembly 17 is connected to the 1st between chipset 12 and the control panel 16, is used for the 1st chipset 12
The signal for being sent to the control panel 16 is isolated.
Provided integrated chip scheme, scheme provided by the present invention can significantly save material compared with the existing technology
Material, in the following, proving this conclusion by specific example:
For example, 16 chips are integrated:
Existing Integrated Solution:
If core power can satisfy 4 chip-in series, 4 series circuits are needed, each chip needs outside one
Circuit is enclosed, finally, every series circuit output signal will be transmitted separately to control panel, 4 series circuits need 4 isolation again
Component.As it can be seen that needing 4 core powers, 16 peripheral circuits and 4 barrier assemblies according to existing Integrated Solution.
Integrated Solution of the invention:
The case where connecting a peripheral circuit according to each chipset, same core power can satisfy 4 chipsets
It connects, 4 chips in parallel is needed in each chipset, each chipset uses the same peripheral circuit, outer therefore, it is necessary to 4
Circuit is enclosed, due to there was only a series circuit, the signal recently entered is transmitted to control panel i.e. by an isolation circuit
It can.Therefore, according to Integrated Solution provided by the present invention, 1 core power, 4 peripheral circuits and 1 isolation group are needed
Part.The number of required core power, peripheral circuit and barrier assembly is the 1/4 of the prior art, therefore can significantly be saved
About cost.
Fig. 2 is electrical block diagram when control panel 16 is connect with task server 21 in one embodiment of the invention.This
In invention, when control panel 16 receives the calculating task that task server 21 issues, according to preset task distribution policy, determine
Which chipset is task is distributed to.
Since control panel 16 is connected with the 1st chipset 12 and n-th of chipset 12, when carrying out task distribution,
Task can be sent to the 1st or n-th of chipset 12 first, be then transmitted to by the 1st or n-th of chipset 12 corresponding
Chipset 12.
For example, control panel 16 after receiving the calculating task that task server 21 issues, is distributed according to preset task
Calculating task is divided into three subtasks a, b and c, also, subtask a is distributed to n-th of chipset 12 by strategy, will be sub
Task b is distributed to (n-1)th chipset 12, and subtask c is distributed to the n-th -2 chipsets 12, then control panel 16 needs to divide
Subtask a, b and c after cutting are sent to n-th of chipset 12 by signal wire 15, and then n-th of chipset 12 passes through signal wire
Subtask b and c are sent to (n-1)th chipset 12 by 15, and (n-1)th chipset 12 is sent subtask c by signal wire 15
To the n-th -2 chipsets 12.In addition, receiving the chipset 12 of subtask also can be sent to group for subtask by signal wire 15
Interior chip 121 can also carry out subtask further specifically, subtask can be sent to any chip 121 in group
The multiple chips 121 being distributed to after segmentation in group.
After n-th of chipset 12 completes subtask a, the calculated result of subtask a is sent to (n-1)th chipset
12, (n-1)th chipset 12 is sent to n-th-after the calculated result for receiving subtask a, by the calculated result of subtask a
2 chipsets 12, and so on, until being sent to the 1st chipset 12.After subtask b and subtask c is completed, also by
Calculated result is sent to the 1st chipset 12 by aforesaid way.
After first chipset 12 receives the calculated result of subtask a, b and c, to the calculated result of subtask a, b and c
Calculated result summarized, to obtain the summarized results of calculating task, and summarized results is sent to by signal wire 15
Barrier assembly 17.After barrier assembly 17 receives the summarized results, which is sent to control panel 16.
Control panel 16 is sent to task server 21 when receiving the summarized results, by the summarized results.
In one embodiment, the circuit further include:
Booster circuit 18 is connect with the core power 11, for core power 11 to boost, to meet the 1st
Required voltage when signal transmits between chipset 12 and control panel 16.
For example, when core voltage is 12V, the voltage of the 1st chipset 12 close to ground terminal side is 11.6V, and
The voltage of signal wire 15 itself is 1.8V, and therefore, the 1st voltage between chipset 12 and barrier assembly 17 is 11.6V+1.8V
=13.4V, therefore, more than the voltage of core power 11, in order to meet the 1st transmission of signal between chipset 12 and control panel 16
The voltage of Shi Suoxu needs to boost to core power 11 by booster circuit 18.
In one embodiment, the circuit further include:
Power filter plate 19 is connected between the core power 11 and the 1st chipset 12, for core electricity
The power supply in source 11 is filtered, and the power supply after being filtered is supplied to the 1st chipset 12.
The present invention also provides a kind of calculating equipment, the circuit that equipment includes any of the above-described embodiment is calculated.
In one embodiment, equipment is calculated further include:
Preset number fan, for radiating for n chipset in circuit；
Shell, for encapsulating circuit and fan.
In the present embodiment, circuit and fan are packaged by shell, then by interface holes by circuit and fan
Each external interface discloses.So that external power supply power supply can be received by these external interfaces by calculating equipment, with external equipment
Carry out data interaction etc..The Interface design of the present embodiment shell can refer to the design of existing block chain number supercomputer equipment.
The present invention also provides a kind of task processing systems, as shown in Fig. 2, task processing system includes:
Calculate equipment；
Task server 21 for issuing calculating task to calculating equipment, and receives the calculating task for calculating equipment feedback
Calculated result.
In calculating equipment, comprising the circuit in above-described embodiment, and calculating the control panel 16 in equipment is for receiving
The calculating task of the publication of task server 21, each chipset being distributed to calculating task in circuit are sent out by first chipset
All calculated results are finally fed back to task server 21 by the calculated result for sending all chips to send.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The shape for the computer program product implemented in usable storage medium (including but not limited to magnetic disk storage and optical memory etc.)
Formula.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (11)
1. a kind of circuit characterized by comprising
Core power, for powering for the circuit；
N series chip group includes the chip of m parallel connection in each chipset.
2. circuit as described in claim 1, which is characterized in that each chipset is connected at least one peripheral circuit.
3. circuit as claimed in claim 2, which is characterized in that the peripheral circuit includes:
Clock power carries out clock control for the communication to each group chip and chip chamber；
Signal transmits power supply, supplies for the signal communication between the signal communication and adjacent chips group between each group chip
Electricity.
4. circuit as claimed in claim 2, which is characterized in that the peripheral circuit further includes signal wire, is connected to each adjacent
Between chipset, for transmitting signal for each adjacent chips group.
5. circuit as claimed in claim 1 or 2, which is characterized in that the circuit further include:
The relevant signal of calculating task for receiving the signal of the 1st chipset transmission, and is sent to n-th of core by control panel
Piece group；Wherein, the 1st chipset is the chipset closest to power supply one end, and n-th of chipset is the chip closest to ground terminal
Group.
6. circuit as claimed in claim 5, which is characterized in that the circuit further include:
Barrier assembly is connected to the 1st between chipset and the control panel, for the 1st chipset to be sent to the control
The signal of making sheet is isolated.
7. circuit as claimed in claim 5, which is characterized in that the circuit further include:
Booster circuit is connect with the core power, for core power to boost, to meet the 1st chipset and control
Required voltage when signal transmits between making sheet.
8. such as the described in any item circuits of claim 1-7, which is characterized in that the circuit further include:
Power filter plate is connected between the core power and the 1st chipset, for the power supply to core power into
Row filtering, and the power supply after being filtered is supplied to the 1st chipset.
9. a kind of calculating equipment, which is characterized in that the calculating equipment includes such as the described in any item circuits of claim 1-8.
10. calculating equipment as claimed in claim 9, which is characterized in that the calculating equipment further include:
Preset number fan, for radiating for n chipset in the circuit；
Shell, for encapsulating the circuit and the fan.
11. a kind of task processing system, which is characterized in that the task processing system includes:
It is as claimed in claim 9 to calculate equipment；
Task server for issuing calculating task to the calculating equipment, and receives the meter of the calculating equipment feedback
The calculated result of calculation task.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811463019.4A CN109375757A (en) | 2018-12-03 | 2018-12-03 | Circuit, computing equipment and task processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811463019.4A CN109375757A (en) | 2018-12-03 | 2018-12-03 | Circuit, computing equipment and task processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109375757A true CN109375757A (en) | 2019-02-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811463019.4A Pending CN109375757A (en) | 2018-12-03 | 2018-12-03 | Circuit, computing equipment and task processing system |
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