CN110007150A - A kind of linear ratio phase method of Direct Digital Phase Processing - Google Patents
A kind of linear ratio phase method of Direct Digital Phase Processing Download PDFInfo
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- CN110007150A CN110007150A CN201910243847.5A CN201910243847A CN110007150A CN 110007150 A CN110007150 A CN 110007150A CN 201910243847 A CN201910243847 A CN 201910243847A CN 110007150 A CN110007150 A CN 110007150A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
Abstract
The invention discloses a kind of linear ratio phase methods of Direct Digital Phase Processing, without using frequency transformation auxiliary circuit, but in turn avoid usual sinusoidal signal waveform for the non-linear distortion of Phase Processing.The periodicity and its wave character of frequency signal phase variation is utilized, the ratio of period all phase variation range is mutually expired according to the linearity range accounting of sinusoidal signal, selecting clock signal is n times for comparing signal respective frequencies.This ensures that always there is a job in the linearity range of signal in continuous n clock signal together.The phase resolution of this method can be even higher better than ps magnitude, can cover day or more always, it can be achieved that the frequency stability measurement of ns magnitude sample time and control etc. since the radio-cycle of signal, and for a long time than the response time mutually with measurement frequency.This method is suitable for the digitized phase between the nominal value signal of optional frequency and measures and compare, and many performances are better than international universally recognized double mixed time difference DMTD.
Description
Technical field
The invention belongs to Radio Measurement field and chronometer time frequency measurement and control, especially a kind of Direct Digitals
The linear ratio phase method of Phase Processing.
Background technique
The linear ratio phase method of Direct Digital Phase Processing is for Frequency Standard Comparison, the high-acruracy survey of phase change detection
Method.Currently, prior art believes two comparisons using gate circuit or integrated circuit trigger when solving the problems, such as that phase is compared
Number direct phase demodulation, if U.S. HpK34-59991A is than phase instrument, this scheme is there is poor linearity, adjustment is inconvenient and in high frequency
It is lower than Xiang Shiyou " dead zone " and the defect of non-linear phenomena.3.986,113 patent of the U.S. uses the side of double mixer width phase detection
Case, though making moderate progress to the linearity and " dead zone ", there are still the measurement accuracy of phase comparator it is related to frequency nominal value and
Low frequency is lower than phase precision and auxiliary common oscillator frequency must make the deficiency of different changes in not year-on-year phase frequency rate value.
The linear phase of analog form, which compares instrument, still has shortcoming in terms of drifting about with phase resolution, in particular for complexity
The variation of its phase difference is difficult to the case where recovering the actual phase variation of measured signal between frequency signal.
Best double mixer time difference measurement method (DMTD) is generally acknowledged in the world at present, it is either simulating or number
DMTD method has very high Measurement Resolution really.But the method that this method uses beat, doubled in error
The view of time difference measurement is greatly reduced simultaneously in versus frequency, also just reduces the shorter sample time frequency stability of measurement in this way
Short-term and transient state ability.For example, DMTD method introduces the multiplication effect of measurement by the method for double mixing, while reducing again
Measurement frequency being such as usually reduced to several hundred Hz from the 10MHz frequency compared originally by mixing.In this way in the comparison of terminal
The frequency stability for being longer than the ms time can only just be measured.And there are time lag issues for DMTD method.DMTD method includes mixed
Frequently, the links such as filtering, amplification, counting, the real-time of processing are greatly affected.Although and DMTD and other methods have
There is very high resolution ratio, but the device is complicated, cost is high, applies and is restricted in control.
To sum up, the defect of method or deficiency specifically include that at this stage
1, the measurement response time is slow, short-term comparison time can only achieve ms grades；
2, mutually make an uproar, long term drift it is larger, long-term stability is insufficient；
3, the device is complicated, and cost is high, using being restricted；
Summary of the invention
The technical problem to be solved by the present invention is to propose a kind of linear ratio phase technology of Direct Digital Phase Processing, utilize
ADC acquires linearly area as phase-detecting section, realizes that high-resolution phase is compared and handled.
To achieve the goals above, the present invention, which adopts the following technical scheme that, is resolved:
A kind of list A/D samples the linear ratio phase method of digital Phase Processing, and selecting clock signal is the corresponding frequency of measured signal
N times of rate guarantees always have a job in the linearity range of signal in continuous n clock signal together in this way, specifically includes
Following steps:
1. keeping original frequency and waveform for signal is compared as measured signal all the way；
2. by another way reference signal by frequency multiplier, frequency expands as n times of measured signal frequency nominal value, each
The clock signal that n reference signal after having frequency multiplication in the measured signal period is sampled as A/D converter, n are positive number；
4. FPGA control A/D converter samples measured signal, and the voltage data of collected linear zone
It is sent into single-chip microprocessor MCU；
5. the voltage data received is converted to the phase difference value of two signals by single-chip microprocessor MCU, and passes through phase difference variable
Change the frequency for calculating measured signal and frequency stability etc..
When clock signal frequency is n times of measured signal frequency, always there is one to go out in every continuous n clock signal together
The linear zone of present measured signal, and be periodically to change in linear zone, a clock signal is due between two signals
Phase change and when moving out linear zone, another clock signal adjacent thereto can be automatically into linear region, Er Qiexiang
The interval of adjacent 2 clock signals is equal to the period of clock signal, i.e. the replacement of clock signal period is that a phase compares
The full period；Wherein n is bigger, and linear zone is narrower, the linearity is better.
A kind of double A/D samples the linear ratio phase method of digital Phase Processing, and two A/D converters shared one high-frequency
Clock signal, frequency values are equal to the common multiple numerical value of measured signal and reference signal frequency, specifically includes the following steps:
1. an A/D converter will be inputted measured signal all the way；
2. choosing reference signal identical with measured signal frequency nominal value inputs another A/D converter；
3. the common multiple frequency for choosing measured signal and reference signal is believed respectively as the sampling clock of two A/D converters
Number；
4. FPGA controls two A/D converters and samples respectively to the signal respectively inputted, and linear collecting
The voltage data in area is sent into single-chip microprocessor MCU as efficiently sampling value；
5. the voltage data received is respectively converted into the phase difference between measured signal and reference signal by single-chip microprocessor MCU
Value, and the frequency stability of the variation calculating measured signal by phase difference value.
Wherein, step 5. in phase difference value calculation method are as follows: collected two efficiently samplings under identical clock
The difference of value is the phase difference value of measured signal and reference signal, then will be and in the clock difference of the efficiently sampling value of acquisition
Increase the corresponding multiple value of corresponding clock cycle on the basis of phase difference value.
Advantages of the present invention is as follows:
1, this method hardware configuration is simple, at low cost, high resolution.Phase resolution can be better than ps magnitude even more
Height directly acquires the phase data of linear zone, avoids linear distortion of the usual sinusoidal signal waveform for Phase Processing, no frequency
Rate translation circuit, processing directly, can significantly reduce drift and circuit noise.
2, actual than in phase, if clock signal frequency multiplication is to 100MHz or higher, the phase obtained in this way is compared
The full period be 10ns.And the full scale value of A/D conversion corresponds to this 10ns, so in the case where 16 A/D are converted, energy
It accesses close to 1 × 10-13Resolution ratio.
3, can be since the radio-cycle of signal than the response time of phase and measurement frequency, and cover day always for a long time
Above, it can be achieved that the frequency stability measurement of ns magnitude sample time and control etc..
4, the present invention is measured not only for linear phase, can be also used for obtaining for phase information in phase noise measurement
Take and frequency and phase controlling in.
Detailed description of the invention
Fig. 1 is equipment composition figure of the present invention using list A/D；
Fig. 2 is waveform diagram of the present invention using list A/D sampling；
Fig. 3 is the equipment composition figure that the present invention uses double A/D；
Fig. 4 is the waveform diagram that the present invention is sampled using double A/D；
Fig. 5 is the digital phase sample between complex frequency signal of the present invention；
Fig. 6 is the correspondence of comparison curve and clock that linear phase of the present invention compares；
Fig. 7 is self-correcting experimental result of the present invention；
Fig. 8 is the application direction of the method for the present invention.
Specific embodiment
With reference to the accompanying drawings and examples, the invention will be further described.
The present invention gives two schemes, and one is list A/D digitized sampling is used, another kind is using double A/D number
Change sampling.When using list A/D circuit, signal has been to maintain original frequency and waveform, another way signal as tested all the way
By then maintaining more crypto set, frequency after frequency multiplier as clock into n times of sample rate, each of sampled clock signal is taken
Fixed time interval or phase difference variation are also ensured between sample value.For sinusoidal signal, by signal just
Really conditioning, so that it is with standard and stable waveform and amplitude, and samples at intervals.
Referring initially to the equipment composition figure that Fig. 1, Fig. 1 are using list A/D, measured signal had compared signal both with reference signal two
It can be simple frequency relation, and can be complex frequency relationship, specific implementation step is as follows:
1. measured signal 1a keeps original frequency and waveform as tested；
2. by reference signal 3a by frequency multiplier 4a, frequency expands as n times of measured signal frequency nominal value, each quilt
The clock signal that the n reference signal surveyed after having frequency multiplication in the signal period is sampled as A/D converter 2a；
3. FPGA 5a control A/D converter 2a samples measured signal, and the voltage of collected linear zone
Data are sent into single-chip microprocessor MCU 6a；
4. the voltage data received is converted to the phase difference value of two signals by single-chip microprocessor MCU 6a；
ΔTn=φn+1-φn
Δ f and τ are the average times of average frequency deviation and measurement, and Δ T is the change of the phase difference in average time τ
Change amount, V0For the amplitude of reference signal, ε (t) is the deviation in amplitude direction, f0For nominal frequency,For the deviation of phase
Value, t represent the moment, and φ represents angle.Then frequency stability is calculated on this basis:
Wherein, m is sampling number.
Sample waveform figure when Fig. 2 is using list A/D, n=10 (clock signal 100Mhz, measured signal 10Mhz), from figure
In it can be seen that always have the linear zone for appearing in measured signal in per continuous 10 clock signals together, and be
Periodically change in this linear zone.Once this clock signal moves out this due to the phase change between two signals
When a linear zone, another clock signal adjacent thereto can be automatically into this linear region, and due to this 2 clocks letter
Number interval be exactly equal to 10ns, be 100MHz compare signal period, that is, this clock signal periodically replace
Change the completion in the full period that phase also exactly one by one compares.
The method for not having to the processing such as frequency multiplication for the relationship between more convenient guarantee comparison signal and clock, uses
2 A/D converters.
Fig. 3 is the equipment composition figure using double A/D, and it is nominal that measured signal 1b and reference signal 2b two compares signal frequency
It is worth identical.Its specific implementation step is as follows:
1. measured signal 1b is inputted an A/D converter 4b；
2. choosing reference signal 2b identical with measured signal frequency nominal value inputs another A/D converter 5b；
3. the common multiple frequency for choosing measured signal and reference signal is believed respectively as the sampling clock of two A/D converters
Number 3b；
4. FPGA 6b controls two A/D converters and samples respectively to the signal respectively inputted, and handle collects line
Property area voltage data as efficiently sampling value be sent into single-chip microprocessor MCU 7b；
5. the voltage data received is respectively converted into the phase difference of measured signal and reference signal by single-chip microprocessor MCU 7b
Value:
Here, Δ Tfxn、ΔTfoN and Δ Tn is respectively represented with clock signal to the phase difference value of measured signal, used time
Clock signal is to the phase difference between the phase difference value and measured signal and reference signal of reference signal.
And calculate frequency stability:
Reference signal is identical as measured signal frequency nominal value, without using frequency multiplication route, the frequency stability meeting of measurement
More preferably.They share a high-frequency clock signal, and frequency values are equal to the multiple value of 2 comparison signal frequencies.This when
Clock signal simultaneously samples 2 comparison signals, is still that collect the data of the linear zone near 0 degree be efficiently sampling
Value.Because comparing the phase difference variation between signal, the acquisition of 2 efficiently sampling values is not necessarily under identical clock.?
The difference of collected 2 efficiently sampling values is exactly this 2 phase difference values compared between signal under identical clock.And in acquisition
When the clock difference of efficiently sampling value, then the corresponding multiple value of corresponding clock cycle is further added by the basis of difference.
Gamma correction must be taken into consideration in this typical linear phase comparison method, especially effective acquisition zone
When accounting for the large percentage in full period of measured signal.It is next after a clock signal completes primary effective acquisition
Clock signal can again be acquired this linear zone, successively go on, the measurement until completing a full period.At one
Least common multiple is not in identical sampled value in one number time, so all effectively collection points in a full period are pressed
The big apparent linear phase of available one of minispread compares curve, as shown in figure 4, when the linear segment limit chosen is larger
When, in the curve that edge may be deviateed, at this moment need to be modified data processing.
Clock be the phase in the case of measured signal frequency multiple compare and frequency relation complex situations under phase ratio
It is right, although clock has not been that the clock group of clock sequence original in clock ensemble samples to obtain in the switching of digitized clock
Phase data, but the clock group of adjacent another clock sequence of adjacent or according to measured signal voltage value samples
Obtain phase data.The switching of the clock group of the clock sequence of this fixation, when being measured signal frequency multiple for clock
The sampling of the clock group of another adjacent clock sequence, just has the variation of a clock cycle in time relationship, and adopts
The phase data of collection also just has the increase or reduction of a clock cycle.Since the comparison of such phase is with the clock cycle
As the full period (0 degree to 360 degree, or in turn) that phase compares, so next beginning than phase cycle is exactly also
A upper end than phase cycle, for periodic phase compare 0 degree and 360 degree be it is equivalent, ensure that the continuous of phase
Property.
And for A/D, A/D dynamic range and A/D accuracy are often referred to identical content.Dynamic range is defined as
The ratio for the minimum and maximum signal that system can measure.Used bit number when A/D resolution ratio is by digital input signal
It determines.For 16 devices, total voltage range is represented as 21665536 independent digital values or output code.Therefore, system
The absolute minimum levels that can be measured are expressed as the 1/65536 of 1 bit or A/D voltage range.For 16 A/D resolution ratio, by
In there is internal or external error source, actual accuracy may be much smaller than resolution ratio.16 A/D include 216=65536 steps
Rapid or conversion, and least significant bit LSB=VREF/65536=3.3V/65536=50.35 μ V.For ideal A/D, own
Code all has the same widths of 1LSB.If the maximum signal level of A/D is 2.5V, it means that a total of 49652 times turn
Change 2.5V/1LSB.In this case, 65536-49652=15884 conversion will is not used by.After this has reacted conversion
Signal loss of accuracy or ENOB lose 0.4.If A/D increases with reference to the difference between VREF and A/D maximum signal level
Add, then ENOB loss or loss of accuracy will aggravate.For example, if A/D maximum signal level be 1.2V and VREF=3.3V,
So ENOB loss will be 1.5.Therefore A/D dynamic range has to matching maximum signal amplitude, to obtain highest accuracy.
Fig. 5 is the digital phase sample between complex frequency signal, in TminAlthough phase change between middle signal is non-company
Continuous property, if but after we rearrange according to monotonicity, the variation for the phase difference that digital collection obtains, stepping-in amount are
Fixed Δ T.Such case is just and with TminFor the similar close to the comparison between frequency value signal of beat value.It therefore, can be for
The sampling and its variation of the arrangement situation of all voltage acquisition data, determine actual phase difference value in least common multiple one number time.
What we wanted value is the linear zone spent from measured signal 0 to 360, is only nearby only accounted for less than the full period at 0 degree
10% very limited linear zone voltage-phase data, as the 4th period approached and the 7th period at 0 point
Close to the position of end cycle.These sample points are all linearity range of the work in measured signal, that is, the virtual value to be chosen
Point.
Set the beginning in fixed full period in specific linearity range processor according to the clock cycle, last bit is set.It presses
Period according to measured signal is interval, and voltage-phase difference value of the clock acquisition fallen in this specific linearity range area is that have
Imitate phase difference value.Once the clock has gone out this specific linearity range area, preceding or another adjacent clock signal thereafter
Just this region has been fallen in.Out, the alternative site that the clock into this specific linearity range area occurs is different, this is with regard to phase
The phase of 0 to 360 degree is compared, from 0 degree, region, another clock then enter from 360 degree a clock out, it is also possible to anti-mistake
Come.The acquisition of this data is suitable for long-term and short run target measurement.Fig. 6 is the explanation of this work, it should be noted that
When two comparison signals are simple frequency relations, comparison clock when measuring effective phase is continuous；When it is complex frequency
When relationship, clock is discontinuous.
Fig. 7 is frequency stability-curve of 10MHz8607 self-correcting.It can be seen from the figure that system noise floor is 3.93
×10-13/ s can satisfy the measurement request of most of atomic frequency standards and crystal oscillator.
Phase change, frequency, frequency stability, the phase that the method for the present invention can also be further applied to measured signal are made an uproar
The measurement of sound and digitized phaselocked loop, modular frequency-phase controlling device and system etc..Fig. 8 is its application
The explanation in direction.Digitized phase is compared not only for frequency stability measurement, is more for phase noise
Measurement and frequency and phase controlling.It is compared with the measuring technique of current full accuracy, although this method can not be complete
The phase and frequency etc. of continuous measurement and control optional frequency, but it after all can be the letter of various most common Frequency points
Number phase and High-Accuracy Frequency measure, and measure more simple, conveniently.
Claims (4)
1. the linear ratio phase method that a kind of list A/D samples digital Phase Processing, which is characterized in that selection clock signal is tested letter
N times of number respective frequencies guarantees always have a job being tested sinusoidal signal in continuous n clock signal together in this way
Linearity range, specifically includes the following steps:
1. will compare signal as measured signal keeps original frequency and waveform；
2. by reference signal by frequency multiplier, frequency expands as n times of measured signal frequency nominal value, n reference after frequency multiplication
The clock signal that signal is sampled as A/D converter, n are positive number；
3. FPGA control A/D converter samples measured signal, and the voltage data of collected linear zone is sent into
Single-chip microprocessor MCU；
4. the voltage data received is converted to the phase difference value of measured signal and reference signal by single-chip microprocessor MCU, and passes through phase
Potential difference variation calculates the frequency and frequency stability of measured signal.
2. the linear ratio phase method that a kind of list A/D according to claim 1 samples digital Phase Processing, which is characterized in that
When clock signal frequency is n times of measured signal frequency, per continuous n clock signal together in always have one appear in it is tested
The linear zone of signal, and be periodically to change in linear zone, a clock signal becomes due to the phase between two signals
When changing and moving out linear zone, another clock signal adjacent thereto can automatically into linear region, and it is two neighboring when
The interval of clock signal is equal to the period of clock signal, i.e. the replacement of clock signal period is the full period that a phase compares；
Wherein n is bigger, and linear zone is narrower, the linearity is better.
3. the linear ratio phase method that a kind of double A/D samples digital Phase Processing, which is characterized in that two A/D converters share one
A high-frequency clock signal, frequency values are equal to the common multiple numerical value of measured signal and reference signal frequency, specifically include following
Step:
1. measured signal is inputted an A/D converter；
2. choosing reference signal identical with measured signal frequency nominal value inputs another A/D converter；
3. the common multiple frequency of selection measured signal and reference signal is respectively as the sampled clock signal of two A/D converters；
4. FPGA controls two A/D converters and samples respectively to the signal respectively inputted, and collecting linear zone
Voltage data is sent into single-chip microprocessor MCU as efficiently sampling value；
5. the voltage data received is converted to the phase difference between measured signal and reference signal by single-chip microprocessor MCU, and is passed through
Phase difference variation calculates the frequency and frequency stability of measured signal.
4. the linear ratio phase method that a kind of double A/D according to claim 3 samples digital Phase Processing, which is characterized in that
Step 5. in phase difference value calculation method are as follows: the difference of collected two efficiently sampling values is tested letter under identical clock
Number and the phase difference value of reference signal then will be on the basis of phase difference value and in the clock difference of the efficiently sampling value of acquisition
The upper corresponding multiple value for increasing the corresponding clock cycle.
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Cited By (3)
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| CN110988463A (en) * | 2019-11-07 | 2020-04-10 | 西安电子科技大学 | Method for accurately acquiring signal frequency and frequency stability through digital phase comparison |
| CN111628764A (en) * | 2020-05-25 | 2020-09-04 | 河北远东通信系统工程有限公司 | Phase-locked loop based on digital direct linear phase comparison |
| CN111999559A (en) * | 2020-08-28 | 2020-11-27 | 西安电子科技大学 | Digital linear phase comparison method based on double ADCs |
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| CN110988463A (en) * | 2019-11-07 | 2020-04-10 | 西安电子科技大学 | Method for accurately acquiring signal frequency and frequency stability through digital phase comparison |
| CN111628764A (en) * | 2020-05-25 | 2020-09-04 | 河北远东通信系统工程有限公司 | Phase-locked loop based on digital direct linear phase comparison |
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