CN110007150B - Linear phase comparison method for direct digital phase processing - Google Patents

Linear phase comparison method for direct digital phase processing Download PDF

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CN110007150B
CN110007150B CN201910243847.5A CN201910243847A CN110007150B CN 110007150 B CN110007150 B CN 110007150B CN 201910243847 A CN201910243847 A CN 201910243847A CN 110007150 B CN110007150 B CN 110007150B
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周渭
于光运
乔文博
牛希东
李智奇
张立东
王娅端
薛丽莉
韩文博
王盼
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HEBEI FAREAST COMMUNICATION SYSTEM ENGINEERING CO LTD
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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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Abstract

The invention discloses a linear phase comparison method for direct digital phase processing, which does not need to use a frequency conversion auxiliary circuit, but avoids the nonlinear distortion of the common sinusoidal signal waveform to the phase processing. The periodicity of phase change of the frequency signal and the waveform characteristics of the frequency signal are utilized, and the clock signal is selected to be n times of the corresponding frequency of the comparison signal according to the proportion that the linear section of the sinusoidal signal accounts for the full phase change range of the phase full period. This ensures that there is always a linear segment of the operating signal of the n clock signals that are consecutive together. The phase resolution of the method can be better than ps magnitude and even higher, the response time of phase comparison and measurement frequency can be started from the carrier frequency period of the signal, the signal can cover more than days for a long time, and the frequency stability measurement and control of ns magnitude sampling time can be realized. The method is suitable for digital phase measurement and comparison between signals with any frequency nominal value, and a plurality of performances are superior to the international commonly accepted double mixing time difference DMTD.

Description

Linear phase comparison method for direct digital phase processing
Technical Field
The invention belongs to the field of radio measurement and precise time frequency measurement and control, and particularly relates to a linear phase comparison method for direct digital phase processing.
Background
The linear phase comparison method of direct digital phase processing is a high-precision measuring method for frequency standard comparison and phase change detection. At present, in the prior art, when the phase comparison problem is solved, a gate circuit or an integrated circuit trigger is adopted to directly phase-discriminate two comparison signals, such as an American HpK 34-59991A phase comparator, and the scheme has the defects of poor linearity, inconvenient adjustment, and dead zone and nonlinear phenomena in phase comparison under high frequency. The us 3.986,113 patent uses a double mixer amplitude-phase detection scheme, which, although improving linearity and "dead zone", still has the disadvantages that the phase comparator has measurement accuracy related to the frequency nominal value and low frequency phase ratio accuracy is low, and the auxiliary common oscillator frequency must be changed differently at different phase ratio values. The analog linear phase comparison instrument has defects in drift and phase resolution, especially for the situation that the phase difference change between complex frequency signals is difficult to recover the actual phase change of the measured signal.
The best double mixer time difference measurement method (DMTD), whether analog or digital, is currently internationally recognized as indeed having a high measurement resolution. However, the method adopts a beat method, so that the apparent comparison frequency of the time difference measurement is greatly reduced while the error is multiplied, and the short-term and transient capability of measuring the frequency stability of the shorter sampling time is reduced. For example, the DMTD method introduces the multiplication effect of the measurement by the double mixing method, and reduces the measurement frequency, such as the frequency of 10MHz compared originally is often reduced to several hundred Hz by mixing. Thus, only the frequency stability longer than ms can be measured in the comparison of the terminals. Also, the DMTD method has a time lag problem. The DMTD method includes the steps of mixing, filtering, amplifying, counting, etc., and the real-time performance of the processing is greatly affected. Moreover, although DMTD and other methods have high resolution, the devices are complicated and expensive, and their application in control is limited.
In summary, the defects or shortcomings of the current stage methods mainly include:
1. the measurement response time is slow, and the short-term comparison time can only reach ms level;
2. phase noise and long-term drift are large, and long-term stability is insufficient;
3. the equipment is complex, the cost is high, and the application is limited;
disclosure of Invention
The invention aims to solve the technical problem of providing a linear phase comparison technology for direct digital phase processing, which utilizes an ADC acquisition signal linear region as a phase detection interval to realize high-resolution phase comparison and processing.
In order to achieve the purpose, the invention adopts the following technical scheme to solve the problem:
a linear phase comparison method for single A/D sampling digital phase processing selects a clock signal n times of the corresponding frequency of a measured signal, thus ensuring that one linear section of the working signal always exists in n continuous clock signals together, and specifically comprises the following steps:
taking a path of comparison signal as a detected signal and keeping the original frequency and waveform;
secondly, the frequency of the other path of reference signal is expanded to be n times of the nominal value of the frequency of the measured signal through a frequency multiplier, n multiplied reference signals in each measured signal period are used as clock signals sampled by an A/D converter, and n is a positive number;
the FPGA controls the A/D converter to sample the detected signal and sends the acquired voltage data of the linear area to the MCU;
the MCU converts the received voltage data into a phase difference value of the two signals, and calculates the frequency and the frequency stability of the detected signal through the phase difference change.
When the frequency of the clock signal is n times of the frequency of the measured signal, one of n continuous clock signals always appears in a linear region of the measured signal and periodically changes in the linear region, when one clock signal moves out of the linear region due to the phase change between the two signals, the other clock signal adjacent to the clock signal automatically enters the linear region, the interval of the adjacent 2 clock signals is equal to the period of the clock signal, namely, the periodic replacement of the clock signal is a full period of phase comparison; wherein the larger n is, the narrower the linear region is, and the better the linearity is.
A linear phase comparison method for double A/D sampling digital phase processing, two A/D converters share a high-frequency clock signal, the frequency value of the clock signal is equal to the common multiple value of the frequency of a measured signal and a reference signal, and the method specifically comprises the following steps:
firstly, inputting a path of tested signal into an A/D converter;
selecting a reference signal with the same frequency nominal value as the measured signal and inputting the reference signal into another A/D converter;
selecting common multiple frequencies of the measured signal and the reference signal as sampling clock signals of the two A/D converters respectively;
the FPGA controls the two A/D converters to respectively sample the respective input signals, and transmits the voltage data acquired in the linear area as an effective sampling value to the MCU;
the MCU converts the received voltage data into phase difference values between the measured signal and the reference signal respectively, and calculates the frequency stability of the measured signal according to the change of the phase difference values.
Wherein, the phase difference value in the fifth step is calculated by the following steps: the difference between two effective sampling values collected under the same clock is the phase difference value of the measured signal and the reference signal, and when the clocks of the collected effective sampling values are different, the corresponding times of the corresponding clock period are increased on the basis of the phase difference value.
The invention has the following advantages:
1. the method has simple hardware structure, low cost and high resolution. The phase resolution can be better than ps magnitude and even higher, the phase data of a linear region can be directly acquired, the linear distortion of the common sinusoidal signal waveform to phase processing is avoided, a frequency conversion circuit is not needed, the processing is direct, and the drift and line noise can be greatly reduced.
2. In a practical phase ratio, if the clock signal is multiplied to 100MHz or higher, the full period of the phase ratio thus obtained is 10 ns. And the fullness value of the A/D conversion corresponds to this 10ns, so that in the case of 16-bit A/D conversion, it is possible to obtain a value close to 1 × 10-13The resolution of (2).
3. The response time of the phase comparison and the measurement frequency can be started from the carrier frequency period of the signal, and the signal can cover more than days for a long time, so that the frequency stability measurement and control of ns-magnitude sampling time can be realized.
4. The invention can be used not only in linear phase measurement, but also in acquisition of phase information in phase noise measurement and in frequency and phase control.
Drawings
FIG. 1 is a diagram showing an apparatus of the present invention using a single A/D;
FIG. 2 is a waveform diagram of the present invention using a single A/D sample;
FIG. 3 is a diagram showing the construction of an apparatus of the present invention using dual A/Ds;
FIG. 4 is a waveform diagram of the present invention using dual A/D sampling;
FIG. 5 is a digital phase sampling between complex frequency signals of the present invention;
FIG. 6 shows the correspondence between the alignment curve and the clock for the linear phase alignment of the present invention;
FIG. 7 is the results of a self-calibration experiment of the present invention;
fig. 8 is an application direction of the method of the present invention.
Detailed Description
The invention is further illustrated by the following figures and examples.
The invention provides two schemes, one is to adopt single A/D digital sampling, and the other is to adopt double A/D digital sampling. When a single A/D circuit is used, one path of signal as a tested signal keeps the original frequency and waveform, the other path of signal passes through a frequency multiplier and then is used as a clock, the denser sampling rate with the frequency being n times is kept, and fixed time intervals or phase difference change is also ensured among sampling values of a sampling clock signal. For a sinusoidal signal, the signal is made to have a standard and stable waveform and amplitude by proper conditioning of the signal, and is sampled at intervals.
Referring to fig. 1, fig. 1 is a diagram of a single a/D device, two comparison signals of a measured signal and a reference signal may be in a simple frequency relationship or a complex frequency relationship, and the specific implementation steps are as follows:
firstly, a detected signal 1a is used as a detected signal and keeps the original frequency and waveform;
secondly, the frequency of the reference signal 3a is expanded to be n times of the nominal value of the frequency of the measured signal through a frequency multiplier 4a, and n multiplied reference signals in each measured signal period are used as clock signals sampled by an A/D converter 2 a;
the FPGA 5a controls the A/D converter 2a to sample the measured signal, and transmits the acquired voltage data of the linear area to the MCU 6a of the singlechip;
the MCU 6a converts the received voltage data into a phase difference value of two signals;
Figure BDA0002010489240000061
Figure BDA0002010489240000062
Figure BDA0002010489240000063
ΔTn＝φn+1-φn
Δ f and τ are the mean frequency deviation and the mean time of the measurement, Δ T is the amount of change in the phase difference over the mean time τ, V0ε (t) is the deviation in the amplitude direction, f, for the amplitude of the reference signal0In order to be at the nominal frequency,
Figure BDA0002010489240000064
t represents the time and phi represents the angle as the deviation value of the phase. Then calculating the frequency stability on the basis of the following steps:
Figure BDA0002010489240000065
wherein m is the number of samples.
Fig. 2 is a sampling waveform diagram when a single a/D, n is used, i.e., 10 (clock signal 100Mhz, signal under test 10Mhz), and it can be seen from the diagram: one of 10 clock signals which are continuous together always appears in a linear region of a measured signal, and the linear region is periodically changed. Once the clock signal moves out of the linear region due to the phase change between two signals, another clock signal adjacent to the clock signal automatically enters the linear region, and since the interval of the 2 clock signals is exactly equal to 10ns, that is, the period of the 100MHz alignment signal, that is, the periodic replacement of the clock signal is exactly the completion of the full period of the phase alignment one by one.
In order to more conveniently ensure the relation between the comparison signal and the clock without processing such as frequency multiplication, 2A/D converters are adopted.
FIG. 3 is a diagram of a dual A/D device, in which the nominal frequency values of two comparison signals of the measured signal 1b and the reference signal 2b are the same. The specific implementation steps are as follows:
firstly, inputting a detected signal 1b into an A/D converter 4 b;
selecting a reference signal 2b with the same frequency nominal value as the measured signal and inputting the reference signal into another A/D converter 5 b;
selecting common multiple frequencies of the measured signal and the reference signal as sampling clock signals 3b of the two A/D converters respectively;
the FPGA 6b controls the two A/D converters to respectively sample the respective input signals, and transmits the voltage data acquired in the linear area as an effective sampling value to the singlechip MCU 7 b;
the MCU 7b converts the received voltage data into phase difference values of the detected signal and the reference signal respectively:
Figure BDA0002010489240000071
Figure BDA0002010489240000072
Figure BDA0002010489240000073
here,. DELTA.Tfxn、ΔTfon and Δ Tn represent the phase difference value of the clock signal to the measured signal, the phase difference value of the clock signal to the reference signal, and the phase difference between the measured signal and the reference signal, respectively.
And calculating the frequency stability:
Figure BDA0002010489240000081
the nominal value of the frequency of the reference signal is the same as that of the measured signal, a frequency doubling circuit is not needed, and the stability of the measured frequency is better. They share a high frequency clock signal with a frequency value equal to 2 times the frequency of the comparison signal. The clock signal samples 2 comparison signals at the same time, and data collected in a linear area near 0 degree is a valid sampling value. Because the phase difference between the comparison signals varies, the 2 valid sampling values are not necessarily obtained under the same clock. The difference between the 2 valid sample values collected at the same clock is the phase difference between the 2 comparison signals. And when the clocks of the collected effective sampling values are different, the corresponding times of the corresponding clock period are increased on the basis of the difference.
Non-linear corrections are a must be considered in this typical linear phase comparison method, especially when the effective acquisition area is a large proportion of the full period of the signal under test. When a clock signal finishes effective acquisition, the next clock signal acquires the linear region again, and the process is carried out in sequence until the measurement of a full period is finished. The exact same sampling value does not appear in a least common multiple period, so that an obvious linear phase comparison curve can be obtained by arranging all effective acquisition points in a full period according to the size, as shown in fig. 4, when the range of the selected linear section is large, a deviated curve may be obtained at the edge, and at this time, data needs to be corrected.
The clock is phase comparison under the condition of multiple frequency of the measured signal and phase comparison under the condition of complex frequency relation, and when the digitalized clock is switched, although the clock is not sampled by a clock group of an original clock sequence in a clock group to obtain phase difference data, the clock group of another clock sequence adjacent to or adjacent to the voltage value of the measured signal is sampled to obtain the phase difference data. The switching of the clock groups of the fixed clock sequence has a change of one clock period in time relation to the sampling of the clock group of another adjacent clock sequence when the clock is a multiple of the frequency of the signal to be detected, and the collected phase data has an increase or decrease of one clock period. Since such phase alignment uses a clock cycle as a full period of the phase alignment (0 degree to 360 degrees, or vice versa), the start of the next phase period is exactly the end of the previous phase period, and the phase alignment is equivalent to the periodic phase alignment of 0 degree and 360 degrees, thereby ensuring the continuity of the phase.
Whereas for a/D, the a/D dynamic range and a/D accuracy generally refer to the same thing. Dynamic range is defined as the ratio of the minimum and maximum signal measurable by the system. The a/D resolution is determined by the number of bits used in digitizing the input signal. For a 16-bit device, the total voltage range is represented as 21665536 independent digital values or output codes. Thus, the absolute minimum level that the system can measure is represented as 1 bit, or 1/65536 of the A/D voltage range. For 16-bit a/D resolution, the actual accuracy may be much less than the resolution due to the presence of internal or external error sources. 16 bit A/D includes 21665536 steps or conversions and least significant bit, LSB, VREF/65536, 3.3V/65536, 50.35 μ V. For an ideal a/D, all codes have the same width of 1 LSB. If the maximum signal value of the A/D is 2.5V, it means that there are 49652 total transitions 2.5V/1 LSB. For this case, there would be 65536 and 49652 15884 conversions unused. This reflects a loss of signal accuracy or a loss of 0.4 bits of ENOB after conversion. E if the difference between the A/D reference VREF and the A/D maximum signal level increasesThe loss of NOB or loss of accuracy will be exacerbated. For example, if the a/D maximum signal level is 1.2V and VREF is 3.3V, the ENOB penalty will be 1.5 bits. The a/D dynamic range must therefore be matched to the maximum signal amplitude to achieve the highest accuracy.
FIG. 5 is a digital phase sampling between complex frequency signals at TminAlthough the phase change between the intermediate signals is discontinuous, the change and the stepping quantity of the phase difference obtained by digital acquisition are fixed delta T if the intermediate signals are rearranged according to monotonicity. This case is summed with TminThe comparison between signals of close frequency values, which are beat values, is similar. Therefore, the actual phase difference value can be determined for all the samples of the arrangement condition of the voltage acquisition data in the least common multiple period and the variation thereof. We take values from the linear region of the measured signal 0 to 360 degrees, only very limited voltage-phase difference data of the linear region occupying less than 10% of the full period around 0 degrees, such as the position near the 0 point of the fourth period and the position near the end of the seventh period. The sampling points are all working in the linear section of the tested signal, namely the effective value points to be selected.
The start and end positions of a fixed full cycle are set in a specific linear segment processor in clock cycles. The voltage-phase difference value of the clock acquisition falling in this particular linear segment region is the effective phase difference value at intervals of the period of the signal under test. Once the clock goes out of this particular linear segment region, the next clock signal before or after it falls exactly in this region. The alternate locations of clock generation into and out of this particular linear segment region are different, such that one clock is out of the region from 0 degrees and the other clock is in from 360 degrees, and vice versa, relative to a phase ratio of 0 to 360 degrees. The acquisition of such data is suitable for the measurement of long-term and short-term indicators. Fig. 6 is an illustration of this operation, and it should be noted that the comparison clocks at which the effective phases are measured are continuous when the two comparison signals are in a simple frequency relationship; when it is a complex frequency relationship, the clock is discontinuous.
FIG. 7 is a 10MHz8607 self-calibrated frequency stability-curveA wire. As can be seen from the figure, the noise floor of the system is 3.93 x 10-13And/s, the measurement requirements of most atomic frequency standards and crystal oscillators can be met.
The method can be further applied to the aspects of phase change, frequency stability, phase noise measurement of the measured signal, a digital phase-locked loop, a modular frequency-phase control device, a modular frequency-phase control system and the like. Fig. 8 is an illustration of the direction of application thereof. The digitized phase ratio is not only used for frequency stability measurement, but more for phase noise measurement and frequency and phase control. Compared with the current highest-precision measurement technology, the method can not completely and continuously measure and control the phase, the frequency and the like of any frequency, but can measure the phase and the frequency of signals of various most common frequency points with high precision, and the measurement is simpler and more convenient.

Claims (4)

1. A linear phase comparison method for single A/D sampling digital phase processing is characterized in that a clock signal is selected to be n times of the corresponding frequency of a detected signal, so that a linear section working in a detected sinusoidal signal is always ensured in n continuous clock signals, and the method specifically comprises the following steps:
firstly, the comparison signal is used as a detected signal to keep the original frequency and waveform;
secondly, the reference signal passes through a frequency multiplier, the frequency is expanded to be n times of the nominal value of the frequency of the measured signal, the n multiplied reference signals are used as clock signals sampled by an A/D converter, and n is a positive number;
the FPGA controls the A/D converter to sample the detected signal and sends the acquired voltage data of the linear area to the MCU;
and fourthly, the MCU converts the received voltage data into a phase difference value between the measured signal and the reference signal, and calculates the frequency and the frequency stability of the measured signal through the phase difference change.
2. A linear phase comparison method of single a/D sampling digital phase processing according to claim 1, wherein when the frequency of the clock signal is n times the frequency of the measured signal, one of n consecutive clock signals always appears in the linear region of the measured signal and periodically changes in the linear region, when one clock signal moves out of the linear region due to the phase change between two signals, the other clock signal adjacent to the clock signal automatically enters the linear region, and the interval between two adjacent clock signals is equal to the period of the clock signal, i.e. the periodic replacement of the clock signal is a full period of the phase comparison; wherein the larger n is, the narrower the linear region is, and the better the linearity is.
3. A linear phase comparison method for double A/D sampling digital phase processing is characterized in that two A/D converters share a high-frequency clock signal, the frequency value of the clock signal is equal to the common multiple value of the frequency of a measured signal and the frequency of a reference signal, and the method specifically comprises the following steps:
firstly, inputting a detected signal into an A/D converter;
selecting a reference signal with the same frequency nominal value as the measured signal and inputting the reference signal into another A/D converter;
selecting common multiple frequencies of the measured signal and the reference signal as sampling clock signals of the two A/D converters respectively;
the FPGA controls the two A/D converters to respectively sample the respective input signals, and transmits the voltage data acquired in the linear area as an effective sampling value to the MCU;
the MCU converts the received voltage data into a phase difference between the measured signal and the reference signal, and calculates the frequency and the frequency stability of the measured signal through the phase difference change.
4. A linear phase comparison method for dual a/D sampling digital phase processing according to claim 3, wherein the phase difference value in step (v) is calculated by: the difference between two effective sampling values collected under the same clock is the phase difference value of the measured signal and the reference signal, and when the clocks of the collected effective sampling values are different, the corresponding times of the corresponding clock period are increased on the basis of the phase difference value.
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