CN109980004B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN109980004B
CN109980004B CN201711446096.4A CN201711446096A CN109980004B CN 109980004 B CN109980004 B CN 109980004B CN 201711446096 A CN201711446096 A CN 201711446096A CN 109980004 B CN109980004 B CN 109980004B
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layer
forming
opening
dielectric layer
work function
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CN109980004A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a dielectric layer is arranged on the substrate, and a first opening penetrating through the thickness of the dielectric layer is formed in the dielectric layer; forming second openings in the substrate and the dielectric layer on two sides of the first opening, wherein the second openings penetrate through the thickness of the dielectric layer and the substrate with partial thickness; forming a stress layer in the second opening in the substrate; after the stress layer is formed, forming an N-type work function layer on the bottom and the side wall of the first opening; forming a first metal layer which is filled in the first opening on the N-type work function layer; and forming a second metal layer which is filled in the second opening on the stress layer. According to the invention, the N-type work function layer is formed after the stress layer is formed, so that the work function value of the N-type work function layer is ensured to meet the requirement, the threshold voltage mismatch of the semiconductor structure can be avoided, and the performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs has correspondingly continued to decrease. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, and short-channel effects (SCE) are more likely to occur.
The fin field effect transistor (FinFET) has outstanding performance in the aspect of inhibiting short channel effect, and the grid electrode of the FinFET can control the fin part at least from two sides, so that compared with a planar MOSFET, the grid electrode of the FinFET has stronger channel control capability, and the short channel effect can be well inhibited.
However, the performance of the prior art semiconductor structures is still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are beneficial to ensuring that the work function value of an N-type work function layer meets the requirement, avoiding the threshold voltage mismatch of the semiconductor structure and improving the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a dielectric layer is arranged on the substrate, and a first opening penetrating through the thickness of the dielectric layer is formed in the dielectric layer; forming second openings in the substrate and the dielectric layer on two sides of the first opening, wherein the second openings penetrate through the thickness of the dielectric layer and the substrate with partial thickness; forming a stress layer in the second opening in the substrate; after the stress layer is formed, forming an N-type work function layer on the bottom and the side wall of the first opening; forming a first metal layer which is filled in the first opening on the N-type work function layer; and forming a second metal layer which is filled in the second opening on the stress layer.
Optionally, the process temperature for forming the stress layer is 300 ℃ to 900 ℃.
Optionally, the stress layer is formed by using a selective epitaxial growth process.
Optionally, the process parameters of the selective epitaxial growth process include: the temperature is 600 ℃ to 850 ℃, the gas pressure is 8Torr to 300Torr, the process gas comprises H2, HCl, SiH2Cl2, GeH4 and B2H6, wherein the gas flow of H2 is 10sccm to 3000sccm, the gas flow of HCl is 10sccm to 200sccm, the gas flow of SiH2Cl2 is 20sccm to 2000sccm, the gas flow of GeH4 is 10sccm to 500sccm, and the gas flow of B2H6 is 5sccm to 100 sccm.
Optionally, the N-type work function layer contains aluminum ions.
Optionally, the material of the N-type work function layer is TiAl, TaAl, TiAlC, AlN, TiAlN, or TaAlN.
Optionally, in the same process step, the first metal layer and the second metal layer are formed.
Optionally, the process steps for forming the first metal layer and the second metal layer include: forming a metal film filled in the first opening and the second opening on the N-type work function layer and the stress layer, wherein the metal film covers the top of the dielectric layer; and removing the metal film higher than the top of the dielectric layer, wherein the metal film remained in the first opening is used as the first metal layer, and the metal film remained in the second opening is used as the second metal layer.
Optionally, before forming the N-type work function layer, the method further includes: and forming a metal silicide layer on the surface of the stress layer.
Optionally, after providing the substrate, before forming the second opening, the method further includes: and forming a gate dielectric layer on the surface of the substrate exposed by the first opening.
Optionally, the forming method of the gate dielectric layer includes a thermal oxidation treatment process.
Optionally, the process temperature of the thermal oxidation treatment process is 750-1000 ℃.
Optionally, before forming the second opening and after forming the gate dielectric layer, the method further includes: forming an anti-reflection coating which is filled in the first opening on the gate dielectric layer; before forming the stress layer and after forming the second opening, the method further includes: and removing the anti-reflection coating.
Optionally, after forming the gate dielectric layer and before forming the anti-reflection coating, the method further includes: forming a protective layer on the gate dielectric layer and the side wall of the first opening; before forming the N-type work function layer, and after forming the stress layer, the method further includes: and removing the protective layer.
Optionally, after the forming of the gate dielectric layer and before the forming of the protective layer, the method further includes: and forming a P-type work function layer on the surface of the gate dielectric layer and the side wall of the first opening.
Optionally, after the forming of the gate dielectric layer and before the forming of the second opening, the method further includes: and adopting an annealing process to carry out densification treatment on the gate dielectric layer.
Optionally, the process temperature of the densification treatment is 800-1050 ℃.
Accordingly, the present invention also provides a semiconductor structure comprising: the dielectric layer is arranged on the substrate, and a first opening penetrating through the thickness of the dielectric layer is formed in the dielectric layer; stress layers positioned in the substrate on two sides of the first opening; and the second opening is positioned in the dielectric layer and penetrates through the thickness of the dielectric layer, and the surface of the stress layer is exposed by the second opening.
Optionally, the semiconductor structure further includes: and the gate dielectric layer is positioned on the surface of the substrate exposed by the first opening.
Optionally, the semiconductor structure further includes: the P-type work function layer is positioned on the surface of the gate dielectric layer and the side wall of the first opening; and the protective layer is positioned on the surface of the P-type work function layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme of the forming method of the semiconductor structure, the dielectric layer is internally provided with a first opening penetrating through the thickness of the dielectric layer; forming second openings in the substrate and the dielectric layer on two sides of the first opening, wherein the second openings penetrate through the thickness of the dielectric layer and the substrate with partial thickness; and forming a stress layer in the second opening in the substrate. And when the stress layer is formed, an N-type work function layer does not exist in the first opening, and after the stress layer is formed, N-type work function layers are formed on the bottom and the side wall of the first opening. According to the invention, the N-type work function layer is formed after the stress layer is formed, so that the N-type work function layer can be prevented from undergoing the forming process of the stress layer, ion diffusion in the material of the N-type work function layer is prevented, the work function value of the N-type work function layer is ensured to meet the requirement, the threshold voltage mismatch of a semiconductor structure can be avoided, and the performance of the semiconductor structure is improved.
In the alternative, the first metal layer and the second metal layer are formed in the same process step, so that the process steps are simplified, and the manufacturing cost is reduced.
In an alternative scheme, the process temperature for forming the stress layer is 300-900 ℃, so that defects in the stress layer can be avoided, and the quality of the formed stress layer can be improved; and the stress release of the stress layer is avoided, so that the stress of the stress layer to the channel is ensured to be proper.
In an alternative, after providing the substrate, before forming the second opening, the forming method further includes: and forming a gate dielectric layer on the surface of the substrate exposed by the first opening, and forming the gate dielectric layer before the stress layer is formed, which is beneficial to avoiding stress release of the stress layer caused by the process environment for forming the gate dielectric layer.
In an alternative scheme, the process temperature of the thermal oxidation treatment process is 750-1000 ℃, and the process temperature of the thermal oxidation treatment process is suitable for improving the uniformity and the density of the gate dielectric layer, so that the forming quality of the gate dielectric layer can be improved.
In an alternative scheme, the process temperature of the densification treatment is 800-1050 ℃, and the process temperature of the densification treatment is proper, so that the defects in the gate dielectric layer material can be reduced, and the carrier mobility of a subsequently formed semiconductor structure can be improved.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 18 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known in the art, the performance of the conventional semiconductor structure is still to be improved.
Now, an analysis is performed in combination with a method for forming a semiconductor structure, and fig. 1 to 6 are schematic structural diagrams corresponding to respective steps in the method for forming a semiconductor structure, where the steps of the process for forming a semiconductor structure mainly include:
referring to fig. 1, a substrate 10 is provided, the substrate 10 has a dielectric layer 11 thereon, and the dielectric layer 11 has a first opening 21 penetrating the thickness of the dielectric layer 11.
Referring to fig. 2, a gate dielectric layer 12 is formed at the bottom of the first opening 21 (refer to fig. 1).
Referring to fig. 3, an N-type work function layer 16 is formed on the sidewalls of the first opening 21 (see fig. 1) and on top of the gate dielectric layer 12.
Referring to fig. 4, a metal gate 41 is formed on the surface of the N-type work function layer 16 to fill the first opening 21 (refer to fig. 1).
Referring to fig. 5, after the metal gate 41 is formed, second openings 22 are formed in the substrate 10 and the dielectric layer 11 on two sides of the first opening 21 (refer to fig. 1), and the second openings 22 penetrate through the thickness of the dielectric layer 11 and a part of the thickness of the substrate 10.
Referring to fig. 6, a stress layer 31 is formed within the second opening 22 (refer to fig. 5) in the substrate 10.
The semiconductor structure formed by the above method has poor performance, and the reason for this is analyzed to be that:
the N-type work function layer 16 contains easily diffusible ions, such as aluminum ions, in the material. Under the influence of the process environment for forming the stress layer 31, for example, the process temperature for forming the stress layer 31, the easily-diffusing ions in the material of the N-type work function layer 16 are easily diffused, so that the work function value of the N-type work function layer 16 is changed, and the threshold voltage of the semiconductor structure is mismatched, thereby reducing the performance of the semiconductor structure.
To this end, the present invention provides a method for forming a semiconductor structure, comprising: forming second openings in the substrate and the dielectric layer on two sides of the first opening, wherein the second openings penetrate through the thickness of the dielectric layer and the substrate with partial thickness; forming a stress layer in the second opening in the substrate; and after the stress layer is formed, forming an N-type work function layer on the bottom and the side wall of the first opening.
According to the invention, the forming step of the N-type work function layer is arranged after the forming step of the stress layer, so that the N-type work function layer can be prevented from undergoing the forming process of the stress layer, ion diffusion in the material of the N-type work function layer can be prevented, the work function value of the N-type work function layer can be ensured to meet the requirement, the threshold voltage mismatch of the semiconductor structure can be avoided, and the performance of the semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to fig. 18 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 7, a substrate 100 is provided, the substrate 100 has a dielectric layer 110 thereon, and the dielectric layer 110 has a first opening 210 penetrating the thickness of the dielectric layer 110.
In this embodiment, the substrate 100 includes: the semiconductor structure comprises a substrate 101, a fin portion 102 protruding out of the substrate 101, and an isolation layer 103 located on the substrate 101, wherein the isolation layer 103 covers part of the sidewall surface of the fin portion 102.
The substrate 101 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 101 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; in this embodiment, the substrate 101 is a silicon substrate.
In this embodiment, the fin 102 is made of the same material as the substrate 101, and is also made of silicon. In other embodiments, the material of the fin 102 may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The isolation layer 103 is made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the isolation layer 103 is made of silicon oxynitride.
The dielectric layer 110 is made of an insulating material. In this embodiment, the dielectric layer 110 is made of silicon oxide. In other embodiments, the material of the dielectric layer may also be silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
The process steps for forming the dielectric layer 110 and the first opening 210 include: forming a dummy gate (not shown) crossing the fin 102 on the isolation layer 103, wherein the dummy gate covers part of the top and part of the sidewall of the fin 102; forming a dielectric film (not shown) on the isolation layer 103, wherein the top of the dielectric film is higher than the top of the dummy gate; removing part of the dielectric film to expose the top of the dummy gate, and taking the residual dielectric film as the dielectric layer 110; the dummy gate is removed to form the first opening 210.
In this embodiment, after forming the dummy gate and before forming the dielectric film, the method further includes: and forming a side wall 104 on the side wall of the pseudo gate. And after the dummy gate is removed, the side wall 104 is reserved.
In the process of removing the dummy gate, the sidewall spacers 104 may protect the sidewalls of the dielectric layer 110, and prevent the sidewalls of the dielectric layer 110 from being etched.
In this embodiment, the material of the sidewall 104 is silicon carbonitride, and in other embodiments, the material of the sidewall 104 may also be silicon nitride, silicon carbide, silicon oxycarbonitride, or silicon oxynitride.
Referring to fig. 8, a gate dielectric layer 120 is formed on the surface of the substrate 100 exposed by the first opening 210 (see fig. 7).
The gate dielectric layer 120 includes an interfacial layer 121 and a high-k gate dielectric layer 122 on top of the interfacial layer 121.
The interface layer 121 can provide a good interface foundation for forming the high-k gate dielectric layer 122, which is beneficial to improving the forming quality of the high-k gate dielectric layer 122 and reducing the interface state density between the high-k gate dielectric layer 122 and the top of the fin portion 102.
In this embodiment, the interface layer 121 is made of silicon oxide. In other embodiments, the material of the interface layer may also be germanium oxide, and the material of the interface layer may also be oxygen-doped silicon germanium, oxygen-doped gallium arsenide, or oxygen-doped indium gallium.
The forming method of the gate dielectric layer 120 includes a thermal oxidation process. Specifically, in this embodiment, the interfacial layer 121 is formed by a thermal oxidation process.
If the process temperature of the thermal oxidation process is too low, the uniformity and density of the formed interface layer 121 are poor, and the improvement effect of the interface layer 121 on the interface foundation between the high-k gate dielectric layer 122 and the top of the fin 102 is affected. In this embodiment, the process temperature of the thermal oxidation process is 750 to 1000 ℃.
In this embodiment, the high-k gate dielectric layer 122 covers the top of the interface layer 121, and also covers the top of the dielectric layer 110 and the sidewall of the first opening 210 (refer to fig. 7), the high-k gate dielectric layer 122 on the top of the dielectric layer 110 is subsequently removed, and the high-k gate dielectric layer 122 on the sidewall of the first opening 210 and the top of the interface layer 121 is remained.
In this embodiment, the forming process of the high-k gate dielectric layer 122 is an atomic layer deposition process. The ald process provides good step coverage at the corner between the bottom of the first opening 210 and the sidewall, and the formed high-k gate dielectric layer 122 has a uniform thickness.
The high-k gate dielectric layer 122 is made of a high-k dielectric material (the dielectric constant is greater than 3.9). In this embodiment, the material of the high-k gate dielectric layer 122 is HfO2(ii) a In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2。
Subsequently, second openings are formed in the substrate 100 and the dielectric layer 110 on two sides of the first opening 210, and a stress layer is formed in the second openings in the substrate 100. The gate dielectric layer 120 is formed before the formation of the stress layer, which is helpful for preventing the stress release of the stress layer caused by the process environment for forming the gate dielectric layer 120, so that the stress layer is difficult to generate a proper stress magnitude for the channel. If the gate dielectric layer 120 is formed after the formation of the stress layer, the stress layer will undergo the thermal oxidation process, and the stress layer is easily subjected to stress release under the influence of the process temperature of the thermal oxidation process.
Referring to fig. 9, a P-type work function layer 130 is formed on the surface of the gate dielectric layer 120 and the sidewall of the first opening 210 (refer to fig. 7).
In this embodiment, the P-type work function layer 130 covers the surface of the high-k gate dielectric layer 122. Subsequently, in the same process step, the high-k gate dielectric layer 122 and the P-type work function layer 130 on top of the dielectric layer 110 are removed.
In this embodiment, the P-type work function layer 130 is made of TiN. In other embodiments, the material of the P-type work function layer may also be TaN, TiSiN, or TaSiN.
In other embodiments, the step of forming the P-type work function layer may also be arranged to be performed after the stress layer is subsequently formed.
In this embodiment, after forming the P-type work function layer 130, the method further includes: and performing densification treatment on the gate dielectric layer 120 by adopting an annealing process.
The densification process can reduce defects in the interfacial layer 121 and the high-k gate dielectric layer 122, which is helpful for improving carrier mobility of a subsequently formed semiconductor structure.
If the process temperature of the densification treatment is too low, it is difficult to effectively reduce the defects in the materials of the interfacial layer 121 and the high-k gate dielectric layer 122, resulting in low carrier mobility of the subsequently formed semiconductor structure. In this embodiment, the process temperature of the densification treatment is 800 to 1050 ℃.
And forming a stress layer in the substrate 100 on both sides of the first opening 210, and arranging the process step of forming the stress layer after the process step of densification treatment, so that the stress layer can be prevented from undergoing the densification treatment process, and the stress layer is prevented from being influenced by the process temperature of densification treatment, and stress release occurs in the process of densification treatment.
Referring to fig. 10, a protection layer 140 is formed on the gate dielectric layer 120 and on the sidewalls of the first opening 210 (see fig. 7).
In this embodiment, the protective layer 140 covers the surface of the P-type work function layer 130, and the high-k gate dielectric layer 122, the P-type work function layer 130, and the protective layer 140 on the top of the dielectric layer 110 are removed in the same process step.
In this embodiment, in the subsequent process of removing the anti-reflective coating, the protection layer 140 can protect the surface of the P-type work function layer 130, so as to prevent the surface of the P-type work function layer 130 from being etched.
In other embodiments, the protective layer covers the surface of the gate dielectric layer, and in the subsequent process of removing the anti-reflection coating, the protective layer can protect the surface of the gate dielectric layer and prevent the gate dielectric layer from being etched.
In this embodiment, the material of the protection layer 140 is silicon oxide. In other embodiments, the material of the protective layer may also be silicon nitride or silicon carbide.
It should be noted that, in other embodiments, after the gate dielectric layer is formed, a subsequent process step of forming an anti-reflective coating may be directly performed.
Referring to fig. 11, an anti-reflective coating 150 is formed on the gate dielectric layer 120 to fill the first opening 210 (refer to fig. 7).
The anti-reflective coating 150 can prevent the sidewall and bottom surfaces of the first opening 210 from being contaminated or damaged by the subsequent process steps for forming the second opening 220.
In this embodiment, the top of the anti-reflective coating 150 is flush with the top of the dielectric layer 110.
In this embodiment, the process steps of forming the anti-reflective coating 150 include: forming an anti-reflective coating film (not shown) covering the protection layer 140, the top of the anti-reflective coating film being higher than the top of the dielectric layer 110; and removing the anti-reflection coating film higher than the top of the dielectric layer 110 to form the anti-reflection coating 150.
In this embodiment, the step of removing the anti-reflective coating film above the top of the dielectric layer 110 further includes: the protective layer 140, the P-type work function layer 130, and the high-k gate dielectric layer 122 on top of the dielectric layer 110 are removed.
In this embodiment, the material of the anti-reflective coating 150 includes silicon-containing oxycarbide.
Referring to fig. 12, second openings 220 are formed in the substrate 100 and the dielectric layer 110 on both sides of the first opening 210 (see fig. 7), and the second openings 220 penetrate through the thickness of the dielectric layer 110 and a portion of the thickness of the substrate 100.
In this embodiment, the second opening 220 is located in the fin portion 102 and the dielectric layer 110 on both sides of the first opening 210, and penetrates through the dielectric layer 110 and the fin portion 102 with a partial thickness.
The second opening 220 provides a spatial location for the stress layer and the second metal layer to be formed subsequently.
In this embodiment, the process steps for forming the second opening 220 include: forming a photoresist layer (not shown) on top of a portion of the dielectric layer 110, the photoresist layer also covering the top of the anti-reflective coating 150; etching the dielectric layer 110 by taking the photoresist layer as a mask until the surface of the fin part 102 is exposed; the exposed fin portion 102 is removed to form the second opening 220.
In this embodiment, the dielectric layer 110 and the fin portion 102 are etched by a dry etching process, where the process parameters of the dry etching process include: the etching gas comprises CH4And CHF3In which CH4The gas flow rate of the gas is 8sccm to 500sccm, CHF3The gas flow is 30sccm to 200sccm, the chamber pressure is 10mTorr to 2000mTorr, the radio frequency power is 100W to 1300W, the direct current self-bias voltage is 80V to 500V, and the etching gas is introduced for 4s to 500 s.
Referring to fig. 13, the anti-reflective coating 150 (refer to fig. 12) is removed.
And forming a stress layer in the second opening 220, and removing the anti-reflective coating 150 to prevent the anti-reflective coating 150 from affecting the quality of the stress layer. If the anti-reflective coating 150 is remained, in the subsequent process of forming the stress layer, the anti-reflective coating 150 is easy to cause pollution to the stress layer, so that the formation quality of the stress layer is poor.
Referring to fig. 14, a stress layer 310 is formed within the second opening 220 (refer to fig. 12) in the substrate 100.
The stress layer 310 serves as a source-drain doped region of a subsequently formed semiconductor structure. In this embodiment, the stress layer 310 is made of silicon germanium.
In this embodiment, the stress layer 310 is formed by a selective epitaxial growth process. The stress layer 310 formed by the selective epitaxial growth process has a high lattice matching degree with the fin portion 102 material, which is beneficial to improving the formation quality of the stress layer 310.
If the process temperature for forming the stress layer 310 is too low, the content of the stress layer 310 is prone to have defects, which affects the quality of forming the stress layer 310; if the process temperature for forming the stress layer 310 is too high, stress release easily occurs in the stress layer 310, and it is difficult for the stress layer 310 to generate appropriate stress on the channel. In this embodiment, the process temperature for forming the stress layer 310 is 300 ℃ to 900 ℃.
The technological parameters of the selective epitaxial growth process comprise: the temperature is 600 ℃ to 850 ℃, the gas pressure is 8Torr to 300Torr, the process gas comprises H2, HCl, SiH2Cl2, GeH4 and B2H6, wherein the gas flow of H2 is 10sccm to 3000sccm, the gas flow of HCl is 10sccm to 200sccm, the gas flow of SiH2Cl2 is 20sccm to 2000sccm, the gas flow of GeH4 is 10sccm to 500sccm, and the gas flow of B2H6 is 5sccm to 100 sccm.
An N-type work function layer is formed on the bottom and the sidewall of the first opening 210, and the process step of forming the stress layer 310 is performed before the process step of forming the N-type work function layer, so that ion diffusion of the N-type work function layer material caused by the process environment of forming the stress layer 310 can be avoided.
The gate dielectric layer 120 is formed on the surface of the substrate 100 exposed by the first opening 210, and the stress layer 310 is formed after the gate dielectric layer 120 is formed, which is beneficial to avoiding stress release of the stress layer 310 caused by a process environment for forming the gate dielectric layer 120, thereby ensuring that the stress layer 310 has a proper stress effect on a channel. If the stress layer 310 is formed first and then the gate dielectric layer 120 is formed, since the forming method of the gate dielectric layer 120 includes a thermal oxidation process, and since the process temperature of the thermal oxidation process is high, the stress layer 310 is easy to release stress during the thermal oxidation process, and thus it is difficult to generate appropriate stress to the channel.
Referring to fig. 15, a silicide layer 320 is formed on the surface of the stress layer 310.
Subsequently, a second metal layer is formed to fill the second opening 220 (refer to fig. 12), and the silicide layer 320 can reduce the parasitic resistance on the surface of the stress layer 310, thereby facilitating the electrical conduction between the stress layer 310 and the second metal layer.
The process steps for forming the silicide layer 320 include: forming a conductive film (not shown) on the top of the dielectric layer 110, the sidewalls of the second opening 220 and the top of the stress layer 310; annealing the conductive film to convert the conductive film on the surface of the stress layer 310 into a silicide layer 320; and removing the conductive film on the top of the dielectric layer 110 and on the sidewall of the second opening 220.
In this embodiment, the material of the conductive film is Ti. In other embodiments, the material of the conductive film may also be Ni or Co.
If the temperature of the annealing process performed on the conductive film is too low, the silicidation reaction of the conductive film cannot be triggered, and the silicide layer 320 cannot be formed. In this embodiment, the temperature of the annealing treatment is 850 to 1000 ℃.
An N-type work function layer is formed on the bottom and the sidewall of the first opening 210, and the silicide layer 320 is formed before the N-type work function layer is formed, which is helpful for preventing ion diffusion of an N-type work function layer material during the formation of the silicide layer 320, thereby ensuring the work function of the N-type work function layer. If the N-type work function layer is formed first and then the silicide layer 320 is formed, the N-type work function layer will undergo an annealing process for forming the silicide layer 320, and the annealing process has a high temperature, which may easily cause diffusion of easily-diffusing ions in the N-type work function layer.
Referring to fig. 16, an N-type work function layer 160 is formed on the bottom and sidewalls of the first opening 210 (refer to fig. 12).
In this embodiment, before forming the N-type work function layer 160, the step of removing the protection layer 140 (refer to fig. 15) is further included, so as to expose the surface of the P-type work function layer 130. The N-type work function layer 160 covers the surface of the P-type work function layer 130.
In this embodiment, the N-type work function layer 160 covers the surface of the P-type work function layer 130, the sidewall of the second opening 220, and the top of the silicide layer 320.
In this embodiment, the material of the N-type work function layer 160 contains aluminum ions, and specifically, the material of the N-type work function layer 160 is TiAl; in addition, the material of the N-type work function layer 160 may also be TaAl, TiAlC, AlN, TiAlN, or TaAlN.
The above-mentioned process step of forming the stress layer 310 in the second opening 220 located in the substrate 100 and forming the N-type work function layer 160 is performed after the process step of forming the stress layer 310, which is helpful for preventing ion diffusion in the N-type work function layer 160 and ensuring that the work function value of the N-type work function layer 160 meets the requirement, thereby avoiding threshold voltage mismatch of a subsequently formed semiconductor structure and improving the performance of the subsequently formed semiconductor structure. If the process step of forming the N-type work function layer 160 is performed before the process step of forming the stress layer 310, the N-type work function layer 160 may undergo the formation process of the stress layer 310, the material of the N-type work function layer 160 contains aluminum ions, the aluminum ions belong to easily-diffusing ions, and are affected by the process environment for forming the stress layer 310, for example, the process temperature of the selective epitaxial growth process, and the aluminum ions in the material of the N-type work function layer 160 are easily diffused, so that the work function value of the N-type work function layer 160 changes.
In another embodiment, if the P-type work function layer is not formed on the gate dielectric layer before the protective layer is formed, after the protective layer is removed and before the N-type work function layer is formed, the method further includes: and forming a P-type work function layer on the surface of the gate dielectric layer.
Referring to fig. 17 and 18, a first metal layer 410 (see fig. 18) is formed on the N-type work function layer 160 to fill the first opening 210; a second metal layer 420 is formed on the stress layer 310 to fill the second opening 220 (see fig. 18).
In this embodiment, the second metal layer 420 covers the sidewall of the second opening 220 and the surface of the P-type work function layer 130 on the top of the silicide layer 320. In other embodiments, before forming the second metal layer, the method further includes: removing the side wall of the second opening and the P-type work function layer on the top of the silicide layer; the second metal layer thus formed covers the top of the silicide layer and the sidewalls of the second opening.
In this embodiment, the top of the first metal layer 410 and the top of the second metal layer 420 are both flush with the top of the dielectric layer 110.
In this embodiment, the first metal layer 410 and the second metal layer 420 are formed in the same process step.
The process steps for forming the first metal layer 410 and the second metal layer 420 include: referring to fig. 17, a metal film 400 is formed on the N-type work function layer 160 and the stress layer 310 to fill the first opening 210 and the second opening 220, and the metal film 400 covers the top of the dielectric layer 110; referring to fig. 18, the metal film 400 is removed above the top of the dielectric layer 110, and the metal film remaining in the first opening 210 is used as the first metal layer 410, and the metal film remaining in the second opening 220 is used as the second metal layer 420.
In this embodiment, the metal film 400 is made of tungsten. In other embodiments, the material of the metal film may also be copper, aluminum or silver.
In this embodiment, a chemical mechanical polishing process is used to remove the metal film 400 above the top of the dielectric layer 110.
Forming the first metal layer 410 and the second metal layer 420 in the same process step can simplify the process steps for forming the first metal layer 410 and the second metal layer 420, thereby reducing the manufacturing cost.
In summary, forming the N-type work function layer 160 after the stress layer 310 is formed can prevent the N-type work function layer 160 from undergoing the formation process of the stress layer 310, thereby preventing the ion diffusion in the material of the N-type work function layer 160, and ensuring that the work function value of the N-type work function layer 160 meets the requirement, thereby ensuring that the threshold voltage of the semiconductor structure is proper, and improving the performance of the semiconductor structure.
Referring to fig. 14, the present invention also provides a semiconductor structure obtained by the above forming method, the semiconductor structure including: a substrate 100, wherein a dielectric layer 110 is disposed on the substrate 100, and a first opening penetrating through the thickness of the dielectric layer 110 is disposed in the dielectric layer 110; stress layers 310 in the substrate 100 on both sides of the first opening; and a second opening 220 located in the dielectric layer 110 and penetrating through the thickness of the dielectric layer 110, wherein the second opening 220 exposes the surface of the stress layer 310.
In this embodiment, the semiconductor structure further includes: a gate dielectric layer 120 located on the surface of the substrate 100 exposed by the first opening; the P-type work function layer 130 is positioned on the surface of the gate dielectric layer 120 and the side wall of the first opening; and a protective layer 140 on the surface of the P-type work function layer 130.
In this embodiment, the substrate 100 includes: the semiconductor structure comprises a substrate 101, a fin portion 102 protruding out of the substrate 101, and an isolation layer 103 located on the substrate 101, wherein the isolation layer 103 covers part of the sidewall surface of the fin portion 102.
The gate dielectric layer 120 includes an interfacial layer 121 and a high-k gate dielectric layer 122 on top of the interfacial layer 121.
In this embodiment, the interface layer 121 is made of silicon oxide. In other embodiments, the material of the interface layer may also be germanium oxide, and the material of the interface layer may also be oxygen-doped silicon germanium, oxygen-doped gallium arsenide, or oxygen-doped indium gallium.
In this embodiment, the high-k gate dielectric layer 122 covers the top of the dielectric layer 110 and the sidewall of the first opening 210, in addition to the top of the interfacial layer 121.
In this embodiment, the P-type work function layer 130 is made of TiN. In other embodiments, the material of the P-type work function layer may also be TaN, TiSiN, or TaSiN.
The protection layer 140 serves to protect the surface of the P-type work function layer 130.
In this embodiment, the material of the protection layer 140 is silicon oxide. In other embodiments, the material of the protective layer may also be silicon nitride or silicon carbide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a dielectric layer is arranged on the substrate, and a first opening penetrating through the thickness of the dielectric layer is formed in the dielectric layer;
forming second openings in the substrate and the dielectric layer on two sides of the first opening, wherein the second openings penetrate through the thickness of the dielectric layer and the substrate with partial thickness;
forming a stress layer in the second opening in the substrate;
after the stress layer is formed, forming an N-type work function layer on the bottom and the side wall of the first opening;
forming a first metal layer which is filled in the first opening on the N-type work function layer;
forming a second metal layer which is filled in the second opening on the stress layer;
after providing the substrate, before forming the second opening, the method further includes: forming a gate dielectric layer on the surface of the substrate exposed by the first opening;
before forming the second opening, and after forming the gate dielectric layer, the method further includes: forming an anti-reflection coating which is filled in the first opening on the gate dielectric layer; before forming the stress layer and after forming the second opening, the method further includes: removing the anti-reflection coating;
after the gate dielectric layer is formed and before the anti-reflection coating is formed, the method further comprises the following steps: forming a protective layer on the gate dielectric layer and the side wall of the first opening; before forming the N-type work function layer, and after forming the stress layer, the method further includes: and removing the protective layer.
2. The method for forming a semiconductor structure according to claim 1, wherein a process temperature for forming the stress layer is 300 ℃ to 900 ℃.
3. The method of forming a semiconductor structure according to claim 1 or 2, wherein the stress layer is formed using a selective epitaxial growth process.
4. The method of forming a semiconductor structure of claim 3, wherein the process parameters of the selective epitaxial growth process comprise: the temperature is 600 ℃ to 850 ℃, the pressure is 8Torr to 300Torr, the process gas comprises H2、HCl、SiH2Cl2、GeH4And B2H6Wherein, the H2The gas flow rate of (1) is 10sccm to 3000sccm, the gas flow rate of HCl is 10sccm to 200sccm, and the SiH2Cl2The gas flow rate of the GeH is 20sccm to 2000sccm4The gas flow rate of (B) is 10sccm to 500sccm2H6The gas flow rate of (2) is 5sccm to 100 sccm.
5. The method of claim 1, wherein the N-type work function layer comprises aluminum ions.
6. The method of forming a semiconductor structure of claim 5, wherein a material of the N-type work function layer is TiAl, TaAl, TiAl C, AlN, TiAlN, or TaAlN.
7. The method of claim 1, wherein the first metal layer and the second metal layer are formed in a same process step.
8. The method of forming a semiconductor structure of claim 7, wherein the process steps of forming the first and second metal layers comprise: forming a metal film filled in the first opening and the second opening on the N-type work function layer and the stress layer, wherein the metal film covers the top of the dielectric layer; and removing the metal film higher than the top of the dielectric layer, wherein the metal film remained in the first opening is used as the first metal layer, and the metal film remained in the second opening is used as the second metal layer.
9. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the N-type work function layer: and forming a metal silicide layer on the surface of the stress layer.
10. The method of claim 1, wherein the gate dielectric layer comprises a thermal oxidation process.
11. The method of claim 10, wherein a process temperature of the thermal oxidation process is 750 ℃ to 1000 ℃.
12. The method of claim 1, wherein after forming the gate dielectric layer and before forming the protective layer, further comprising: and forming a P-type work function layer on the surface of the gate dielectric layer and the side wall of the first opening.
13. The method of claim 1, wherein after forming the gate dielectric layer and before forming the second opening, further comprising: and adopting an annealing process to carry out densification treatment on the gate dielectric layer.
14. The method of claim 13, wherein the densification process is performed at a process temperature of 800 ℃ to 1050 ℃.
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