CN109980004A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109980004A CN109980004A CN201711446096.4A CN201711446096A CN109980004A CN 109980004 A CN109980004 A CN 109980004A CN 201711446096 A CN201711446096 A CN 201711446096A CN 109980004 A CN109980004 A CN 109980004A
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- 238000000034 method Methods 0.000 title claims abstract description 94
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 239000002184 metal Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 21
- 238000011049 filling Methods 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 421
- 239000000463 material Substances 0.000 claims description 56
- 230000008569 process Effects 0.000 claims description 46
- 239000011248 coating agent Substances 0.000 claims description 26
- 238000000576 coating method Methods 0.000 claims description 26
- 239000011241 protective layer Substances 0.000 claims description 25
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 238000000280 densification Methods 0.000 claims description 14
- 229910021332 silicide Inorganic materials 0.000 claims description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 8
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 7
- 229910015148 B2H6 Inorganic materials 0.000 claims description 6
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 6
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 6
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- 229910004490 TaAl Inorganic materials 0.000 claims description 3
- 229910004491 TaAlN Inorganic materials 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 3
- 229910010041 TiAlC Inorganic materials 0.000 claims description 3
- 229910010037 TiAlN Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 9
- 238000000926 separation method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000036961 partial effect Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- 229910004200 TaSiN Inorganic materials 0.000 description 2
- 229910008482 TiSiN Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, forming method include: offer substrate, have dielectric layer in the substrate, have the first opening through the thickness of dielectric layers in the dielectric layer；The second opening, substrate of second opening through the thickness of dielectric layers and segment thickness are formed in the substrate of first opening two sides and dielectric layer；Stressor layers are formed being located in intrabasement second opening；After forming the stressor layers, N-type workfunction layer is formed in first open bottom and side wall；The first metal layer of full first opening of filling is formed on the N-type workfunction layer；The second metal layer of full second opening of filling is formed in the stressor layers.The present invention forms N-type workfunction layer after stressor layers formation, advantageously ensures that the work function value of N-type workfunction layer meets the requirements, can be avoided the threshold voltage mismatch of semiconductor structure, improves the performance of semiconductor structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In semiconductor fabrication, as integrated circuit feature size persistently reduces, the channel length of MOSFET also it is corresponding not
It is disconnected to shorten.However, the distance between device source electrode and drain electrode also shorten therewith with the shortening of device channel length, lead to grid
It is extremely deteriorated to the control ability of channel, short-channel effect (SCE:short-channel effects) is easier to occur.
Fin formula field effect transistor (FinFET) has performance outstanding, the grid of FinFET in terms of inhibiting short-channel effect
Best can control fin from two sides less, thus compared with planar MOSFET, control of the grid of FinFET to channel
Ability is stronger, can be good at inhibiting short-channel effect.
But the performance of semiconductor structure is still to be improved in the prior art.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, helps to ensure that N-type work function
The work function value of layer meets the requirements, and can be avoided the threshold voltage mismatch of semiconductor structure, improves the performance of semiconductor structure.
To solve the above problems, the present invention provides a kind of method for forming semiconductor structure, comprising: provide substrate, the base
There is dielectric layer on bottom, there is the first opening through the thickness of dielectric layers in the dielectric layer；In first opening two
The second opening is formed in the substrate and dielectric layer of side, second opening runs through the thickness of dielectric layers and segment thickness
Substrate；Stressor layers are formed being located in intrabasement second opening；After forming the stressor layers, described first
N-type workfunction layer is formed on open bottom and side wall；The of full first opening of filling is formed on the N-type workfunction layer
One metal layer；The second metal layer of full second opening of filling is formed in the stressor layers.
Optionally, the technological temperature for forming the stressor layers is 300 DEG C~900 DEG C.
Optionally, the stressor layers are formed using selective epitaxial growth process.
Optionally, it is 600 DEG C to 850 DEG C that the technological parameter of the selective epitaxial growth process, which includes: temperature, and air pressure is
8Torr to 300Torr, process gas include and H2, HCl, SiH2Cl2, GeH4 and B2H6, wherein the gas flow of the H2
Gas flow for 10sccm to 3000sccm, the HCl is 10sccm to 200sccm, and the gas flow of the SiH2Cl2 is
The gas flow of 20sccm to 2000sccm, the GeH4 are 10sccm to 500sccm, and the gas flow of the B2H6 is
5sccm to 100sccm.
Optionally, contain aluminium ion in the N-type workfunction layer.
Optionally, the material of the N-type workfunction layer is TiAl, TaAl, TiAlC, AlN, TiAlN or TaAlN.
Optionally, the first metal layer and second metal layer in processing step, are being formed with along with.
Optionally, the processing step for forming the first metal layer and second metal layer includes: in the N-type workfunction layer
And the metal film of full first opening of filling and the second opening is formed in stressor layers, and the metal film covers the dielectric layer
Top；Removal is higher than the metal film at the top of the dielectric layer, and residue is located at the metal film in first opening as institute
The first metal layer is stated, residue is located at the metal film in second opening as the second metal layer.
Optionally, before forming the N-type workfunction layer, further includes: form metal silicide layer in the stress layer surface.
Optionally, after providing substrate, before forming second opening, further includes: in the substrate that first opening is exposed
Surface forms gate dielectric layer.
Optionally, the forming method of the gate dielectric layer includes thermal oxidation processes.
Optionally, the technological temperature of the thermal oxidation processes is 750 DEG C~1000 DEG C.
Optionally, before forming second opening, and after forming the gate dielectric layer, further includes: in the gate medium
The anti-reflection coating of full first opening of filling is formed on layer；It is opened before forming the stressor layers, and forming described second
After mouthful, further includes: remove the anti-reflection coating.
Optionally, after forming the gate dielectric layer, before forming the anti-reflection coating, further includes: in the gate dielectric layer
Upper and described first opening sidewalls form protective layer；Before forming the N-type workfunction layer, and after forming the stressor layers, also
It include: the removal protective layer.
Optionally, after forming the gate dielectric layer, and before forming the protective layer, further includes: in the gate dielectric layer
P-type workfunction layer is formed on surface and first opening sidewalls.
Optionally, after forming the gate dielectric layer, and before forming second opening, further includes: use annealing process
Densification is carried out to the gate dielectric layer.
Optionally, the technological temperature of the densification is 800 DEG C~1050 DEG C.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate has dielectric layer in the substrate, described
There is the first opening through the thickness of dielectric layers in dielectric layer；Described intrabasement answering positioned at first opening two sides
Power layer；The second opening in the dielectric layer and through the thickness of dielectric layers, second opening expose the stress
Layer surface.
Optionally, the semiconductor structure further include: the gate dielectric layer of the substrate surface exposed positioned at first opening.
Optionally, the semiconductor structure further include: be located on the gate dielectric layer surface and first opening sidewalls
P-type workfunction layer；Protective layer positioned at the P-type workfunction layer surface.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the forming method of semiconductor structure provided by the invention, has in dielectric layer and run through the medium
First opening of thickness degree；The second opening, second opening are formed in the substrate of first opening two sides and dielectric layer
Through the substrate of the thickness of dielectric layers and segment thickness；Stress is formed being located in intrabasement second opening
Layer.When forming the stressor layers, N-type workfunction layer is not present in first opening, after forming the stressor layers, described
N-type workfunction layer is formed on first open bottom and side wall.The present invention forms the N-type work content after stressor layers formation
Several layers, avoidable N-type workfunction layer undergoes the forming process of the stressor layers, thus prevent in N-type workfunction layer material from
Son diffusion, advantageously ensures that the work function value of N-type workfunction layer meets the requirements, and the threshold voltage that can be avoided semiconductor structure loses
Match, improves the performance of semiconductor structure.
In optinal plan, in processing step, the first metal layer and second metal layer are being formed with along with, is keeping processing step simple
Change, advantageously reduces manufacturing cost.
In optinal plan, the technological temperature for forming the stressor layers is 300 DEG C~900 DEG C, be can avoid in the stressor layers
It is formed defective, is conducive to the formation quality for improving the stressor layers；And it helps avoid the stressor layers generation stress to release
It puts, so that proof stress layer is appropriate to the stress intensity of channel.
In optinal plan, after substrate is provided, before forming second opening, the forming method further include: described the
The substrate surface that one opening is exposed forms gate dielectric layer, forms the gate dielectric layer before forming the stressor layers, facilitates
The process environments for avoiding the formation of the gate dielectric layer cause the stressor layers that stress release occurs.
In optinal plan, the technological temperature of the thermal oxidation processes is 750 DEG C~1000 DEG C, the thermal oxidation
The technological temperature of technique suitably helps to improve the uniformity and consistency of the gate dielectric layer, so that the gate medium can be improved
The formation quality of layer.
In optinal plan, the technological temperature of the densification is 800 DEG C~1050 DEG C, the work of the densification
Skill temperature is appropriate, can reduce the defects of described gate dielectric layer material, helps to improve the semiconductor structure being subsequently formed
Carrier mobility.
Detailed description of the invention
Fig. 1 to Fig. 6 is the corresponding structural schematic diagram of each step in a kind of forming method of semiconductor structure；
Fig. 7 to Figure 18 is the corresponding structural schematic diagram of each step in one embodiment of method for forming semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that the performance of existing semiconductor structure is still to be improved.
It is analyzed now in conjunction with a kind of forming method of semiconductor structure, Fig. 1 to Fig. 6 is a kind of formation of semiconductor structure
The corresponding structural schematic diagram of each step, the processing step for forming semiconductor structure specifically include that in method
With reference to Fig. 1, substrate 10 is provided, there is dielectric layer 11 in the substrate 10, have in the dielectric layer 11 and run through institute
State the first opening 21 of 11 thickness of dielectric layer.
With reference to Fig. 2, gate dielectric layer 12 is formed in the first opening 21 (referring to Fig. 1) bottom.
With reference to Fig. 3, N-type workfunction layer is formed at the top of 21 (the referring to Fig. 1) side wall of the first opening and gate dielectric layer 12
16。
With reference to Fig. 4, the metal gate of full first opening 21 (referring to Fig. 1) of filling is formed on 16 surface of N-type workfunction layer
41。
The substrate 10 with reference to Fig. 5, after forming the metal gate 41, in the first opening 21 (referring to Fig. 1) two sides
And the second opening 22 is formed in dielectric layer 11, second opening 22 is through 11 thickness of dielectric layer and the base of segment thickness
Bottom 10.
With reference to Fig. 6, stressor layers 31 are formed in second opening 22 (referring to Fig. 5) being located in the substrate 10.
The performance for the semiconductor structure that the above method is formed is poor, analyzes its reason and is:
Contain easy diffusion ion, such as aluminium ion in 16 material of N-type workfunction layer.By the technique for forming stressor layers 31
Environment influences, such as forms the technological temperature influence of stressor layers 31, and the easy diffusion ion in 16 material of N-type workfunction layer holds
It easily spreads, so that the work function value of N-type workfunction layer 16 changes, thus the threshold voltage of semiconductor structure is caused to lose
Match, the performance of semiconductor structure is caused to decline.
For this purpose, the present invention provides a kind of method for forming semiconductor structure, comprising: substrate and medium in the first opening two sides
The second opening, substrate of second opening through the thickness of dielectric layers and segment thickness are formed in layer；It is described being located at
Stressor layers are formed in intrabasement second opening；After forming the stressor layers, in first open bottom and side wall
Form N-type workfunction layer.
The present invention carries out after the forming step of N-type workfunction layer to be arranged in the forming step of stressor layers, can avoid N-type
Work-function layer undergoes the forming process of the stressor layers, to prevent the ion in N-type workfunction layer material from spreading, is conducive to protect
The work function value of card N-type workfunction layer meets the requirements, and can be avoided the threshold voltage mismatch of semiconductor structure, improves semiconductor junction
The performance of structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 7 to Figure 18 is the structural schematic diagram that the semiconductor structure that one embodiment of the invention provides forms process.
With reference to Fig. 7, substrate 100 is provided, there is dielectric layer 110 in the substrate 100, have in the dielectric layer 110 and pass through
Wear the first opening 210 of 110 thickness of dielectric layer.
In the present embodiment, the substrate 100 includes: substrate 101, protrudes from the fin 102 of the substrate 101 and be located at
Separation layer 103 on the substrate 101, the separation layer 103 cover the partial sidewall surface of the fin 102.
The material of the substrate 101 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium, and the substrate 101 can also
It is enough the germanium substrate on the silicon substrate or insulator on insulator；In the present embodiment, the substrate 101 is silicon substrate.
In the present embodiment, the material of the fin 102 is identical as 101 material of substrate, is also silicon.In other embodiments
In, the material of the fin 102 can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
The material of the separation layer 103 is silica, silicon nitride or silicon oxynitride.In the present embodiment, the separation layer 103
Material be silicon oxynitride.
The material of the dielectric layer 110 is insulating materials.In the present embodiment, the material of the dielectric layer 110 is silica.
In other embodiments, the material of the dielectric layer can also be silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, nitrogen oxygen
SiClx, boron nitride or boron carbonitrides.
The processing step for forming the dielectric layer 110 and the first opening 210 includes: that cross is formed on the separation layer 103
Pseudo- grid (not shown) across fin 102, the puppet grid cover the atop part and partial sidewall of the fin 102；It is described every
Deielectric-coating (not shown) is formed on absciss layer 103, is higher than at the top of the pseudo- grid at the top of the deielectric-coating；Remove the described of segment thickness
Deielectric-coating exposes at the top of the pseudo- grid, and the remaining deielectric-coating is as the dielectric layer 110；The pseudo- grid are removed, described in formation
First opening 210.
In the present embodiment, after forming the pseudo- grid, before forming the deielectric-coating, further includes: the shape on the pseudo- grid side wall
At side wall 104.After removing the pseudo- grid, retain the side wall 104.
During removing the pseudo- grid, the side wall 104 can protect 110 side wall of dielectric layer, avoid being given an account of
110 side wall of matter layer is etched.
In the present embodiment, the material of the side wall 104 is carbonitride of silicium, in other embodiments, the material of the side wall 104
Material can also be silicon nitride, silicon carbide, carbon silicon oxynitride, silicon oxynitride.
With reference to Fig. 8, gate dielectric layer 120 is formed on 100 surface of substrate that first opening 210 (referring to Fig. 7) is exposed.
The gate dielectric layer 120 includes boundary layer 121 and the high-k gate dielectric layer positioned at 121 top of boundary layer
122。
The boundary layer 121 can be to form high-k gate dielectric layer 122 to provide good interface basis, be conducive to improve institute
The formation quality for stating high-k gate dielectric layer 122, the interfacial state reduced between 102 top of the high-k gate dielectric layer 122 and fin are close
Degree.
In the present embodiment, the material of the boundary layer 121 is silica.In other embodiments, the material of the boundary layer
Material can also be germanium oxide, and in addition the material of the boundary layer can also be the SiGe for mixing oxygen, mix the GaAs of oxygen or mix oxygen
Gallium indium.
The forming method of the gate dielectric layer 120 includes thermal oxidation processes.Specifically, in the present embodiment, using heat
Oxidation processing technique forms the boundary layer 121.
If the technological temperature of the thermal oxidation processes is too low, the uniformity of the boundary layer 121 resulted in and
Low density influences the boundary layer 121 and imitates to the improvement of the interface basis between 102 top of high-k gate dielectric layer 122 and fin
Fruit.In the present embodiment, the technological temperature of the thermal oxidation processes is 750 DEG C~1000 DEG C.
In the present embodiment, the high-k gate dielectric layer 122 also covers the medium in addition to covering 121 top of boundary layer
110 top of layer and first opening 210 (referring to Fig. 7) side wall, the high-k gate dielectric at subsequent removal 110 top of dielectric layer
Layer 122 retains the high-k gate dielectric layer 122 for being located at 121 top of first 210 side walls of opening and the boundary layer.
In the present embodiment, the formation process of the high-k gate dielectric layer 122 is atom layer deposition process.The atomic layer deposition
Corner of the product technique between the first 210 bottoms of opening and side wall has good step coverage, and the high k grid of formation are situated between
122 thickness of matter layer is uniform.
The material of the high-k gate dielectric layer 122 is high K medium material (dielectric constant is greater than 3.9).In the present embodiment, institute
The material for stating high-k gate dielectric layer 122 is HfO2；In other embodiments, the material of the high-k gate dielectric layer can also be
HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO2。
Subsequent the second opening of formation in the substrate 100 of first opening, 210 two sides and dielectric layer 110, and
Stressor layers are formed in second opening in the substrate 100.The gate dielectric layer 120 forms it in the stressor layers
Preceding formation, the process environments for helping to prevent from being formed the gate dielectric layer 120 cause the stressor layers that stress release occurs, so that
The stressor layers are difficult to generate suitable stress intensity to channel.If the gate dielectric layer 120 is after stressor layers formation
It is formed, the stressor layers will undergo the thermal oxidation processes process, in the technological temperature shadow of the thermal oxidation processes
Under sound, the stressor layers are easy to happen stress release.
With reference to Fig. 9, p-type is formed on 120 surface of gate dielectric layer and first opening 210 (referring to Fig. 7) side wall
Work-function layer 130.
In the present embodiment, the P-type workfunction layer 130 covers 122 surface of high-k gate dielectric layer.It is subsequent with along with
High-k gate dielectric layer 122 and P-type workfunction layer 130 in processing step, on 110 top of removal dielectric layer.
In the present embodiment, the material of the P-type workfunction layer 130 is TiN.In other embodiments, the p-type work function
The material of layer can also be TaN, TiSiN or TaSiN.
In other embodiments, the step of forming P-type workfunction layer, which can also be arranged in, is subsequently formed the laggard of stressor layers
Row.
In the present embodiment, after forming P-type workfunction layer 130, further includes: using annealing process to the gate dielectric layer 120
Carry out densification.
The densification can reduce the defects of the boundary layer 121 and high-k gate dielectric layer 122, facilitate
Improve the carrier mobility for the semiconductor structure being subsequently formed.
If the technological temperature of the densification is too low, it is difficult to the boundary layer 121 and high-k gate dielectric layer be effectively reduced
The defects of 122 materials cause the carrier mobility for the semiconductor structure being subsequently formed low.In the present embodiment, the densification
The technological temperature for changing processing is 800 DEG C~1050 DEG C.
It is subsequent to form stressor layers in the substrate 100 of first opening, 210 two sides, the technique of the stressor layers will be formed
Procedure carries out after the processing step of the densification, can be avoided the stressor layers and undergoes at the densification
Reason process, to prevent the technological temperature by the densification from being influenced, the stressor layers are in the densification process
Middle generation stress release.
With reference to Figure 10, on the gate dielectric layer 120 and first opening 210 (referring to Fig. 7) side wall forms protective layer
140。
In the present embodiment, the protective layer 140 covers 130 surface of P-type workfunction layer, it is subsequent with along with technique walk
High-k gate dielectric layer 122, P-type workfunction layer 130 and protective layer 140 in rapid, on 110 top of removal dielectric layer.
It is subsequently formed the anti-reflection coating of full first opening 210 of filling, it is described anti-in subsequent removal in the present embodiment
During reflectance coating, the protective layer 140 can play the role of protection 130 surface of P-type workfunction layer, thus anti-
Only 130 surface of P-type workfunction layer is etched.
In other embodiments, the protective layer cover grid dielectric layer surface, in the subsequent removal anti-reflection coating
In the process, the protective layer can protect the gate dielectric layer surface, and the gate dielectric layer is avoided to be etched.
In the present embodiment, the material of the protective layer 140 is silica.In other embodiments, the material of the protective layer
Material can also be silicon nitride or silicon carbide.
It should be noted that in other embodiments, can also directly carry out subsequent shape after forming the gate dielectric layer
At the processing step of anti-reflection coating.
With reference to Figure 11, the anti-reflective of full first opening 210 (referring to Fig. 7) of filling is formed on the gate dielectric layer 120
Penetrate coating 150.
The anti-reflection coating 150 can be avoided the processing step for being subsequently formed the second opening 220 to first opening
210 side walls and bottom surface are polluted or are damaged.
In the present embodiment, 150 top of the anti-reflection coating with flushed at the top of the dielectric layer 110.
In the present embodiment, the processing step for forming the anti-reflection coating 150 includes: to form the covering protective layer 140
Antireflection film (not shown), be higher than 110 top of dielectric layer at the top of the antireflection film；Removal is higher than the medium
The antireflection film at 110 top of layer, forms the anti-reflection coating 150.
In the present embodiment, it is higher than the processing step of the antireflection film at 110 top of dielectric layer in removal further include: go
Except protective layer 140, P-type workfunction layer 130 and the high-k gate dielectric layer 122 being located on 110 top of dielectric layer.
In the present embodiment, the material of the anti-reflection coating 150 includes siliceous oxycarbide.
With reference to Figure 12, formed in the substrate 100 of the first opening 210 (referring to Fig. 7) two sides and dielectric layer 110
Second opening 220, substrate 100 of second opening 220 through 110 thickness of dielectric layer and segment thickness.
In the present embodiment, second opening 220 is located at the fin 102 and medium of first opening, 210 two sides
In layer 110, and through 110 thickness of dielectric layer and the fin 102 of segment thickness.
Second opening 220 provides spatial position to be subsequently formed stressor layers and second metal layer.
In the present embodiment, the processing step for forming second opening 220 includes: at part 110 top of dielectric layer
Photoresist layer (not shown) is formed, the photoresist layer also covers 150 top of anti-reflection coating；It is to cover with the photoresist layer
Film etches the dielectric layer 110 until exposing 102 surface of fin；The fin 102 that segment thickness exposes is removed, forms described the
Two openings 220.
In the present embodiment, the dielectric layer 110 and fin 102, the dry etching work are etched using dry etch process
The technological parameter of skill includes: that etching gas includes CH4And CHF3, wherein CH4Gas flow be 8sccm to 500sccm, CHF3
Gas flow be 30sccm to 200sccm, chamber pressure be 10mTorr to 2000mTorr, radio-frequency power be 100W extremely
1300W, it is 80V to 500V that DC self-bias, which sets voltage, and etching gas is passed through the time as 4s to 500s.
With reference to Figure 13, remove the anti-reflection coating 150 (with reference to Figure 12).
It is subsequent to form stressor layers in second opening 220, the anti-reflection coating 150 is removed to prevent the anti-reflective
Coating 150 is penetrated to impact the quality of stressor layers.If retaining the anti-reflection coating 150, in the mistake for being subsequently formed stressor layers
Cheng Zhong, the anti-reflection coating 150 is easy to pollute the stressor layers, so that the formation of the stressor layers is of poor quality.
With reference to Figure 14, stressor layers are formed in second opening 220 (referring to Figure 12) being located in the substrate 100
310。
Source and drain doping area of the stressor layers 310 as the semiconductor structure being subsequently formed.In the present embodiment, the stress
The material of layer 310 is SiGe.
In the present embodiment, the stressor layers 310 are formed using selective epitaxial growth process.Using the selective epitaxial
The lattice match of the stressor layers 310 and 102 storeroom of fin that growth technique is formed is high, is conducive to answer described in improvement
The formation quality of power layer 310.
If the technological temperature for forming the stressor layers 310 is too low, it is easy that there is defect in the stressor layers 310, influences institute
State the formation quality of stressor layers 310；If the technological temperature for forming the stressor layers 310 is excessively high, the stressor layers 310 are easy to happen
Stress release, the stressor layers 310 are difficult to generate stress appropriate to channel.In the present embodiment, the stressor layers 310 are formed
Technological temperature is 300 DEG C~900 DEG C.
The technological parameter of the selective epitaxial growth process include: temperature be 600 DEG C to 850 DEG C, air pressure be 8Torr extremely
300Torr, process gas include and H2, HCl, SiH2Cl2, GeH4 and B2H6, wherein the gas flow of the H2 is 10sccm
To 3000sccm, the gas flow of the HCl is 10sccm to 200sccm, the gas flow of the SiH2Cl2 be 20sccm extremely
The gas flow of 2000sccm, the GeH4 are 10sccm to 500sccm, the gas flow of the B2H6 be 5sccm extremely
100sccm。
It is subsequent to form N-type workfunction layer on first 210 bottoms of opening and side wall, the stressor layers 310 will be formed
Processing step be arranged in the processing step to form N-type workfunction layer before carry out, can be avoided to form the stressor layers 310
Process environments cause N-type workfunction layer material that ion diffusion occurs.
It is aforementioned to form gate dielectric layer 120 on 100 surface of substrate that first opening 210 is exposed, in the gate dielectric layer
120 formed after form the stressor layers 310, be conducive to avoid the formation of the gate dielectric layer 120 process environments make it is described
Stressor layers 310 discharge stress, so that 310 pairs of channel of proof stress layer have stress appropriate.If being initially formed the stress
Layer 310 forms the gate dielectric layer 120 afterwards, since the forming method of the gate dielectric layer 120 includes thermal oxidation processes,
And due to the technological temperature of thermal oxidation processes height, cause the stressor layers 310 in the thermal oxidation processes
It is easy release stress in the process, to be difficult to generate stress appropriate to channel.
With reference to Figure 15, metal silicide layer 320 is formed on 310 surface of stressor layers.
It is subsequently formed the second metal layer of full second opening 220 (with reference to Figure 12) of filling, the metal silicide layer 320
The dead resistance that can reduce 310 surface of stressor layers, is conducive to the fax between the stressor layers 310 and second metal layer
It leads.
The processing step for forming the metal silicide layer 320 includes: at 110 top of dielectric layer, second opening
220 side walls and the stressor layers form conductive film (not shown) on 310 top；The conductive film is made annealing treatment, is made
The conductive film on 310 surface of stressor layers is changed into metal silicide layer 320；It removes 110 top of the dielectric layer, described second open
Conductive film on 220 side walls of mouth.
In the present embodiment, the material of the conductive film is Ti.In other embodiments, the material of the conductive film can be with
For Ni or Co.
If too low to the temperature of the annealing of conductive film progress, the silication that can not trigger the conductive film is anti-
It answers, leads to not to form metal silicide layer 320.In the present embodiment, the temperature of the annealing is 850~1000 DEG C.
It is subsequent to form N-type workfunction layer on first 210 bottoms of opening and side wall, in the N-type workfunction layer shape
At the metal silicide layer 320 is formed before, help to prevent N-type workfunction layer material from forming the metal silicide layer 320
Ion diffusion occurs in the process, to guarantee the work function size of N-type workfunction layer.If be initially formed the N-type workfunction layer, after
The metal silicide layer 320 is formed, experience is formed the annealing treating process mistake of metal silicide layer 320 by the N-type workfunction layer
Journey, the annealing treating process temperature is high, and the easy diffusion ion in N-type workfunction layer is easy to cause to spread.
With reference to Figure 16, N-type workfunction layer 160 is formed on 210 (the referring to Figure 12) bottom of the first opening and side wall.
It further include removing the protective layer 140 (with reference to Figure 15) before forming N-type workfunction layer 160 in the present embodiment, from
And expose 130 surface of P-type workfunction layer.The N-type workfunction layer 160 covers 130 surface of P-type workfunction layer.
In the present embodiment, the N-type workfunction layer 160 is covered outside 130 surface of P-type workfunction layer, also described in covering
320 top of second 220 side walls of opening and the metal silicide layer.
In the present embodiment, contain aluminium ion in 160 material of N-type workfunction layer, specifically, the N-type workfunction layer
160 material is TiAl；In addition, the material of the N-type workfunction layer 160 can also for TaAl, TiAlC, AlN, TiAlN or
TaAlN。
It is aforementioned to form stressor layers 310 in second opening 220 being located in the substrate 100, form the N-type function
The processing step of function layer 160 carries out after being arranged in the processing step to form stressor layers 310, helps to prevent N-type work function
Ion diffusion in layer 160, guarantees that the work function value of N-type workfunction layer 160 meets the requirements, so that avoid being subsequently formed partly leads
The threshold voltage mismatch of body structure improves the performance for the semiconductor structure being subsequently formed.If forming the N-type workfunction layer 160
Processing step be arranged in the processing step to form stressor layers 310 before carry out, then the N-type workfunction layer 160 can undergo institute
The forming process of stressor layers 310 is stated, contains aluminium ion in 160 material of N-type workfunction layer, the aluminium ion belongs to easy diffusion
Ion is influenced by the process environments for forming the stressor layers 310, such as the technological temperature shadow of the selective epitaxial growth process
It rings, the aluminium ion in 160 material of N-type workfunction layer is easy diffusion, and the work function value of N-type workfunction layer 160 is caused to occur
Variation.
It should be noted that in other embodiments, the aforementioned not shape on the gate dielectric layer before forming protective layer
At P-type workfunction layer, then after removing the protective layer, before the formation N-type workfunction layer, further includes: in the grid
Dielectric layer surface forms P-type workfunction layer.
With reference to Figure 17 and Figure 18, the first of full first opening 210 of filling is formed on the N-type workfunction layer 160
Metal layer 410 (refers to Figure 18)；The second metal layer 420 of full second opening 220 of filling is formed in the stressor layers 310
(referring to Figure 18).
In the present embodiment, the covering of second metal layer 420 is located at second 220 side walls of opening and silication gold
Belong to 130 surface of P-type workfunction layer at 320 top of layer.In other embodiments, before forming the second metal layer, further includes: go
Except the P-type workfunction layer at the top of second opening sidewalls and the metal silicide layer；The second metal layer thus formed is covered
Lid metal silicide layer top and second opening sidewalls.
In the present embodiment, at the top of 410 top of the first metal layer and second metal layer 420 with the dielectric layer 110
Top flushes.
In the present embodiment, the first metal layer 410 and second metal layer 420 in processing step, are being formed with along with.
The processing step for forming the first metal layer 410 and second metal layer 420 includes: with reference to Figure 17, in the N-type
The metal film 400 of full first opening 210 of filling and the second opening 220 is formed in work-function layer 160 and stressor layers 310, and
The metal film 400 covers 110 top of dielectric layer；With reference to Figure 18, removal is higher than the gold at 110 top of dielectric layer
Belong to film 400, residue is located at the metal film in first opening 210 as the first metal layer 410, and residue is located at described the
Metal film in two openings 220 is as the second metal layer 420.
In the present embodiment, the material of the metal film 400 is tungsten.In other embodiments, the material of the metal film is also
It can be copper, aluminium or silver.
In the present embodiment, the metal film at 110 top of dielectric layer is higher than using chemical mechanical milling tech removal
400。
Formation can be simplified forming the first metal layer 410 and second metal layer 420 in processing step with along with
The processing step of one metal layer 410 and second metal layer 420, so as to reduce manufacturing cost.
To sum up, the N-type workfunction layer 160 is formed after the stressor layers 310 formation, can avoid N-type workfunction layer
The forming process of the 160 experience stressor layers 310, to prevent the ion in 160 material of N-type workfunction layer from spreading, to guarantee N
The work function value of type work-function layer 160 meets the requirements, to guarantee that the threshold voltage of semiconductor structure is appropriate, improves semiconductor junction
The performance of structure.
Referring to Fig.1 4, the present invention also provides a kind of semiconductor structure obtained using above-mentioned forming method, the semiconductors
Structure includes: substrate 100, has dielectric layer 110 in the substrate 100, has in the dielectric layer 110 and run through the dielectric layer
First opening of 110 thickness；Stressor layers 310 in the substrate 100 of first opening two sides；Positioned at the medium
The second opening 220 in layer 110 and through 110 thickness of dielectric layer, second opening 220 expose the stressor layers 310
Surface.
In the present embodiment, the semiconductor structure further include: the grid positioned at 100 surface of substrate that first opening is exposed
Dielectric layer 120；P-type workfunction layer 130 on 120 surface of gate dielectric layer and first opening sidewalls；Positioned at institute
State the protective layer 140 on 130 surface of P-type workfunction layer.
In the present embodiment, the substrate 100 includes: substrate 101, protrudes from the fin 102 of the substrate 101 and be located at
Separation layer 103 on the substrate 101, the separation layer 103 cover the partial sidewall surface of the fin 102.
The gate dielectric layer 120 includes boundary layer 121 and the high-k gate dielectric layer positioned at 121 top of boundary layer
122。
In the present embodiment, the material of the boundary layer 121 is silica.In other embodiments, the material of the boundary layer
Material can also be germanium oxide, and in addition the material of the boundary layer can also be the SiGe for mixing oxygen, mix the GaAs of oxygen or mix oxygen
Gallium indium.
In the present embodiment, the high-k gate dielectric layer 122 also covers the medium in addition to covering 121 top of boundary layer
210 side walls of 110 top of layer and first opening.
In the present embodiment, the material of the P-type workfunction layer 130 is TiN.In other embodiments, the p-type work function
The material of layer can also be TaN, TiSiN or TaSiN.
The effect of the protective layer 140 is to protect 130 surface of P-type workfunction layer.
In the present embodiment, the material of the protective layer 140 is silica.In other embodiments, the material of the protective layer
Material can also be silicon nitride or silicon carbide.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, there is dielectric layer in the substrate, have in the dielectric layer and opened through the first of the thickness of dielectric layers
Mouthful；
The second opening is formed in the substrate of first opening two sides and dielectric layer, second opening, which runs through, to be given an account of
The substrate of matter thickness degree and segment thickness；
Stressor layers are formed being located in intrabasement second opening；
After forming the stressor layers, N-type workfunction layer is formed in first open bottom and side wall；
The first metal layer of full first opening of filling is formed on the N-type workfunction layer；
The second metal layer of full second opening of filling is formed in the stressor layers.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the process warm of the stressor layers
Degree is 300 DEG C~900 DEG C.
3. the forming method of semiconductor structure as claimed in claim 1 or 2, which is characterized in that use selective epitaxial growth
Technique forms the stressor layers.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the selective epitaxial growth process
Technological parameter include: temperature be 600 DEG C to 850 DEG C, air pressure is 8Torr to 300Torr, and process gas includes and H2、HCl、
SiH2Cl2、GeH4And B2H6, wherein the H2Gas flow be 10sccm to 3000sccm, the gas flow of the HCl is
10sccm to 200sccm, the SiH2Cl2Gas flow be 20sccm to 2000sccm, the GeH4Gas flow be
10sccm to 500sccm, the B2H6Gas flow be 5sccm to 100sccm.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that contain in the N-type workfunction layer
Aluminium ion.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the material of the N-type workfunction layer
For TiAl, TaAl, TiAlC, AlN, TiAlN or TaAlN.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that with along in processing step, shape
At the first metal layer and second metal layer.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that form the first metal layer and
The processing step of two metal layers includes: that full first opening of filling and the are formed on the N-type workfunction layer and stressor layers
The metal film of two openings, and the metal film covers at the top of the dielectric layer；Removal is higher than the gold at the top of the dielectric layer
Belong to film, residue is located at the metal film in first opening as the first metal layer, and residue is located in second opening
Metal film as the second metal layer.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that before forming the N-type workfunction layer,
Further include: metal silicide layer is formed in the stress layer surface.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that after providing substrate, form described the
Before two openings, further includes: form gate dielectric layer in the substrate surface that first opening is exposed.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the formation side of the gate dielectric layer
Method includes thermal oxidation processes.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the thermal oxidation processes
Technological temperature is 750 DEG C~1000 DEG C.
13. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that before forming second opening,
And after forming the gate dielectric layer, further includes: form the antireflection of full first opening of filling on the gate dielectric layer
Coating；Before forming the stressor layers, and after forming second opening, further includes: remove the anti-reflection coating.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that after forming the gate dielectric layer,
Before forming the anti-reflection coating, further includes: on the gate dielectric layer and first opening sidewalls form protective layer；It is formed
Before the N-type workfunction layer, and after forming the stressor layers, further includes: remove the protective layer.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that after forming the gate dielectric layer,
And before forming the protective layer, further includes: form p-type work content on the gate dielectric layer surface and first opening sidewalls
Several layers.
16. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that after forming the gate dielectric layer,
And before forming second opening, further includes: carry out densification to the gate dielectric layer using annealing process.
17. the forming method of semiconductor structure as claimed in claim 16, which is characterized in that the technique of the densification
Temperature is 800 DEG C~1050 DEG C.
18. a kind of semiconductor structure characterized by comprising
Substrate has dielectric layer in the substrate, has the first opening through the thickness of dielectric layers in the dielectric layer；
The intrabasement stressor layers positioned at first opening two sides；
The second opening in the dielectric layer and through the thickness of dielectric layers, second opening expose the stressor layers
Surface.
19. semiconductor structure as claimed in claim 18, which is characterized in that further include: expose positioned at first opening
The gate dielectric layer of substrate surface.
20. semiconductor structure as claimed in claim 19, which is characterized in that further include: be located at the gate dielectric layer surface and
P-type workfunction layer on first opening sidewalls；Protective layer positioned at the P-type workfunction layer surface.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070138559A1 (en) * | 2005-12-16 | 2007-06-21 | Intel Corporation | Replacement gates to enhance transistor strain |
| US20100052074A1 (en) * | 2008-08-26 | 2010-03-04 | Chien-Ting Lin | Metal gate transistor and method for fabricating the same |
| CN105990137A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof, and semiconductor structure and forming method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070138559A1 (en) * | 2005-12-16 | 2007-06-21 | Intel Corporation | Replacement gates to enhance transistor strain |
| US20100052074A1 (en) * | 2008-08-26 | 2010-03-04 | Chien-Ting Lin | Metal gate transistor and method for fabricating the same |
| CN105990137A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof, and semiconductor structure and forming method thereof |
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