CN109979889B - Semiconductor Package - Google Patents

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Publication number
CN109979889B
CN109979889B CN201811610226.8A CN201811610226A CN109979889B CN 109979889 B CN109979889 B CN 109979889B CN 201811610226 A CN201811610226 A CN 201811610226A CN 109979889 B CN109979889 B CN 109979889B
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semiconductor chip
semiconductor
substrate
pads
package
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CN201811610226.8A
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CN109979889A (en
Inventor
赵京淳
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package is provided. The semiconductor package includes: a first substrate having a first surface and a second surface opposite the first surface; a first semiconductor chip located on the first surface of the first substrate; a second semiconductor chip located on the first surface of the first substrate; a stiffener on the first semiconductor chip and the second semiconductor chip; and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on a first surface of the first substrate and a plurality of second pads on a second surface of the first substrate. The first semiconductor chip is connected to a first group of the plurality of first pads. The second semiconductor chip is connected to a second set of the first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least sidewalls of each of the first and second semiconductor chips and the stiffener.

Description

Semiconductor package
The present application claims priority from korean patent application No. 10-2017-0182025 filed in the korean intellectual property office on 12 months 28 of 2017, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
Example embodiments of the present disclosure relate to a semiconductor package including a plurality of semiconductor chips.
Background
With the continued development of the electronics industry, there has been an increasing need for high performance, high speed and small size electronic components. In response to this trend, semiconductor packages have been manufactured in such a manner that a plurality of semiconductor chips are mounted on a single interposer or package substrate. The difference in thermal expansion coefficient between the elements constituting the semiconductor package may cause warpage in the semiconductor package. The magnitude of warpage may increase in a semiconductor package including a plurality of semiconductor chips.
Disclosure of Invention
According to example embodiments of the inventive concepts, a semiconductor package may include: a first substrate having a first surface and a second surface opposite the first surface, the first substrate comprising a plurality of first pads on the first surface of the first substrate and a plurality of second pads on the second surface of the first substrate; a first semiconductor chip on the first surface of the first substrate, the first semiconductor chip being connected to a first group of the first pads; a second semiconductor chip on the first surface of the first substrate, the second semiconductor chip being connected to a second set of first pads of the plurality of first pads; a stiffener on the first semiconductor chip and the second semiconductor chip, the stiffener covering a space between the first semiconductor chip and the second semiconductor chip; and an encapsulant on the first surface of the first substrate, the encapsulant covering at least sidewalls of each of the first and second semiconductor chips and the stiffener.
According to example embodiments of the inventive concepts, a semiconductor package may include: a first substrate having opposing first and second surfaces, wherein the first substrate comprises a plurality of first pads on the first surface of the first substrate and a plurality of second pads on the second surface of the first substrate; a first semiconductor chip on a first surface of the first substrate, wherein the first semiconductor chip is connected to a first portion of the plurality of first pads and includes a step portion lower than an upper surface of the first semiconductor chip; a second semiconductor chip on the first surface of the first substrate, wherein the second semiconductor chip is connected to the second portions of the plurality of first pads and has an upper surface substantially flush with the surface of the stepped portion of the first semiconductor chip; a stiffener located on the step portion of the first semiconductor chip and the second semiconductor chip, wherein the stiffener covers a space between the first semiconductor chip and the second semiconductor chip and has a flat plate shape; and an encapsulant on the first surface of the first substrate, wherein the encapsulant covers sidewalls of the first semiconductor chip, sidewalls of the second semiconductor chip, and sidewalls of the stiffener.
According to example embodiments of the inventive concepts, a semiconductor package may include: a package substrate, wherein the package substrate includes an insulating member having opposing first and second surfaces, a plurality of first pads located on the first surface of the insulating member, a plurality of second pads located on the second surface of the insulating member, and a redistribution layer located in the insulating member and connected to the plurality of first pads and the plurality of second pads; a first semiconductor chip on the package substrate, wherein the first semiconductor chip is connected to a first group of first pads of the plurality of first pads; a second semiconductor chip on the package substrate, wherein the second semiconductor chip is connected to a second group of the plurality of first pads; a stiffener on the first semiconductor chip and the second semiconductor chip, wherein the stiffener covers a space between the first semiconductor chip and the second semiconductor chip; and an encapsulant on the package substrate, wherein the encapsulant covers at least the sidewalls of the first semiconductor chip, the sidewalls of the second semiconductor chip, and the sidewalls of the stiffener.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor package according to an example embodiment.
Fig. 2 is a plan view of the semiconductor package of fig. 1.
Fig. 3A and 3B are schematic views showing the warpage phenomenon before and after improvement, respectively, to show effects caused by the reinforcing member according to the example embodiment.
Fig. 4 is a cross-sectional view of a semiconductor package according to an example embodiment.
Fig. 5 is a plan view of the semiconductor package of fig. 4.
Fig. 6 is a schematic view showing a warp phenomenon to show effects caused by the reinforcing member according to the example embodiment.
Fig. 7 is a cross-sectional view of a module including the semiconductor package of fig. 4.
Fig. 8 is a cross-sectional view of a semiconductor package according to an example embodiment.
Fig. 9 is a plan view of the semiconductor package of fig. 8.
Fig. 10 is a cross-sectional view of a module including the semiconductor package of fig. 8.
Fig. 11, 12 and 13 are cross-sectional views of a semiconductor package according to example embodiments.
Detailed Description
Various example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. The inventive concept may, however, be embodied in many alternate forms and should not be construed as limited to only the example embodiments set forth herein.
Fig. 1 is a cross-sectional view of a semiconductor package according to an example embodiment. Fig. 2 is a plan view of the semiconductor package of fig. 1. Fig. 1 is a sectional view taken along line I-I' of fig. 2.
Referring to fig. 1 and 2, a semiconductor package 100 includes: an insert 110 having a first surface 110A and an opposing second surface 110B; a first semiconductor chip 120 on the first surface 110A of the interposer 110; a second semiconductor chip 130 on the first surface 110A of the interposer 110; and an encapsulant 160 on the first surface 110A of the insert 110. The semiconductor package 100 further includes stiffener (stiffener) 150 on the first semiconductor chip 120 and the second semiconductor chip 130.
The interposer 110 includes a substrate 111, a wiring circuit 114 in the substrate 111, a plurality of first pads (or "first pads") 112 on a first surface 110A of the interposer 110, and a plurality of second pads (or "second pads") 113 on a second surface 110B of the interposer 110. The plurality of first pads 112 and the plurality of second pads 113 may be connected to the wiring circuit 114. Although the wiring circuit 114 is shown in a part of the substrate 111 in a dotted line in fig. 1, the inventive concept is not limited thereto. The routing circuit 114 may be connected to respective ones of the plurality of first pads 112 and the plurality of second pads 113.
The substrate 111 may be a silicon substrate. In some embodiments, the substrate 111 may be a printed circuit board. For example, the substrate 111 may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a photosensitive insulating material.
In some embodiments, the substrate 111 may include a prepreg (prepreg), ABF (ajinomoto build-up film), FR-4, or Bismaleimide Triazine (BT) resin.
The external terminals 115 are disposed on the plurality of second pads 113 located on the second surface 110B of the interposer 110. The external terminal 115 may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and/or an alloy thereof.
The first semiconductor chip 120 may have an active surface facing the first surface 110A of the interposer 110 and an inactive surface opposite to the active surface. The first semiconductor chip 120 includes a first connection electrode (or connection pad) 120P disposed on an active surface thereof. The connection terminals 116 are disposed between the first connection electrodes 120P and the first pads 112 of the interposer 110, respectively. The first semiconductor chip 120 may be a flip chip bonded on the first surface 110A of the interposer 110 through the connection terminals 116. The first semiconductor chip 120 may include a logic chip such as a controller or a microprocessor.
The various pads (or "pads") of the devices described herein may be conductive terminals connected to internal wiring of the devices and may transmit signals and/or supply voltages between the internal wiring and/or internal circuitry of the devices and an external power supply. For example, a chip pad (or "chip pad") of a semiconductor chip may be electrically connected to an integrated circuit of the semiconductor chip and a device to which the semiconductor chip is connected, and a power supply voltage and/or a signal is transmitted between the integrated circuit of the semiconductor chip and the device. The various pads may be disposed on or near the outer surface of the device and may generally have a planar area (typically greater than the corresponding surface area of the internal wiring to which the various pads are connected) to facilitate connection with another terminal such as a bump, solder ball, and/or external wiring.
Although the second semiconductor chip 130 is illustrated as a single chip in the drawings, the inventive concept is not limited thereto. The second semiconductor chip 130 may include a plurality of semiconductor chips (refer to fig. 8 and 9). The second semiconductor chip 130 may include a memory chip such as a High Band Memory (HBM). In some embodiments, the second semiconductor chip 130 may include DRAM, SRAM, flash memory, PRAM, reRAM, feRAM, or MRAM.
The second semiconductor chip 130 may have an active surface on which the second connection electrode 130P is located and an inactive surface opposite to the active surface. The second semiconductor chip 130 may be a flip chip bonded to the interposer 110 such that the second connection electrode 130P is connected to the first pad 112 of the interposer 110 through the connection terminal 116. According to an example embodiment, a first group of first pads 112 among the plurality of first pads 112 is connected to the first connection electrode 120P of the first semiconductor chip 120, and a second group of first pads 112 among the plurality of first pads 112 is connected to the second connection electrode 130P of the second semiconductor chip 130. According to an example embodiment, a first group of first pads 112 among the plurality of first pads 112 is not connected to the second connection electrode 130P of the second semiconductor chip 130, and a second group of first pads 112 among the plurality of first pads 112 is not connected to the first connection electrode 120P of the first semiconductor chip 120.
The second semiconductor chip 130 may be laterally spaced apart from the first semiconductor chip 120. According to the exemplary embodiment, the upper surface 120T of the first semiconductor chip 120 and the upper surface 130T of the second semiconductor chip 130 are at the same level in the direction perpendicular to the first surface 110A of the interposer 110, and the lowermost surface of the first semiconductor chip 120 and the lowermost surface of the second semiconductor chip 130 are at the same level in the direction perpendicular to the first surface 110A of the interposer 110. However, the present disclosure is not limited thereto. For example, in an alternative embodiment, the upper surface 120T of the first semiconductor chip 120 may be located at a level higher than the level of the upper surface 130T of the second semiconductor chip 130 in a direction perpendicular to the first surface 110A of the interposer 110 (see, e.g., fig. 12). The space S between the first semiconductor chip 120 and the second semiconductor chip 130 may be a region where warpage of the semiconductor package 100 occurs due to a difference in Coefficient of Thermal Expansion (CTE) between other elements of the semiconductor package 100, such as the encapsulant 160 and the interposer 110. For example, when the encapsulant 160 comprises an organic material having a relatively high CTE (such as an epoxy molding compound) and the substrate 111 of the interposer 110 comprises silicon, the difference in CTE between the encapsulant 160 and the substrate 111 of the interposer 110 may increase warpage. According to an example embodiment, the encapsulant 160 may be a monolayer and may include a homogeneous molding compound.
The reinforcement member 150 is disposed on the first semiconductor chip 120 and the second semiconductor chip 130, and connects the first semiconductor chip 120 and the second semiconductor chip 130. The reinforcement member 150 covers a space S between the first semiconductor chip 120 and the second semiconductor chip 130, which may be a bending region. The reinforcement member 150 may be adhered to the upper surface 120T of the first semiconductor chip 120 and the upper surface 130T of the second semiconductor chip 130 using the adhesive layer 161. The adhesive layer 161 may include a non-conductive film (NCF), an Anisotropic Conductive Film (ACF), an Ultraviolet (UV) sensitive film, a transient adhesive, a thermosetting adhesive, a laser curable adhesive, an ultrasonic curable adhesive, and/or a non-conductive paste (NCP).
The encapsulant 160 may cover the first and second semiconductor chips 120 and 130, for example, the encapsulant 160 may cover a portion and sidewalls of upper surfaces of the first and second semiconductor chips 120 and 130. The encapsulant 160 may cover the sidewalls of the reinforcement member 150. The encapsulant 160 may have a planar upper surface 100T that is substantially flush with the upper surface 150T of the reinforcement member 150. The planar upper surface 100T of the encapsulant 160 may be formed by polishing the encapsulant 160 to expose the reinforcement member 150.
The reinforcement 150 may have a plate shape. The reinforcement member 150 may have a thickness t in a direction perpendicular to the first surface 110A of the insert 110 sufficient to prevent or inhibit the occurrence of warpage. However, the thickness T of the semiconductor package 100 in the direction perpendicular to the first surface 110A of the interposer 110 may be limited to not more than a certain thickness. The thickness T of the stiffener 150 may be less than 20% of the thickness T of the semiconductor package 100. For example, the thickness t of the reinforcement member 150 may be less than 500 μm. According to an example embodiment, the thickness t1 of the first semiconductor chip 120 may be the same as the thickness t2 of the second semiconductor chip 130 in a direction perpendicular to the first surface 110A of the interposer 110, but the disclosure is not limited thereto. In an alternative embodiment, the first semiconductor chip 120 and the second semiconductor chip 130 may have different thicknesses in a direction perpendicular to the first surface 110A of the interposer 110. According to an example embodiment, the thickness t of the reinforcement member 150 may be smaller than the thickness t1 of the first semiconductor chip 120, and the thickness t of the reinforcement member 150 may be smaller than the thickness t2 of the second semiconductor chip 130.
The reinforcement member 150 may include a material having a hardness (e.g., young's modulus) greater than that of the encapsulant 160.
According to example embodiments, the reinforcement member 150 may be rectangular, and side surfaces of the rectangular reinforcement member 150 parallel to side surfaces of the semiconductor package 100 or side surfaces of the first and second semiconductor chips 120 and 130 may have corresponding lengths smaller than lengths of the upper or lower surfaces 150T and 150L of the reinforcement member 150 in a direction parallel to the first surface 110A of the interposer 110 in a direction perpendicular to the first surface 110A of the interposer 110. According to example embodiments, the upper surface 150T of the reinforcement member 150 may have the same length in a direction parallel to the first surface 110A of the insert 110 as the length of the lower surface 150L of the reinforcement member in a direction parallel to the first surface 110A of the insert 110. According to an example embodiment, the thickness t of the reinforcement member 150 may be greater than the thickness of the adhesive layer 161 in a direction perpendicular to the first surface 110A of the insert 110. According to an example embodiment, the lower surface 150L of the stiffener 150 faces the inactive surfaces of the first semiconductor chip 120 and the second semiconductor chip 130 (e.g., faces the upper surface 120T of the first semiconductor chip 120 and the upper surface 130T of the second semiconductor chip 130, respectively), and the upper surface 150T of the stiffener 150 faces away from the inactive surfaces of the first semiconductor chip 120 and the second semiconductor chip 130.
In some embodiments, the reinforcement member 150 may comprise the same material composition as the base 111 of the insert 110. The material composition of stiffener 150 allows for adequate control of stresses caused by CTE mismatch of the various materials in semiconductor package 100; providing a semiconductor package 100 with less warpage and thus improving coplanarity (compliance with industry specifications) of the surface (e.g., PCB board) to which it is ultimately bonded. Furthermore, the material composition of the reinforcement member 150 allows for lighter packaging, which is beneficial for application products where weight is a factor. In this exemplary embodiment, CTE mismatch between the upper and lower portions of the semiconductor package 100 may be prevented or minimized, thus reducing or preventing warpage. According to an example embodiment, stiffener 150 may not include logic and/or may not include transistors. The reinforcement member 150 and the base 111 of the insert 110 may comprise, for example, silicon. According to an exemplary embodiment, the reinforcement may be entirely formed of a crystalline semiconductor material, but the present disclosure is not limited thereto. According to example embodiments, the reinforcement member 150 may extend from a portion of the upper surface 120T of the first semiconductor chip 120 to an adjacent portion of the upper surface 130T of the second semiconductor chip 130, and may be disposed at an edge region of the semiconductor package 100. Accordingly, warpage in an edge region of the semiconductor package 100 (e.g., an edge region of the interposer 110) may be reduced. According to an example embodiment, the stiffener 150 may include a redistribution line therein as a wiring structure to connect the first and second semiconductor chips 120 and 130.
Referring to fig. 2, the area (or size) of the first semiconductor chip 120 may be larger than the area (or size) of the second semiconductor chip 130. The reinforcement member 150 has a first width W1 in a first direction (e.g., a vertical direction) and a second width W2 in a second direction (e.g., a horizontal direction) perpendicular to the first direction. The reinforcement member 150 may be disposed on the upper surface 120T and the upper surface 130T of adjacent portions of the first and second semiconductor chips 120 and 130. According to example embodiments, less than 50% (e.g., in the range of 20% -40%) of the surface area of the upper surface 120T of the first semiconductor chip 120 may be covered by the stiffener 150, and more than 50% (e.g., in the range of 60% -100%) of the surface area of the upper surface 130T of the second semiconductor chip 130 may be covered by the stiffener 150. However, the present disclosure is not limited thereto. For example, in an alternative embodiment, the entire surface area of the upper surface 120T of the first semiconductor chip 120 and the entire surface area of the upper surface 130T of the second semiconductor chip 130 may be covered by the stiffener 150 (see, e.g., fig. 12).
Fig. 3A and 3B are schematic views showing the pre-improvement and post-improvement warp phenomena, respectively, to illustrate effects caused by the reinforcing member according to the example embodiment.
Referring to fig. 3A, when the reinforcement members are not provided on the upper surfaces 120T and 130T of the adjacent portions of the first and second semiconductor chips 120 and 130, the space C1 between the first and second semiconductor chips 120 and 130 is shown to be highly warped. However, when the reinforcement is provided so as to cover a considerable portion (for example, a portion greater than 75%) of the space C1, warpage can be greatly reduced in the same space C1.
Meanwhile, since the area (or size) of the second semiconductor chip 130 is smaller than that of the first semiconductor chip 120, the contact area between the interposer 110 and the encapsulant 160 may be larger around the second semiconductor chip 130 than around the first semiconductor chip 120. Accordingly, considerable warpage may be caused in the edge region C2 of the interposer 110 around the second semiconductor chip 130 and the space C1 between the first semiconductor chip 120 and the second semiconductor chip 130.
The warpage in the edge region C2 of the insert 110 may be controlled by the footprint of the reinforcement member 150.
Fig. 4 is a cross-sectional view of a semiconductor package according to an example embodiment. Fig. 5 is a plan view of the semiconductor package of fig. 4. Fig. 4 shows a cross-sectional view taken along line II-II' of fig. 5. Fig. 6 is a schematic view showing a warp phenomenon to show effects caused by the reinforcing member according to the example embodiment.
Referring to fig. 4 and 5, the semiconductor package 100A is similar or identical to the semiconductor package 100 described with reference to fig. 1 and 2, except for the structure of the stiffener 150'.
Referring to fig. 5, since the area (or size) of the second semiconductor chip 130 may be smaller than the area (or size) of the first semiconductor chip 120, the contact area of the interposer 110 and the encapsulant 160 is greater around the second semiconductor chip 130 than around the first semiconductor chip 120. Accordingly, the interposer 110 may warp at an edge region (refer to, for example, C2 of fig. 6) around the second semiconductor chip 130.
According to an exemplary embodiment, the reinforcement member 150' may extend onto an upper surface of a peripheral portion of the second semiconductor chip 130 adjacent to the edge region of the interposer 110. For example, a first width W1' of the reinforcement member 150' in a first direction (i.e., a vertical direction) and a second width W2' in a second direction (i.e., a horizontal direction) perpendicular to the first direction may be increased to be larger than the first width W1 and the second width W2 of the reinforcement member 150 of the above-described example embodiment shown in fig. 1 and 2 to further cover a peripheral portion of the second semiconductor chip 130 adjacent to the edge region of the interposer 110.
As a result, as shown in fig. 6, warpage in the edge region C2 of the insert 110 can be reduced. In some embodiments, in order to improve warpage in the edge region C2 of the interposer 110, the reinforcement member 150' may cover almost the entire upper surface 130T of the second semiconductor chip 130. In other embodiments, the stiffener 150D (see fig. 12) may extend onto the upper surface 120T of the peripheral portion of the first semiconductor chip 120 further away from the second semiconductor chip 130.
Fig. 7 is a cross-sectional view of a module including the semiconductor package of fig. 4.
Referring to fig. 7, the semiconductor package module 200A includes the semiconductor package 100A shown in fig. 4 and a package substrate 210 on which the semiconductor package 100A is mounted. The semiconductor package module 200A may be a complete semiconductor package (i.e., a semiconductor package in its final form after the semiconductor package fabrication process is completed). The semiconductor package 100A may be a component of the semiconductor package module 200A.
The package substrate 210 includes an upper pad (or "upper pad") 212, a lower pad (or "lower pad") 213, and an insulating member 211, the insulating member 211 including a redistribution layer connecting the upper pad 212 and the lower pad 213. The upper pad 212 may be connected to the second pad 113 of the interposer 110 through the external terminal 115. Similar to the redistribution layer 314 of the package substrate 310 (see fig. 13), the redistribution layer includes at least one routing circuit formed of vias and conductive patterns.
The upper pad 212 may be formed corresponding to the size and arrangement of the second pad 113 of the insert 110. The under-pad 213 may be formed based on input/output (I/O) terminals of a circuit such as a motherboard circuit to expand the size and space of the under-pad 213. Such a circuit may be implemented by a redistribution layer of the package substrate 210. External connection terminals 215, such as solder bumps, to be connected to external circuits are provided on the lower pads 213, respectively. The external connection terminal 215 may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and/or an alloy thereof.
The semiconductor package module 200A includes a heat spreader 170 located on an upper surface of the semiconductor package 100A (e.g., an upper surface of the stiffener 150'). The heat spreader 170 may have a cap structure and extend onto the sidewalls of the semiconductor package 100A. The heat spreader 170 may be adhered to the semiconductor package 100A using an adhesive member 180. Heat may be transferred from the first semiconductor chip 120 and the second semiconductor chip 130 to the heat sink 170 through the stiffener 150'.
The heat sink 170 may comprise a highly thermally conductive material such as metal or ceramic. For some embodiments, the heat spreader 170 may include a Thermal Interface Material (TIM). Adhesive member 180 can include NCF, ACF, UV sensitive films, instant adhesives, thermosetting adhesives, laser curable adhesives, ultrasonic curable adhesives, and/or NCP.
Fig. 8 is a cross-sectional view of a semiconductor package according to an example embodiment. Fig. 9 is a plan view of the semiconductor package of fig. 8. Fig. 8 shows a cross-sectional view taken along line III-III' of fig. 9.
Referring to fig. 8 and 9, the semiconductor package 100B is similar to or identical to the semiconductor package 100 described with reference to fig. 1 and 2 except that a stepped portion G is formed in the first semiconductor chip 120', a plurality of second semiconductor chips 130A, 130B, 130C, and 130D are provided, two reinforcements 150A and 150B are provided, and a thickness Ta of the first semiconductor chip 120' and a thickness Tb of the second semiconductor chips 130A, 130B, 130C, and 130D are different from each other (ta+.tb).
The semiconductor package 100B includes a first semiconductor chip 120 'such as an Application Specific Integrated Circuit (ASIC) and four second semiconductor chips 130A to 130D such as HBMs surrounding the first semiconductor chip 120'. Referring to fig. 9, each two of the four second semiconductor chips 130A to 130D are arranged at each of two opposite sides of the first semiconductor chip 120'.
The thickness Ta of the first semiconductor chip 120' may be different from the thickness Tb of the second semiconductor chips 130A to 130D. Referring to fig. 8, the thickness Ta of the first semiconductor chip 120' may be greater than the thickness Tb of the second semiconductor chips 130A to 130D. The first semiconductor chip 120' includes a stepped portion G lower than the upper surface of the first semiconductor chip 120' in a region adjacent to the second semiconductor chips 130A to 130D, so that the upper surfaces of the reinforcement members 150A and 150B located on the stepped portion G may be flush with the upper surface of the first semiconductor chip 120 '. A surface (e.g., a concave surface) of the first semiconductor chip 120 'provided by the stepped portion G of the first semiconductor chip 120' may be substantially flush with the upper surfaces of the second semiconductor chips 130A to 130D.
Referring to fig. 9, stepped portions G of the first semiconductor chip 120 'are formed in opposite peripheral portions of the first semiconductor chip 120', respectively. Each of the step portions G may correspond to each two of the second semiconductor chips 130A to 130D.
The reinforcement members 150A and 150B may include a first reinforcement member 150A and a second reinforcement member 150B. The first reinforcement 150A and the second reinforcement 150B may be disposed on the stepped portion G and on the upper surfaces of the second semiconductor chips 130A to 130D, and cover the spaces S1 and S2 between the first semiconductor chip 120' and the second semiconductor chips 130A to 130D. According to an exemplary embodiment, a length of a portion of the first reinforcement member 150A covering the step portion G of the first semiconductor chip 120' adjacent to the second semiconductor chips 130A and 130D in a direction parallel to the upper surface of the interposer 110 may be smaller than a length of a portion of the first reinforcement member 150A covering the upper surfaces of the second semiconductor chips 130A and 130D in a direction parallel to the upper surface of the interposer 110. According to an exemplary embodiment, a length of a portion of the second reinforcement member 150B covering the step portion G of the first semiconductor chip 120' adjacent to the second semiconductor chips 130B and 130C in a direction parallel to the upper surface of the interposer 110 may be smaller than a length of a portion of the second reinforcement member 150B covering the upper surfaces of the second semiconductor chips 130B and 130C in a direction parallel to the upper surface of the interposer 110.
The stepped portion G in the first semiconductor chip 120' may prevent the thickness of the semiconductor package 100B from increasing due to the thickness t of the first reinforcement member 150A and the second reinforcement member 150B. In some embodiments, the stepped portion G may be formed to have a depth d in a direction perpendicular to the upper surface of the insert 110 that is greater than the thickness t of the first and second reinforcement members 150A and 150B in the direction perpendicular to the upper surface of the insert 110, and thus, the first and second reinforcement members 150A and 150B are disposed in the semiconductor package 100B without increasing the thickness of the semiconductor package 100B.
Fig. 10 is a cross-sectional view of a module including the semiconductor package of fig. 8.
Referring to fig. 10, the semiconductor package module 200B is similar to or identical to the semiconductor package module 200A described with reference to fig. 7, except that the semiconductor package 100B shown in fig. 8 is disposed in the semiconductor package module 200B.
The semiconductor package module 200B includes a package substrate 210 and the semiconductor package 100B shown in fig. 8. The package substrate 210 includes an upper pad 212, a lower pad 213, and an insulating member 211, the insulating member 211 including a redistribution layer connecting the upper pad 212 and the lower pad 213. The upper pad 212 may be connected to the second pad 113 of the interposer 110 through the external terminal 115.
The semiconductor package module 200B includes a heat spreader 170 on the upper surface and sidewalls of the semiconductor package 100B. Since the upper surfaces of the first reinforcement member 150A and the second reinforcement member 150B and the upper surface of the first semiconductor chip 120' are substantially flush with each other, heat generated from the first semiconductor chip 120' and the second semiconductor chips 130A to 130D can be transferred to the heat sink 170 adjacent thereto through the upper surfaces of the first semiconductor chip 120' and the first reinforcement member 150A and the second reinforcement member 150B.
Fig. 11 is a cross-sectional view of a semiconductor package according to an example embodiment.
Referring to fig. 11, the semiconductor package 100C is similar or identical to the semiconductor package 100A described with reference to fig. 4 and 5, except that the first semiconductor chip 120 "and the second semiconductor chip 130 have different thicknesses, the first semiconductor chip 120" includes a stepped portion G therein, and the reinforcement member 150C includes a redistribution layer 155.
The thickness of the first semiconductor chip 120″ in the direction perpendicular to the upper surface of the interposer 110 may be greater than the thickness of the second semiconductor chip 130 in the direction perpendicular to the upper surface of the interposer 110. A step portion G lower than the upper surface of the first semiconductor chip 120″ may be formed in a portion of the first semiconductor chip 120″ adjacent to the second semiconductor chip 130. The surface (e.g., a recessed surface) provided by the stepped portion G of the first semiconductor chip 120″ may be substantially flush with the upper surface 130T of the second semiconductor chip 130. Accordingly, the reinforcement member 150C located on the stepped portion G of the first semiconductor chip 120″ and on the second semiconductor chip 130 may be located at a flat level.
The reinforcement 150C may be a redistribution structure including a redistribution layer (RDL) 155 instead of a dummy chip. The reinforcement 150C may have a plurality of connection pads (or "connection pads") 150P on a lower surface (or mounting surface) thereof that are connected to the redistribution layer 155. The redistribution layer 155 may be formed of a via and a conductive pattern. The redistribution layer 155 may be formed from one or more layers.
The first semiconductor chip 120″ includes a first lower electrode 120P1 on a lower surface thereof and a first upper electrode 120P2 on a portion (e.g., a concave surface) of an upper surface thereof. The first lower electrode 120P1 may be connected to the first pad 112 of the interposer 110 through the first connection terminal 116. The first upper electrode 120P2 may be disposed on the stepped portion G to be connected to the connection pad 150P of the reinforcement member 150C through the second connection terminal 156. The first upper electrode 120P2 may be located below the reinforcement member 150C.
The reinforcement member 150C may be fixed to the first semiconductor chip 120″ and the second semiconductor chip 130 using the second connection terminal 156 without using an adhesive. According to example embodiments, an underfill resin may be disposed between the reinforcement member 150C and the first and second semiconductor chips 120″ and 130. In some embodiments, the encapsulant 160 may cover at least a portion of the lower surface and sidewalls of the first semiconductor chip 120", at least a portion of the lower surface of the second semiconductor chip 130, at least a portion of the upper surface and sidewalls of the second semiconductor chip 130, and at least a portion of the lower surface and sidewalls of the stiffener 150C.
The second semiconductor chip 130 includes a second lower electrode 130P1 on a lower surface thereof and a second upper electrode 130P2 on an upper surface thereof. The second lower electrode 130P1 may be connected to the first pad 112 of the interposer 110 through the first connection terminal 116. The second upper electrode 130P2 may be connected to the connection pad 150P of the reinforcement member 150C through the second connection terminal 156.
Since the redistribution layer 155 of the stiffener 150C is used to connect at least some electrodes of the first semiconductor chip 120″ and the second semiconductor chip 130, the wiring circuit 114 of the interposer 110 may be simplified. In some embodiments, the routing circuitry 114 of the interposer 110 may be simplified, thus reducing the number of layers of the routing circuitry 114. Therefore, the thickness of the semiconductor package 100C can be reduced.
Fig. 12 is a cross-sectional view of a semiconductor package according to an example embodiment.
Referring to fig. 12, the semiconductor package 100D is similar or identical to the semiconductor package 100 described with reference to fig. 1 and 2, except that the thickness Ta of the first semiconductor chip 120 is different from the thickness Tb of the second semiconductor chip 130 (ta+.tb) and the thickness of the reinforcement member 150D is different according to portions thereof.
The thickness Ta of the first semiconductor chip 120 in the direction perpendicular to the upper surface of the interposer 110 may be greater than the thickness Tb of the second semiconductor chip 130 in the direction perpendicular to the upper surface of the interposer 110. In this exemplary embodiment, unlike the foregoing exemplary embodiment of fig. 8 and 11, the structure of the reinforcement member 150D may be modified without forming a stepped portion in the first semiconductor chip 120.
The reinforcement member 150D has a flat upper surface, and includes a first portion 150Da having a first thickness ta in a direction perpendicular to the upper surface of the insert 110, and a second portion 150Db having a second thickness tb greater than the first thickness ta in a direction perpendicular to the upper surface of the insert 110. The thinner first portion 150Da of the reinforcement member 150 may be disposed on the upper surface 120T of the first semiconductor chip 120. The thicker second portion 150Db of the stiffener 150 may be disposed on the upper surface 130T of the second semiconductor chip 130. The difference (Tb-Ta) between the first thickness Ta and the second thickness Tb of the reinforcement member 150D may be set to correspond to (e.g., be substantially equal to or less than) the difference (Ta-Tb) between the thickness Ta of the first semiconductor chip 120 and the thickness Tb of the second semiconductor chip 130.
The reinforcement member 150D may have a substantially flat upper surface that is flush with the upper surface of the encapsulant 160. In the cross-sectional view, the reinforcement member 150D may cover substantially the entire upper surface 120T of the first semiconductor chip 120 and the entire upper surface 130T of the second semiconductor chip 130. The reinforcement member 150D may cover a space between the first semiconductor chip 120 and the second semiconductor chip 130 and extend onto upper surfaces 120T and 130T of peripheral portions of the first semiconductor chip 120 and the second semiconductor chip 130 adjacent to edge regions of the interposer 110.
Fig. 13 is a cross-sectional view of a semiconductor package according to an example embodiment.
Referring to fig. 13, the semiconductor package 100E is similar or identical to the semiconductor package 100 described with reference to fig. 1 and 2, except that the thickness of the first semiconductor chip 120 is different from the thickness of the second semiconductor chip 130, the step portion G is formed in the first semiconductor chip 120, and a package substrate 310 is provided instead of an interposer.
In the case where the thickness of the first semiconductor chip 120 is different from the thickness of the second semiconductor chip 130, the stepped portion G is formed in the first semiconductor chip 120 such that the reinforcement member 150 is provided on the stepped portion G similarly to the reinforcement member 150A or 150B shown in fig. 8.
According to an example embodiment, the first semiconductor chip 120 and the second semiconductor chip 130 are connected to the package substrate 310 instead of the interposer. The first semiconductor chip 120 and the second semiconductor chip 130 are mounted on the package substrate 310.
The package substrate 310 includes an insulating member 311 having opposite first and second surfaces 310A and 310B, a plurality of first pads (or "first pads") 312 and a plurality of second pads (or "second pads") 313 respectively located on the first and second surfaces 310A and 310B of the insulating member 311, and a redistribution layer 314 in the insulating member 311 connecting the first and second pads 312 and 313. The insulating member 311 may be a Printed Circuit Board (PCB). For example, the insulating member 311 may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a photosensitive insulating material.
In some embodiments, the insulating member 311 may include a prepreg, ABF (ajinomoto build-up film), FR-4, or Bismaleimide Triazine (BT) resin. The redistribution layer 314 and the first and second pads 312 and 313 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and/or alloys thereof, but are not limited thereto. The external terminals 315 may be respectively disposed on the second pads 313. The external terminal 315 may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and/or an alloy thereof.
While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims (16)

1. A semiconductor package, the semiconductor package comprising:
a first substrate having a first surface and a second surface opposite the first surface, the first substrate comprising a plurality of first pads on the first surface of the first substrate and a plurality of second pads on the second surface of the first substrate;
A first semiconductor chip on the first surface of the first substrate, the first semiconductor chip connected to a first set of first pads of the plurality of first pads;
A second semiconductor chip on the first surface of the first substrate, the second semiconductor chip being connected to a second set of first pads of the plurality of first pads, the first semiconductor chip including a stepped portion adjacent to the second semiconductor chip, and a surface of the stepped portion of the first semiconductor chip being flush with an upper surface of the second semiconductor chip;
A reinforcement member located on the stepped portion of the first semiconductor chip and the upper surface of the second semiconductor chip, the upper surface of the reinforcement member being flush with the upper surface of the first semiconductor chip, and the reinforcement member covering a space between the first semiconductor chip and the second semiconductor chip; and
An encapsulant on the first surface of the first substrate, the encapsulant covering at least sidewalls of each of the first and second semiconductor chips and the stiffener,
Wherein the first semiconductor chip includes a first upper electrode on the surface of the step portion,
The second semiconductor chip includes a second upper electrode on the upper surface of the second semiconductor chip,
The first upper electrode and the second upper electrode are positioned below the reinforcement member, and
The reinforcement includes a redistribution layer connected to the first upper electrode and the second upper electrode.
2. The semiconductor package according to claim 1,
Wherein the second semiconductor chip has a smaller size than the first semiconductor chip, and
Wherein the reinforcement member covers an upper surface of a peripheral portion of the second semiconductor chip adjacent to an edge region of the first substrate.
3. The semiconductor package according to claim 2, wherein the stiffener covers an entire upper surface of the second semiconductor chip.
4. The semiconductor package of claim 1, wherein a thickness of the stiffener in a direction perpendicular to the first surface of the first substrate is less than 20% of a total thickness of the semiconductor package in the direction perpendicular to the first surface of the first substrate.
5. The semiconductor package according to claim 1,
Wherein the first semiconductor chip has a first thickness in a direction perpendicular to the first surface of the first substrate, and
Wherein the second semiconductor chip has a second thickness smaller than the first thickness of the first semiconductor chip in the direction perpendicular to the first surface of the first substrate.
6. The semiconductor package according to claim 1,
Wherein the first semiconductor chip further includes a first lower electrode on a lower surface of the first semiconductor chip,
Wherein the second semiconductor chip further includes a second lower electrode on a lower surface of the second semiconductor chip,
Wherein the first lower electrode and the second lower electrode are connected to corresponding first pads of the plurality of first pads.
7. The semiconductor package of claim 1, wherein the second semiconductor chip comprises a plurality of second semiconductor chips, and
Wherein the plurality of second semiconductor chips are disposed on opposite sides of the first semiconductor chip.
8. The semiconductor package of claim 7, wherein the stiffener comprises a first stiffener and a second stiffener, and
Wherein the first stiffener and the second stiffener are located on the opposite sides of the first semiconductor chip, respectively.
9. The semiconductor package of claim 1, wherein the stiffener has a hardness greater than a hardness of the encapsulant.
10. The semiconductor package of claim 1, wherein the stiffener and the first substrate are formed from the same material composition.
11. The semiconductor package of claim 1, wherein the first semiconductor chip is a logic chip and the second semiconductor chip is a memory chip.
12. The semiconductor package of claim 1, further comprising a heat spreader located on the stiffener.
13. The semiconductor package according to claim 1, further comprising a package substrate including an upper pad, an under pad, and a redistribution layer connecting the upper pad and the under pad,
Wherein the upper pad is connected to the plurality of second pads of the first substrate.
14. A semiconductor package, the semiconductor package comprising:
A first substrate having opposed first and second surfaces, the first substrate comprising a plurality of first pads on the first surface of the first substrate and a plurality of second pads on the second surface of the first substrate;
A first semiconductor chip on the first surface of the first substrate, the first semiconductor chip being connected to first portions of the plurality of first pads and including a stepped portion lower than an upper surface of the first semiconductor chip;
a second semiconductor chip located on the first surface of the first substrate, the second semiconductor chip being connected to second portions of the plurality of first pads and having an upper surface flush with a surface of the step portion of the first semiconductor chip;
A reinforcement member located on the surface of the stepped portion of the first semiconductor chip and the upper surface of the second semiconductor chip, the upper surface of the reinforcement member being flush with the upper surface of the first semiconductor chip, and the reinforcement member covering a space between the first semiconductor chip and the second semiconductor chip and having a flat plate shape; and
An encapsulant on the first surface of the first substrate, the encapsulant covering sidewalls of the first semiconductor chip, sidewalls of the second semiconductor chip, and sidewalls of the stiffener,
Wherein the first semiconductor chip includes a first upper electrode on the surface of the step portion,
The second semiconductor chip includes a second upper electrode on the upper surface of the second semiconductor chip,
The first upper electrode and the second upper electrode are positioned below the reinforcement member, and
The reinforcement includes a redistribution layer connected to the first upper electrode and the second upper electrode.
15. The semiconductor package according to claim 14,
Wherein the first semiconductor chip further includes a first lower electrode on a lower surface of the first semiconductor chip,
Wherein the second semiconductor chip further includes a second lower electrode on a lower surface of the second semiconductor chip,
Wherein the first lower electrode and the second lower electrode are connected to corresponding first pads of the plurality of first pads.
16. A semiconductor package, the semiconductor package comprising:
A package substrate, the package substrate comprising: an insulating member having opposed first and second surfaces; a plurality of first pads located on the first surface of the insulating member; a plurality of second pads located on the second surface of the insulating member; and a redistribution layer in the insulating member and connecting the plurality of first pads and the plurality of second pads;
A first semiconductor chip on the package substrate, the first semiconductor chip being connected to a first group of first pads of the plurality of first pads;
A second semiconductor chip on the package substrate, the second semiconductor chip being connected to a second group of first pads among the plurality of first pads, the first semiconductor chip including a stepped portion adjacent to the second semiconductor chip, and a surface of the stepped portion of the first semiconductor chip being flush with an upper surface of the second semiconductor chip;
A reinforcement member located on the stepped portion of the first semiconductor chip and the upper surface of the second semiconductor chip, the upper surface of the reinforcement member being flush with the upper surface of the first semiconductor chip, and the reinforcement member covering a space between the first semiconductor chip and the second semiconductor chip; and
An encapsulant on the package substrate, the encapsulant covering at least sidewalls of the first semiconductor chip, sidewalls of the second semiconductor chip, and sidewalls of the stiffener,
Wherein the first semiconductor chip includes a first upper electrode on the surface of the step portion,
The second semiconductor chip includes a second upper electrode on the upper surface of the second semiconductor chip,
The first upper electrode and the second upper electrode are positioned below the reinforcement member, and
The reinforcement includes a redistribution layer connected to the first upper electrode and the second upper electrode.
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10629547B1 (en) * 2018-10-30 2020-04-21 Micron Technology, Inc. Redistribution-layer fanout package stiffener
JP7251951B2 (en) * 2018-11-13 2023-04-04 新光電気工業株式会社 Semiconductor device and method for manufacturing semiconductor device
US11088086B2 (en) * 2019-04-26 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
KR102609138B1 (en) * 2019-04-29 2023-12-05 삼성전기주식회사 Printed circuit board assembly
KR102653499B1 (en) * 2019-06-28 2024-03-29 삼성전자주식회사 Semiconductor package
KR20210046913A (en) 2019-10-18 2021-04-29 삼성전자주식회사 System-in-package module
CN114514605A (en) * 2019-11-22 2022-05-17 华为技术有限公司 Chip package, electronic equipment and chip package preparation method
KR20210066387A (en) 2019-11-28 2021-06-07 삼성전자주식회사 Semiconductor package
US11450622B2 (en) * 2021-01-20 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
CN116868331A (en) * 2021-02-24 2023-10-10 华为技术有限公司 Chip packaging structure, manufacturing method thereof and electronic equipment
KR102484357B1 (en) * 2021-02-26 2023-01-04 해성디에스 주식회사 Roll-to-roll panel level package
US11848246B2 (en) * 2021-03-24 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219293A (en) * 2012-01-23 2013-07-24 台湾积体电路制造股份有限公司 Sawing underfill in packaging processes
CN104051377A (en) * 2013-03-14 2014-09-17 通用电气公司 Power Overlay Structure And Method Of Making Same
CN106328605A (en) * 2015-06-30 2017-01-11 三星电子株式会社 Semiconductor package

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5394609A (en) 1993-10-26 1995-03-07 International Business Machines, Corporation Method and apparatus for manufacture of printed circuit cards
US6429530B1 (en) 1998-11-02 2002-08-06 International Business Machines Corporation Miniaturized chip scale ball grid array semiconductor package
TW460927B (en) 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
US7202556B2 (en) 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
DE10164494B9 (en) 2001-12-28 2014-08-21 Epcos Ag Encapsulated low-profile device and method of manufacture
TWI239080B (en) * 2002-12-31 2005-09-01 Advanced Semiconductor Eng Semiconductor chip package and method for the same
KR100541395B1 (en) 2003-09-09 2006-01-11 삼성전자주식회사 Apparatus for stacking semiconductor chips on wafer, method using the apparatus, and semiconductor package manufactured thereby
KR100618892B1 (en) 2005-04-13 2006-09-01 삼성전자주식회사 Semiconductor package accomplishing a fan-out structure through wire bonding
TWI278079B (en) 2005-04-14 2007-04-01 Chipmos Technologies Inc Pillar grid array package
US7319591B2 (en) 2005-05-26 2008-01-15 International Business Machines Corporation Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages
KR20080022452A (en) 2006-09-06 2008-03-11 삼성전자주식회사 Pop package and method of producing the same
US20080128897A1 (en) 2006-12-05 2008-06-05 Tong Wa Chao Heat spreader for a multi-chip package
JP2008166373A (en) 2006-12-27 2008-07-17 Nec Electronics Corp Semiconductor device and its manufacturing method
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US7927919B1 (en) 2009-12-03 2011-04-19 Powertech Technology Inc. Semiconductor packaging method to save interposer
US8304917B2 (en) 2009-12-03 2012-11-06 Powertech Technology Inc. Multi-chip stacked package and its mother chip to save interposer
US8384105B2 (en) * 2010-03-19 2013-02-26 Micron Technology, Inc. Light emitting diodes with enhanced thermal sinking and associated methods of operation
US8963339B2 (en) 2012-10-08 2015-02-24 Qualcomm Incorporated Stacked multi-chip integrated circuit package
US8907472B2 (en) * 2013-02-07 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package comprising perforated foil sheet
US9287194B2 (en) * 2013-03-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods for semiconductor devices
TWI496270B (en) 2013-03-12 2015-08-11 矽品精密工業股份有限公司 Semiconductor package and method of manufacture
US9341671B2 (en) 2013-03-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Testing holders for chip unit and die package
US9111912B2 (en) * 2013-05-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9056763B2 (en) * 2013-09-27 2015-06-16 Intel Corporation Stress buffer layer for integrated microelectromechanical systems (MEMS)
US9496248B2 (en) 2014-01-06 2016-11-15 Fujitsu Limited Interposer for integrated circuit chip package
US20150287697A1 (en) * 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
KR101579673B1 (en) 2014-03-04 2015-12-22 앰코 테크놀로지 코리아 주식회사 Method for fabricating semiconductor package and semiconductor package using the same
US20150262902A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) * 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9165793B1 (en) * 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9524883B2 (en) * 2014-05-13 2016-12-20 Invensas Corporation Holding of interposers and other microelectronic workpieces in position during assembly and other processing
US9589933B2 (en) 2014-06-23 2017-03-07 Micron Technology, Inc. Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
US9252127B1 (en) * 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US9548273B2 (en) * 2014-12-04 2017-01-17 Invensas Corporation Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
KR102065943B1 (en) * 2015-04-17 2020-01-14 삼성전자주식회사 Fan-out semiconductor package and method of manufacturing the same
JP6592977B2 (en) 2015-06-12 2019-10-23 凸版印刷株式会社 Semiconductor package substrate, semiconductor package and manufacturing method thereof
US9673148B2 (en) 2015-11-03 2017-06-06 Dyi-chung Hu System in package
US9865566B1 (en) * 2016-06-15 2018-01-09 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10141253B2 (en) * 2016-11-14 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR20180086804A (en) * 2017-01-23 2018-08-01 앰코 테크놀로지 인코포레이티드 Semiconductor device and manufacturing method thereof
US10573579B2 (en) * 2017-03-08 2020-02-25 Mediatek Inc. Semiconductor package with improved heat dissipation
US10276536B2 (en) * 2017-04-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US20180350708A1 (en) * 2017-06-06 2018-12-06 Powertech Technology Inc. Package structure and manufacturing method thereof
US10283428B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
US10461014B2 (en) * 2017-08-31 2019-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreading device and method
US10930633B2 (en) * 2018-06-29 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer design for package integration
US10672712B2 (en) * 2018-07-30 2020-06-02 Advanced Micro Devices, Inc. Multi-RDL structure packages and methods of fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219293A (en) * 2012-01-23 2013-07-24 台湾积体电路制造股份有限公司 Sawing underfill in packaging processes
CN104051377A (en) * 2013-03-14 2014-09-17 通用电气公司 Power Overlay Structure And Method Of Making Same
CN106328605A (en) * 2015-06-30 2017-01-11 三星电子株式会社 Semiconductor package

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