CN109904276A - A kind of GaN base Vertical collection opto chip and preparation method thereof - Google Patents

A kind of GaN base Vertical collection opto chip and preparation method thereof Download PDF

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CN109904276A
CN109904276A CN201910097597.9A CN201910097597A CN109904276A CN 109904276 A CN109904276 A CN 109904276A CN 201910097597 A CN201910097597 A CN 201910097597A CN 109904276 A CN109904276 A CN 109904276A
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multiple quantum
quantum wells
substrate
base vertical
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CN109904276B (en
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黎大兵
程东碧
孙晓娟
贾玉萍
石芝铭
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Abstract

The present invention relates to a kind of GaN base Vertical collection opto chip and preparation method thereof, solving existing GaN integrated opto-electronic integration density not can be further improved, performance cannot be optimal the technical issues of identical with horizontal structure structure.GaN base Vertical collection opto chip of the invention is able to achieve the optical communication between LED and PD, grown epitaxial layer is distinguished on two pieces of sapphires, and the structure of designed detector and light emitting diode is grown on epitaxial layer, then sapphire is thinned, there is no the one side of growth of device to be bonded together by Bonding two pieces of sapphires, it can be used for vertical direction and establish optical communication, further increase the integration density of GaN base material optic communication.This structure is by individually designing detector PD and Light-emitting diode LED, it can be achieved that the information between vertical structure device is transmitted.Present invention process is simple, low in cost, has broad application prospects.

Description

A kind of GaN base Vertical collection opto chip and preparation method thereof
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of GaN base Vertical collection opto chip and its preparation Method.
Background technique
Integrated opto-electronic is in fields such as information communication, multimedia, personal consumption, measurement sensing, bio-sensing and military affairs With important application prospects, compared to Si base integrated opto-electronic device, GaN base integrated opto-electronic has significant advantage, mainly In terms of being embodied in following two: (1) Si is indirect bandgap material, and Si base light source problem is to restrict Si base optical electronic The prominent question of development and application;(2) traditional Si material has very strong absorbability, SiO to visible light2Refractive Index of Material compared with Small, light field limitation capability is poor, and GaN material does not absorb visible light, while having biggish refractive index.Theoretically, GaN base Material is the excellent material for preparing visible light waveguide and Planar integration photonic device.
Currently, from the point of view of the development of GaN base integrated opto-electronic, in horizontal structure mainly by light emitting diode Led, modulation The active devices such as device, detector PD are integrated on same substrate, and are connected with passive devices such as optical waveguide, isolator, couplers It picks up to constitute micro photo electric system.At home, horizontal structure visible light communication InGaN/GaN multiple quantum wells diode is realized It shines and detects, information rate can be transmitted and reach 20MHZ.However there are two the integrated opto-electronic disadvantages of this horizontal structure, the Any is that the integration density of this planar structure not can be further improved, and second point, which is that this horizontal GaN structure is integrated, requires water The identical detector PD of flat structure and Light-emitting diode LED cannot make the performance of the two be optimal in this way, influence Integrated Light The transmission performance of electronic communication.
Summary of the invention
The invention solves GaN integrated opto-electronic integration densities in the prior art not can be further improved and horizontal structure knot The technical issues of structure is identical, and performance cannot be optimal provides a kind of GaN base Vertical collection opto chip and its preparation side Method.
In order to solve the above-mentioned technical problem, technical solution of the present invention is specific as follows:
A kind of GaN base Vertical collection opto chip, including multiple quantum wells diode (LED) part and multiple quantum wells detector The part PD;
Multiple quantum wells diode (LED) part includes: substrate and multiple quantum wells LED structure;
The multiple quantum wells LED structure includes successively growing GaN epitaxial layer on substrate, n-GaN layers, In GaN/GaN Layer and p-GaN layer;
The part multiple quantum wells detector PD includes: substrate and multiple quantum wells PD structure;
The multiple quantum wells PD structure includes successively growing GaN epitaxial layer on substrate, n-GaN layers, InG aN/GaN Layer and p-GaN layer;
The one side of the non-growth of device of substrate of multiple quantum wells diode (LED) part and the multiple quantum wells detector PD The non-growth of device of partial substrate is bonded together on one side;
The multiple quantum wells LED structure and the multiple quantum wells PD structure are coated with metal electrode respectively, and are packaged with lead.
In the above-mentioned technical solutions, the n-GaN is that Si is adulterated in GaN material, and p-GaN is adulterated in GaN material Mg.
In the above-mentioned technical solutions, the substrate is sapphire.
In the above-mentioned technical solutions, the metal electrode is Ni, Au, Pt, Ni/Au, Ti/Al or Ti/Al/Ti/Au.
A kind of preparation method of GaN base Vertical collection opto chip, comprising the following steps:
Step 1: growing GaN epitaxial layer on substrate;
Step 2: growing n-GaN layers in GaN epitaxial layer;
Step 3: growing InGaN/GaN layers on n-GaN layer;
Step 4: carrying out photoetching, etching after the InGaN/GaN layer spin coating photoresist of step 3;
Step 5: growing p-GaN layer on InGaN/GaN layers, the preparation of multiple quantum wells LED structure is completed;
Step 6: repeating step 1 to five, multiple quantum wells PD structure is obtained;
It is thinned Step 7: the one side of the non-growth of device of above-mentioned two substrate is polished, is then bonded together;
Step 8: distinguishing evaporation metal electrode in the multiple quantum wells LED structure and the multiple quantum wells PD structure, then Lead packages complete the preparation of GaN base Vertical collection opto chip.
In the above-mentioned technical solutions, using MOCVD technology growth GaN epitaxial layer, n-GaN layers, InGaN/GaN layers or p- GaN layer.
In the above-mentioned technical solutions, photoresist described in step 4 is negative photoresist or the eurymeric with reverse speed characterisstic Photoresist.
In the above-mentioned technical solutions, when metal electrode is Ni/Au combination electrode, annealing conditions temperature is taken the photograph for 400-600 Family name's degree, time are 3-15 minutes.
In the above-mentioned technical solutions, when metal electrode is Ti/Al combination electrode, annealing temperature is 500-700 degrees Celsius, Time -5 minutes 30 seconds.
The beneficial effects of the present invention are:
GaN base Vertical collection opto chip of the invention is able to achieve the optical communication between LED and PD, in two pieces of sapphires Upper grown epitaxial layer respectively, and the structure of designed detector and light emitting diode is grown on epitaxial layer, it then will be blue precious Stone is thinned, and does not have the one side of growth of device to be bonded together by Bonding two pieces of sapphires, can be used for vertical direction and build Vertical optical communication, further increases the integration density of GaN base material optic communication.And this structure passes through individually design detection Device PD and Light-emitting diode LED distinguish grown epitaxial layer in two pieces of sapphires, and grow designed detector on epitaxial layer And the structure of light emitting diode is, it can be achieved that the information between vertical structure device is transmitted, and can solve horizontal structure because of phase Same PD and LED structure prevents the problem of optic communication performance is from being optimal.
GaN base Vertical collection opto chip of the invention further increases the integrated density of photonic device, reduces device The difficulty and cost of preparation realize that device miniaturization is integrated.
The preparation method of GaN base Vertical collection opto chip of the invention, simple process and low cost have wide Application prospect.
Detailed description of the invention
Invention is further described in detail with reference to the accompanying drawings and detailed description.
Fig. 1 is the structural schematic diagram of GaN base Vertical collection opto chip of the invention.
Fig. 2 is the preparation flow figure of GaN base Vertical collection opto chip of the invention.
Specific embodiment
The present invention provides a kind of GaN base Vertical collection opto chip, including multiple quantum wells diode (LED) part and volume The part sub- well detector PD;Multiple quantum wells diode (LED) part includes: substrate and multiple quantum wells LED structure;The volume Sub- trap LED structure includes GaN epitaxial layer, n-GaN layers, InGaN/GaN layers and the p-GaN layer successively grown on substrate;It is described The part multiple quantum wells detector PD includes: substrate and multiple quantum wells PD structure;The multiple quantum wells PD structure includes successively growing GaN epitaxial layer, n-GaN layers, InGaN/GaN layers and p-GaN layer on substrate;Multiple quantum wells diode (LED) part The non-growth of device of substrate and the part multiple quantum wells detector PD the non-growth of device of substrate while be bonded in one It rises;The multiple quantum wells LED structure and the multiple quantum wells PD structure are coated with metal electrode respectively, and are packaged with lead.It is preferred that The n-GaN is that Si is adulterated in GaN material, and p-GaN is that Mg is doped in GaN material;The substrate is sapphire;It is described Metal electrode is Ni, Au, Pt, Ni/Au, Ti/Al or Ti/Al/Ti/Au.
The present invention also provides a kind of preparation methods of GaN base Vertical collection opto chip, comprising the following steps:
Step 1: growing GaN epitaxial layer on substrate;
Step 2: growing n-GaN layers in GaN epitaxial layer;
Step 3: growing InGaN/GaN layers on n-GaN layer;
Step 4: carrying out photoetching, etching after the InGaN/GaN layer spin coating photoresist of step 3;
Step 5: growing p-GaN layer on InGaN/GaN layers, the preparation of multiple quantum wells LED structure is completed;
Step 6: repeating step 1 to five, multiple quantum wells PD structure is obtained;
It is thinned Step 7: the one side of the non-growth of device of above-mentioned two substrate is polished, is then bonded together;
Step 8: distinguishing evaporation metal electrode in the multiple quantum wells LED structure and the multiple quantum wells PD structure, then Lead packages complete the preparation of GaN base Vertical collection opto chip.
Photoresist described in preferred steps four is negative photoresist or the positive photo glue with reverse speed characterisstic.
Preferably, substrate needed for growth GaN material is the typical substrates such as sapphire, silicon, silicon carbide, and growing method is gold Belong to Organic Vapor Deposition method (MOCVD), the especially method of high temperature MOCVD.
Preferably, photoresist used in photoetching is negative photoresist or the positive photo glue with reverse speed characterisstic.
Preferably, the method for preparing electrode is electron beam evaporation or thermal evaporation, the type of electrode material is Ni, Au, Pt, Ni/Au, Ti/Al or Ti/Al/Ti/Au etc., can be formed with GaN Schottky or ohm-type half same metal contacted or The different types of metal of person.
Preferably, the condition annealed when preparing electrode is depending on metal species, when metal electrode is Ni/Au compound electric Pole, annealing conditions temperature are 400-600 degrees Celsius, and the time is 3-15 minutes;When metal electrode be Ti/Al combination electrode, Annealing temperature is 500-700 degrees Celsius, the time -5 minutes 30 seconds.
Preferably, the condition of Sapphire Substrate polishing thickness is depending on design requirement.
Present embodiment is described with reference to the drawings, Fig. 2 is the preparation flow of GaN base Vertical collection opto chip of the invention Figure, comprising:
(1) Sapphire Substrate (number 1) is cleaned, with being dried with nitrogen.
(2) GaN epitaxial layer is grown on a sapphire substrate before this using MOCVD method, then grow in GaN epitaxial layer N-GaN layers, then InGaN/GaN layers (alternatively referred to as MQWs layers) is grown on n-GaN layer, and by adjusting the In in InGaN Component ratio improves the emission wavelength of multiple quantum wells LED.
(3) photoresist is coated on InGaN/GaN layers and carries out photoetching development, will use covering of having customized in exposure process Graphics field on mask plate is completely disposed above chip, sets the time for exposure of 7s, by exposure technique, will set by film version The pattern transfer on mask plate counted is to photoresist layer.Device after exposure develops, and comes out graphical display. Development mainly uses 3038 developer solutions, is cleaned and is dried with nitrogen with clear water after development, then dry steam on hot plate, so far Complete photoetching development step.It also needs to carry out structure of the ICP nitride etch to form device after photoetching development, be dried in cleaning It is dry.Then p-GaN layer is grown on the InGaN/GaN layer after photoetching, etching, completes the preparation of multiple quantum wells LED structure;
(4) since Sapphire Substrate (number 1) is too thick, it would be desirable to substrate polishing be thinned to reduce the propagation road of light Diameter.
(5) Sapphire Substrate (number 2) is cleaned, with being dried with nitrogen.
(6) GaN epitaxial layer is grown on a sapphire substrate before this using MOCVD method, then grow in GaN epitaxial layer N-GaN layers, then InGaN/GaN layers are grown on n-GaN layer.
(7) photoresist is coated on InGaN/GaN layers and carries out photoetching development, will use covering of having customized in exposure process Graphics field on mask plate is completely disposed above chip, sets the time for exposure of 7s, by exposure technique, will set by film version The waveguiding structure counted on mask plate is transferred to photoresist layer.Chip after exposure develops, and goes out graphical display Come.Development mainly uses 3038 developer solutions, is cleaned and is dried with nitrogen with clear water after development, then dries steam on hot plate, So far photoetching development step is completed.It also needs to carry out structure of the ICP nitride etch to form device after photoetching development, clean Drying.Then p-GaN layer is grown on the InGaN/GaN layer after photoetching, etching, completes the preparation of multiple quantum wells PD structure;
(8) Sapphire Substrate (number 2) polishing is carried out to be thinned.
(9) by the one side of Sapphire Substrate (number 1) non-growth of device and Sapphire Substrate (number 2) non-growth of device It is bonded together on one side by Bonding, using electron beam evaporation technique, respectively multiple quantum wells LED structure and multiple quantum wells PD structure plates metal electrode, and GaN base Vertical collection opto chip is prepared in package lead.
Referring to Fig.1, in conjunction with specific embodiments to GaN base Vertical collection opto chip of the invention further specifically It is bright as follows:
The required substrate of GaN material is selected, the present invention selects sapphire as substrate.
Multiple quantum wells LED structure is prepared using multistep growth method, utilizes high temperature MOCVD technology growth GaN epitaxial layer, n- GaN layer, InGaN/GaN layers and p-GaN layer, the especially method of high temperature MOCVD, do not have particular/special requirement, root to the thickness of each layer It is designed according to actual needs.N-GaN is that Si is adulterated in GaN material, and InGaN/GaN layers are by InGaN and GaN according to certain The group of ratio is grouped as structure obtained from growth, the light of the wavelength emitted needed for being set according to the In component in InGaN, p- GaN is that Mg is doped in GaN material.
The present invention utilizes photoetching technique, carves the integrated waveguide design configuration on mask plate.
Using electron beam evaporation technique, Schottky contact electrode Ni/Au composite layer is evaporated in p-GaN layer, with a thickness of 10-300 nanometers.
Using quick anneal oven, anneal under nitrogen atmosphere to Ni/Au Schottky contact electrode, annealing temperature 400- 600 degrees Celsius, the time is 3-15 minutes.
It repeats the above steps and multiple quantum wells PD structure is prepared.
By passing through on one side for the non-growth of device of Sapphire Substrate of multiple quantum wells LED structure and multiple quantum wells PD structure Bonding is bonded together, lead packages.
Present invention will be further explained below with reference to the attached drawings and examples, but the present invention is not limited to these Examples.
Embodiment 1
(1) Sapphire Substrate (number 1) is cleaned, with being dried with nitrogen.
(2) GaN epitaxial layer is grown on a sapphire substrate before this using MOCVD method, then grow in GaN epitaxial layer N-GaN layers, then InGaN/GaN layers (alternatively referred to as MQWs layers) is grown on n-GaN layer.
(3) photoresist is coated on InGaN/GaN layers and carries out photoetching development, will use covering of having customized in exposure process Graphics field on mask plate is completely disposed above chip, sets the time for exposure of 7s, by exposure technique, will set by film version The pattern transfer on mask plate counted is to photoresist layer.Device after exposure develops, and comes out graphical display. Development mainly uses 3038 developer solutions, is cleaned and is dried with nitrogen with clear water after development, then dry steam on hot plate, so far Complete photoetching development step.It also needs to carry out structure of the ICP nitride etch to form device after photoetching development, be dried in cleaning It is dry.Then p-GaN layer is grown on the InGaN/GaN layer after photoetching, etching, completes the preparation of multiple quantum wells LED structure;
N-GaN is that Si is adulterated in GaN material, and p-GaN is that Mg is doped in GaN material;
(4) metal electrode Ni/Au is prepared in multiple quantum wells LED structure by being evaporated in vacuo, with a thickness of 100 nanometers, so After annealing, annealing temperature are 500 degrees Celsius, and the time is 10 minutes;
(5) since Sapphire Substrate (number 1) is too thick, it would be desirable to substrate polishing be thinned to reduce the propagation road of light Diameter.
(6) Sapphire Substrate (number 2) is cleaned, with being dried with nitrogen.
(7) GaN epitaxial layer is grown on a sapphire substrate before this using MOCVD method, then grow in GaN epitaxial layer N-GaN layers, then InGaN/GaN layers are grown on n-GaN layer, and volume is improved by the component ratio of adjusting InGaN/GaN The luminous efficiency of sub- trap PD.
(8) photoresist is coated on InGaN/GaN layers and carries out photoetching development, will use covering of having customized in exposure process Graphics field on mask plate is completely disposed above chip, sets the time for exposure of 7s, by exposure technique, will set by film version The waveguiding structure counted on mask plate is transferred to photoresist layer.Chip after exposure develops, and goes out graphical display Come.Development mainly uses 3038 developer solutions, is cleaned and is dried with nitrogen with clear water after development, then dries steam on hot plate, So far photoetching development step is completed.It also needs to carry out structure of the ICP nitride etch to form device after photoetching development, clean Drying.Then p-GaN layer is grown on the InGaN/GaN layer after photoetching, etching, completes the preparation of multiple quantum wells PD structure;
(9) metal electrode Ni/Au is prepared in multiple quantum wells PD structure by being evaporated in vacuo, with a thickness of 100 nanometers, then Annealing, annealing temperature are 500 degrees Celsius, and the time is 10 minutes;
(10) Sapphire Substrate (number 2) polishing is carried out to be thinned.
(11) by the one side of Sapphire Substrate (number 1) non-growth of device and Sapphire Substrate (number 2) non-growth of device One side be bonded together by Bonding, GaN base Vertical collection photoelectron core shown in FIG. 1 can be obtained in package lead Piece.
Embodiment 2
(1) Sapphire Substrate (number 1) is cleaned, with being dried with nitrogen.
(2) GaN epitaxial layer is grown on a sapphire substrate before this using MOCVD method, then grow in GaN epitaxial layer N-GaN layers, then InGaN/GaN layers (alternatively referred to as MQWs layers) is grown on n-GaN layer.
(3) photoresist is coated on InGaN/GaN layers and carries out photoetching development, will use covering of having customized in exposure process Graphics field on mask plate is completely disposed above chip, sets the time for exposure of 7s, by exposure technique, will set by film version The pattern transfer on mask plate counted is to photoresist layer.Device after exposure develops, and comes out graphical display. Development mainly uses 3038 developer solutions, is cleaned and is dried with nitrogen with clear water after development, then dry steam on hot plate, so far Complete photoetching development step.It also needs to carry out structure of the ICP nitride etch to form device after photoetching development, be dried in cleaning It is dry.Then p-GaN layer is grown on the InGaN/GaN layer after photoetching, etching, completes the preparation of multiple quantum wells LED structure;
N-GaN is that Si is adulterated in GaN material, and p-GaN is that Mg is doped in GaN material;
(4) metal electrode Ti/Al is prepared in multiple quantum wells LED structure by being evaporated in vacuo, with a thickness of 50 nanometers, then Annealing, annealing temperature are 600 degrees Celsius, and the time is 2 minutes;
(5) since Sapphire Substrate (number 1) is too thick, it would be desirable to substrate polishing be thinned to reduce the propagation road of light Diameter.
(6) Sapphire Substrate (number 2) is cleaned, with being dried with nitrogen.
(7) GaN epitaxial layer is grown on a sapphire substrate before this using MOCVD method, then grow in GaN epitaxial layer N-GaN layers, then InGaN/GaN layers are grown on n-GaN layer, and volume is improved by the component ratio of adjusting InGaN/GaN The luminous efficiency of sub- trap PD.
(8) photoresist is coated on InGaN/GaN layers and carries out photoetching development, will use covering of having customized in exposure process Graphics field on mask plate is completely disposed above chip, sets the time for exposure of 7s, by exposure technique, will set by film version The waveguiding structure counted on mask plate is transferred to photoresist layer.Chip after exposure develops, and goes out graphical display Come.Development mainly uses 3038 developer solutions, is cleaned and is dried with nitrogen with clear water after development, then dries steam on hot plate, So far photoetching development step is completed.It also needs to carry out structure of the ICP nitride etch to form device after photoetching development, clean Drying.Then p-GaN layer is grown on the InGaN/GaN layer after photoetching, etching, completes the preparation of multiple quantum wells PD structure;
(9) metal electrode Ti/Al is prepared in multiple quantum wells PD structure by being evaporated in vacuo, with a thickness of 50 nanometers, then Annealing, annealing temperature are 600 degrees Celsius, and the time is 2 minutes;
(10) Sapphire Substrate (number 2) polishing is carried out to be thinned.
(11) by the one side of Sapphire Substrate (number 1) non-growth of device and Sapphire Substrate (number 2) non-growth of device One side be bonded together by Bonding, GaN base Vertical collection photoelectron core shown in FIG. 1 can be obtained in package lead Piece.
Metal electrode in above-described embodiment may be replaced by other metal electrodes of above-mentioned restriction, here no longer one by one It enumerates.
Multiple quantum wells LED structure of the invention has good luminous efficiency and detection effect with multiple quantum wells PD structure Rate, by the performance etc. for adjusting the adjustable device of In component.The dislocation density of Sapphire Substrate and GaN material is small.Nanoparticle The density and dislocation density of son are close.The type of GaN Schottky contact electrode is Ni, Au, Pt or Ni/Au, Ti/Al, Ti/ The condition of composite materials multilayer film such as Al/Ti/Au etc., electrode anneal can be depending on specific metal species, such as Ni/ Au combination electrode, annealing conditions temperature are 400-600 degree, and the time is 3-15 points;If the annealing temperature of Ti/Al is 500-700 degree, Time -5 minutes 30 seconds.
The method of the present invention is not limited to the above embodiments, and GaN base Vertical collection opto chip structure of the present invention is relative to biography The advantages of Horizontal collection waveguiding structure of system, is that GaN first and sapphire will not all absorb the light that light source is issued, this is It is determined by the band gap of material.The most important be this structure can with individually designed LED, PD multi-quantum pit structure, LED, PD performance is set to respectively reach optimal performance, this is that conventional flat structure is not achieved.From the perspective of long term growth, It can produce three-dimensional photoelectricity interacted system when this Vertical collection waveguide and current Horizontal collection waveguide are combined, favorably In the integrated of photoelectricity interconnection, possess potential commercial value.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or It changes still within the protection scope of the invention.

Claims (9)

1. a kind of GaN base Vertical collection opto chip, which is characterized in that including multiple quantum wells diode (LED) part and volume The part sub- well detector PD;
Multiple quantum wells diode (LED) part includes: substrate and multiple quantum wells LED structure;
The multiple quantum wells LED structure include successively grow GaN epitaxial layer on substrate, n-GaN layers, InGaN/GaN layers and P-GaN layer;
The part multiple quantum wells detector PD includes: substrate and multiple quantum wells PD structure;
The multiple quantum wells PD structure includes successively growing GaN epitaxial layer on substrate, n-GaN layers, InGaN/GaN layers and p- GaN layer;
The one side of the non-growth of device of substrate of multiple quantum wells diode (LED) part and the part multiple quantum wells detector PD Substrate non-growth of device be bonded together on one side;
The multiple quantum wells LED structure and the multiple quantum wells PD structure are coated with metal electrode respectively, and are packaged with lead.
2. GaN base Vertical collection opto chip according to claim 1, which is characterized in that the n-GaN is in GaN Si is adulterated in material, p-GaN is that Mg is doped in GaN material.
3. GaN base Vertical collection opto chip according to claim 1, which is characterized in that the substrate be sapphire, Silicon or silicon carbide.
4. GaN base Vertical collection opto chip according to claim 1, which is characterized in that the metal electrode be Ni, Au, Pt, Ni/Au, Ti/Al or Ti/Al/Ti/Au.
5. the preparation method of GaN base Vertical collection opto chip, feature described in a kind of claim 1-4 any one exist In, comprising the following steps:
Step 1: growing GaN epitaxial layer on substrate;
Step 2: growing n-GaN layers in GaN epitaxial layer;
Step 3: growing InGaN/GaN layers on n-GaN layer;
Step 4: carrying out photoetching, etching after the InGaN/GaN layer spin coating photoresist of step 3;
Step 5: growing p-GaN layer on InGaN/GaN layers, the preparation of multiple quantum wells LED structure is completed;
Step 6: repeating step 1 to five, multiple quantum wells PD structure is obtained;
It is thinned Step 7: the one side of the non-growth of device of above-mentioned two substrate is polished, is then bonded together;
Step 8: distinguish evaporation metal electrode in the multiple quantum wells LED structure and the multiple quantum wells PD structure, then lead The preparation of GaN base Vertical collection opto chip is completed in encapsulation.
6. the preparation method of GaN base Vertical collection opto chip according to claim 5, which is characterized in that use MOCVD technology growth GaN epitaxial layer, n-GaN layers, InGaN/GaN layers or p-GaN layer.
7. the preparation method of GaN base Vertical collection opto chip according to claim 5, which is characterized in that step 4 Described in photoresist be negative photoresist or the positive photo glue with reverse speed characterisstic.
8. the preparation method of GaN base Vertical collection opto chip according to claim 5, which is characterized in that work as metal Electrode is Ni/Au combination electrode, and annealing conditions temperature is 400-600 degrees Celsius, and the time is 3-15 minutes.
9. the preparation method of GaN base Vertical collection opto chip according to claim 5, which is characterized in that work as metal Electrode is Ti/Al combination electrode, and annealing temperature is 500-700 degrees Celsius, the time -5 minutes 30 seconds.
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Cited By (2)

* Cited by examiner, † Cited by third party
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CN114400262A (en) * 2022-01-18 2022-04-26 南京邮电大学 Gallium nitride photoelectron integrated chip and preparation method thereof
RU2810635C1 (en) * 2023-07-25 2023-12-28 Акционерное общество "НПО "Орион" Method for manufacturing dual-spectral photosensitive element based on schottky barrier using mesa technology

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649147A (en) * 2004-12-16 2005-08-03 南通富士通微电子股份有限公司 Back-to-back packaging integrated circuit and its producing method
CN101558348A (en) * 2006-09-29 2009-10-14 佛罗里达大学研究基金公司 Method and apparatus for infrared detection and display
CN102347518A (en) * 2011-06-24 2012-02-08 中国科学院上海微系统与信息技术研究所 Micro-energy system with high energy density per unit volume and fabrication method thereof
CN103515467A (en) * 2012-06-26 2014-01-15 北京大学 Delta E-E nuclear radiation detector based on substrate bonding and preparation method thereof
CN103839931A (en) * 2012-11-26 2014-06-04 西安威正电子科技有限公司 Double-faced packaging structure of double chips
WO2015057771A1 (en) * 2013-10-15 2015-04-23 The Penn State Research Foundation Light emitting diodes and photodetectors
CN105428305A (en) * 2015-11-20 2016-03-23 南京邮电大学 Suspended LED optical waveguide and photoelectric detector monolithic integrated device and preparation method thereof
CN107482031A (en) * 2017-08-09 2017-12-15 南京邮电大学 GaN base micron order LED array and preparation method thereof
WO2018063438A1 (en) * 2016-09-29 2018-04-05 The Regents Of The University Of California Visible light communication system-on-a-chip
CN108735852A (en) * 2017-04-21 2018-11-02 株式会社村田制作所 Optical sensor
CN108964762A (en) * 2018-07-23 2018-12-07 京东方科技集团股份有限公司 Visible light communication device and its driving method, door lock and visible light communication method

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649147A (en) * 2004-12-16 2005-08-03 南通富士通微电子股份有限公司 Back-to-back packaging integrated circuit and its producing method
CN101558348A (en) * 2006-09-29 2009-10-14 佛罗里达大学研究基金公司 Method and apparatus for infrared detection and display
CN102347518A (en) * 2011-06-24 2012-02-08 中国科学院上海微系统与信息技术研究所 Micro-energy system with high energy density per unit volume and fabrication method thereof
CN103515467A (en) * 2012-06-26 2014-01-15 北京大学 Delta E-E nuclear radiation detector based on substrate bonding and preparation method thereof
CN103839931A (en) * 2012-11-26 2014-06-04 西安威正电子科技有限公司 Double-faced packaging structure of double chips
WO2015057771A1 (en) * 2013-10-15 2015-04-23 The Penn State Research Foundation Light emitting diodes and photodetectors
CN105428305A (en) * 2015-11-20 2016-03-23 南京邮电大学 Suspended LED optical waveguide and photoelectric detector monolithic integrated device and preparation method thereof
WO2018063438A1 (en) * 2016-09-29 2018-04-05 The Regents Of The University Of California Visible light communication system-on-a-chip
CN108735852A (en) * 2017-04-21 2018-11-02 株式会社村田制作所 Optical sensor
CN107482031A (en) * 2017-08-09 2017-12-15 南京邮电大学 GaN base micron order LED array and preparation method thereof
CN108964762A (en) * 2018-07-23 2018-12-07 京东方科技集团股份有限公司 Visible light communication device and its driving method, door lock and visible light communication method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114400262A (en) * 2022-01-18 2022-04-26 南京邮电大学 Gallium nitride photoelectron integrated chip and preparation method thereof
RU2810635C1 (en) * 2023-07-25 2023-12-28 Акционерное общество "НПО "Орион" Method for manufacturing dual-spectral photosensitive element based on schottky barrier using mesa technology

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