CN109904154A - A kind of super barrier rectifier of groove and preparation method thereof - Google Patents
A kind of super barrier rectifier of groove and preparation method thereof Download PDFInfo
- Publication number
- CN109904154A CN109904154A CN201910152821.XA CN201910152821A CN109904154A CN 109904154 A CN109904154 A CN 109904154A CN 201910152821 A CN201910152821 A CN 201910152821A CN 109904154 A CN109904154 A CN 109904154A
- Authority
- CN
- China
- Prior art keywords
- conduction type
- layer
- groove
- doped epitaxial
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 230000004888 barrier function Effects 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 210000000746 body region Anatomy 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of super barrier rectifier of groove and preparation method thereof.The super barrier rectifier of groove includes the first conduction type heavy doping substrate layer, the first conduction type doped epitaxial layer, the first conduction type lightly doped epitaxial layer, gate dielectric layer, gate electrode layer, the second conductivity type body region, the first conduction type heavy doping source region, front electrode layer and back electrode layer.Present invention incorporates PN diode, Schottky diode and MOS transistor leakage current are low, the advantages such as cut-in voltage is low, the shortcomings that eliminating thermal instability compared to conventional schottky thickeies the voltage endurance capability and reliability for improving oxide gate dielectric layer using trench base oxide；Anode of the present invention uses grooving structure, increases the contact area of the first conduction type source region, reduces contact resistance；Simultaneously using the double epitaxial layers of the first conduction type of different levels of doping and trench gate structure, the conducting resistance of device is further decreased, the on-state power consumption of device is reduced.
Description
Technical field
The present invention relates to power semiconductor rectifiers, especially provide a kind of super barrier rectifier of groove and its preparation side
Method.
Background technique
Power semiconductor rectifier, is widely used in power converter and power supply.The power of two kinds of basic structures is partly led
Body rectifier is PIN power rectifier and Schottky barrier rectifier.The former forward voltage drop is big, and reverse recovery time is long, but leaks
Electricity is smaller, and has superior high-temperature stability, is mainly used in the mesohigh range of 300V or more.The latter is mainly used in
200V mesolow range below, forward voltage drop is small, and reverse recovery time is short, but reverse leakage current is higher, high temperature reliability
It is poor.Super barrier rectifier integrates rectifier diode and MOS transistor in parallel between the anode and cathode to be had to be formed
It is excellent with significantly competing in 100V application below compared with low forward conduction voltage, the rectifying device of more stable high-temperature behavior
Gesture.
Summary of the invention
To solve the above-mentioned problems, the object of the present invention is to provide a kind of super potential barriers of groove for reducing device on-state power consumption
Rectifier and preparation method thereof.
In order to achieve the above objectives, technical scheme is as follows: a kind of super barrier rectifier of groove and its preparation side
Method, including the first conduction type heavy doping substrate layer (10), the first conduction type doped epitaxial layer (20), the first conduction type are light
Doped epitaxial layer (30), gate dielectric layer (401,402), gate electrode layer (501), the second conductivity type body region (60), first are led
Electric type heavy doping source region (70), front electrode layer (801), back electrode layer (802)；The first conduction type doped epitaxial
Layer (20) is covered on the first conduction type heavy doping substrate layer (10)；The first conduction type lightly doped epitaxial layer (30)
It is covered on the first conduction type doped epitaxial layer (20)；Portion on the first conduction type lightly doped epitaxial layer (30)
Surface is divided to form groove (301) structure, groove (301) surface is covered by gate dielectric layer (401,402), the gate dielectric layer
Covering grid electrode layer (501) on (401,402), and gate electrode layer (501) fills up entire groove (301)；Described second is conductive
Type body region (60) is covered on the remainder surface on the first conduction type lightly doped epitaxial layer (30), is situated between with the grid
The partial region of matter layer (402) exterior side wall is connected；The first conduction type heavy doping source region (70) is covered on the second conduction
Part of the surface on type body region (60) is also connected with the partial region of the gate dielectric layer (402) exterior side wall；It is described
Front electrode layer (801) is covered on the second conductivity type body region (60), the first conduction type heavy doping source region (70), gate dielectric
On layer (402) and gate electrode layer (501)；The back electrode layer (802) is located at the first conduction type heavy doping substrate layer
(10) lower surface.
Further, preparation method the following steps are included:
Step 1: providing a heavy doping N+ substrate as the first conduction type heavy doping substrate layer (10), in first conduction
Extension the first conduction type doped epitaxial layer (20) on type heavy doping substrate layer (10)；
Step 2: extension the first conduction type lightly doped epitaxial layer (30) on the first conduction type doped epitaxial layer (20)；
Step 3: in first conduction type lightly doped epitaxial layer (30) top etching groove (301)；
Step 4: in the first conduction type lightly doped epitaxial layer (30) upper surface and groove (301) sidewall growth trench oxide
(40)；
Step 5: being thickeied channel bottom gate dielectric layer (401) by anisotropic oxide growth；
Step 6: filling up entire groove (301) in groove (301) interior depositing polysilicon (50)；
Step 7: the polysilicon (50) in isotropic etching groove (301) forms gate electrode layer (501)；
Step 8: the first conduction type heavy doping source region (70) is injected；
Step 9: source contact hole (701) etch；
Step 10: P+ source region (702) is injected；
Step 11: front metal deposit and etching, form front electrode layer (801)；
Step 12: thinning back side, injection and back metal deposit；It is formed back electrode layer (802).
Further, the doping concentration of the first conduction type lightly doped epitaxial layer (30) is mixed than first conduction type
Miscellaneous epitaxial layer (20) it is lower.
Further, the upper surface of the gate electrode layer (501) forms the inclined-plane of a certain angle.
Further, anode uses grooving structure, increases the area N+ contact area, reduces contact resistance.
Further, the conducting resistance for reducing device by using double epitaxial layers and groove structure reduces the on-state of device
Power consumption.
The beneficial effects of the present invention are: (1) present invention incorporates the leakages of PN diode, Schottky diode and MOS transistor
The advantages such as electric current is low, and cut-in voltage is low, the shortcomings that eliminating thermal instability compared to conventional schottky, using groove
Bottom oxide thickeies the voltage endurance capability and reliability for improving oxide gate dielectric layer；(2) anode of the present invention uses grooving knot
Structure increases the contact area of the first conduction type source region, reduces contact resistance；(3) present invention is using the of different levels of doping
The double epitaxial layers of one conduction type and trench gate structure, further decrease the conducting resistance of device, reduce the on-state power consumption of device.
(4) the advantages of present invention has manufacturing process flow simple, characteristic good.
Detailed description of the invention
Fig. 1 is structure of the invention sectional view；Fig. 2 is principle of the invention figure；Fig. 3-13 is preparation method block diagram of the present invention.
Specific embodiment
It describes the specific embodiments of the present invention in detail with reference to the accompanying drawing.
As shown, a kind of super barrier rectifier of groove and preparation method thereof, including the first conduction type heavy doping lining
Bottom (10), the first conduction type doped epitaxial layer (20), the first conduction type lightly doped epitaxial layer (30), gate dielectric layer
(401,402), gate electrode layer (501), the second conductivity type body region (60), the first conduction type heavy doping source region (70), front
Electrode layer (801), back electrode layer (802)；The first conduction type doped epitaxial layer (20) is covered in the first conduction type
On heavy doping substrate layer (10)；It is outer that the first conduction type lightly doped epitaxial layer (30) is covered in the doping of the first conduction type
Prolong on layer (20)；Part of the surface on the first conduction type lightly doped epitaxial layer (30) forms groove (301) structure,
Groove (301) surface is covered by gate dielectric layer (401,402), covering grid electrode on the gate dielectric layer (401,402)
Layer (501), and gate electrode layer (501) fills up entire groove (301)；Second conductivity type body region (60) is covered on first and leads
Remainder surface on electric type lightly doped epitaxial layer (30), the part with the gate dielectric layer (402) exterior side wall
Region is connected；The first conduction type heavy doping source region (70) is covered on the part table on the second conductivity type body region (60)
Face is also connected with the partial region of the gate dielectric layer (402) exterior side wall；The front electrode layer (801) is covered on
Two conductivity type body regions (60), the first conduction type heavy doping source region (70), gate dielectric layer (402) and gate electrode layer (501)
On；The back electrode layer (802) is located at the lower surface of the first conduction type heavy doping substrate layer (10).
Preparation method the following steps are included:
Step 1: providing a heavy doping N+ substrate as the first conduction type heavy doping substrate layer (10), in first conduction
Extension the first conduction type doped epitaxial layer (20) on type heavy doping substrate layer (10)；
Step 2: extension the first conduction type lightly doped epitaxial layer (30) on the first conduction type doped epitaxial layer (20)；
Step 3: in first conduction type lightly doped epitaxial layer (30) top etching groove (301)；
Step 4: in the first conduction type lightly doped epitaxial layer (30) upper surface and groove (301) sidewall growth trench oxide
(40)；
Step 5: being thickeied channel bottom gate dielectric layer (401) by anisotropic oxide growth；
Step 6: filling up entire groove (301) in groove (301) interior depositing polysilicon (50)；
Step 7: the polysilicon (50) in isotropic etching groove (301) forms gate electrode layer (501)；
Step 8: the first conduction type heavy doping source region (70) is injected；
Step 9: source contact hole (701) etch；
Step 10: P+ source region (702) is injected；
Step 11: front metal deposit and etching, form front electrode layer (801)；
Step 12: thinning back side, injection and back metal deposit；It is formed back electrode layer (802).
The doping concentration of the first conduction type lightly doped epitaxial layer (30) is than the first conduction type doped epitaxial
Layer (20) it is lower.
The upper surface of the gate electrode layer (501) forms the inclined-plane of a certain angle.
Anode uses grooving structure, increases the area N+ contact area, reduces contact resistance.
The conducting resistance for reducing device by using double epitaxial layers and groove structure reduces the on-state power consumption of device.
Working principle: when SBR anode of the present invention adds positive voltage, be equivalent to metal-oxide-semiconductor source electrode and grid at the same add positive voltage,
Longitudinal conducting channel is formed, and electric current flows to cathode by anode；When cathode adds positive voltage, the second conductivity type body region (60) and
One conduction type lightly doped epitaxial layer (30) forms reverse-biased PN junction pressure resistance, and SBR is smaller than the forward voltage drop of conventional diode, can be with
Obtain the forward voltage drop close to Schottky diode.Meanwhile SBR has temperature stability more better than Schottky diode, SBR's
Another advantage is that leakage current ratio Xiao Te diode is smaller.SBR schematic diagram as shown in Figure 2, can be equivalent to grid G and source electrode
S be shorted after a DMOS forward diode structure in parallel, wherein 601 ' be anode, when anode plus positive voltage, electric current can be with
SBR cathode is flowed to by MOS structure channel and diode；When cathode making alive, MOS structure and diode are all in shutdown shape
State, SBR bear backward voltage.
It is to be illustrated to preferable implementation of the invention, but the invention is not limited to the implementation above
Example, those skilled in the art can also make various equivalent variations on the premise of without prejudice to spirit of the invention or replace
It changes, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.
Claims (6)
1. a kind of super barrier rectifier of groove and preparation method thereof, it is characterised in that: served as a contrast including the first conduction type heavy doping
Bottom (10), the first conduction type doped epitaxial layer (20), the first conduction type lightly doped epitaxial layer (30), gate dielectric layer
(401,402), gate electrode layer (501), the second conductivity type body region (60), the first conduction type heavy doping source region (70), front
Electrode layer (801) and back electrode layer (802)；The first conduction type doped epitaxial layer (20) is covered in the first conduction type
On heavy doping substrate layer (10)；It is outer that the first conduction type lightly doped epitaxial layer (30) is covered in the doping of the first conduction type
Prolong on layer (20)；Part of the surface on the first conduction type lightly doped epitaxial layer (30) forms groove (301) structure,
Groove (301) surface is covered by gate dielectric layer (401,402), covering grid electrode on the gate dielectric layer (401,402)
Layer (501), and gate electrode layer (501) fills up entire groove (301)；Second conductivity type body region (60) is covered on first and leads
Remainder surface on electric type lightly doped epitaxial layer (30), the part with the gate dielectric layer (402) exterior side wall
Region is connected；The first conduction type heavy doping source region (70) is covered on the part table on the second conductivity type body region (60)
Face is also connected with the partial region of the gate dielectric layer (402) exterior side wall；The front electrode layer (801) is covered on
Two conductivity type body regions (60), the first conduction type heavy doping source region (70), gate dielectric layer (402) and gate electrode layer (501)
On；The back electrode layer (802) is located at the lower surface of the first conduction type heavy doping substrate layer (10).
2. super barrier rectifier of a kind of groove according to claim 1 and preparation method thereof, it is characterised in that: preparation side
Method the following steps are included:
Step 1: providing a heavy doping N+ substrate as the first conduction type heavy doping substrate layer (10), in first conduction
Extension the first conduction type doped epitaxial layer (20) on type heavy doping substrate layer (10)；
Step 2: extension the first conduction type lightly doped epitaxial layer (30) on the first conduction type doped epitaxial layer (20)；
Step 3: in first conduction type lightly doped epitaxial layer (30) top etching groove (301)；
Step 4: in the first conduction type lightly doped epitaxial layer (30) upper surface and groove (301) sidewall growth trench oxide
(40)；
Step 5: being thickeied channel bottom gate dielectric layer (401) by anisotropic oxide growth；
Step 6: filling up entire groove (301) in groove (301) interior depositing polysilicon (50)；
Step 7: the polysilicon (50) in isotropic etching groove (301) forms gate electrode layer (501)；
Step 8: the first conduction type heavy doping source region (70) is injected；
Step 9: source contact hole (701) etch；
Step 10: P+ source region (702) is injected；
Step 11: front metal deposit and etching, form front electrode layer (801)；
Step 12: thinning back side, injection and back metal deposit；It is formed back electrode layer (802).
3. super barrier rectifier of a kind of groove according to claim 1 and preparation method thereof, it is characterised in that: described
The doping concentration of one conduction type lightly doped epitaxial layer (30) is lower than the first conduction type doped epitaxial layer (20).
4. super barrier rectifier of a kind of groove according to claim 1 and preparation method thereof, it is characterised in that: the grid
The upper surface of electrode layer (501) forms the inclined-plane of a certain angle.
5. super barrier rectifier of a kind of groove according to claim 2 and preparation method thereof, it is characterised in that: anode is adopted
With grooving structure, increase the area N+ contact area, reduces contact resistance.
6. super barrier rectifier of a kind of groove according to claim 2 and preparation method thereof, it is characterised in that: by adopting
The conducting resistance for reducing device with double epitaxial layers and groove structure reduces the on-state power consumption of device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910152821.XA CN109904154A (en) | 2019-02-28 | 2019-02-28 | A kind of super barrier rectifier of groove and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910152821.XA CN109904154A (en) | 2019-02-28 | 2019-02-28 | A kind of super barrier rectifier of groove and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109904154A true CN109904154A (en) | 2019-06-18 |
Family
ID=66945848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910152821.XA Pending CN109904154A (en) | 2019-02-28 | 2019-02-28 | A kind of super barrier rectifier of groove and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109904154A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510079A (en) * | 2020-11-27 | 2021-03-16 | 龙腾半导体股份有限公司 | Charge balance groove super-barrier rectifier and manufacturing method thereof |
| CN114512402A (en) * | 2022-04-19 | 2022-05-17 | 深圳芯能半导体技术有限公司 | Groove type silicon carbide Schottky diode and manufacturing method thereof |
| CN116960189A (en) * | 2023-07-05 | 2023-10-27 | 重庆平伟实业股份有限公司 | High-efficiency Schottky contact super-barrier rectifier |
| CN117790423A (en) * | 2024-02-23 | 2024-03-29 | 芯联集成电路制造股份有限公司 | Semiconductor device and method for manufacturing the same, semiconductor integrated circuit and method for manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728270A (en) * | 2008-10-24 | 2010-06-09 | 北大方正集团有限公司 | Groove type DMOS tube and preparation method thereof |
| CN103337523A (en) * | 2013-06-19 | 2013-10-02 | 张家港凯思半导体有限公司 | Super potential barrier rectification device with inclined grooves, and manufacturing method thereof |
| CN207925475U (en) * | 2017-12-04 | 2018-09-28 | 贵州恒芯微电子科技有限公司 | A kind of trench gate super barrier rectifier |
| CN209312768U (en) * | 2019-02-28 | 2019-08-27 | 厦门芯一代集成电路有限公司 | A kind of super barrier rectifier of groove |
-
2019
- 2019-02-28 CN CN201910152821.XA patent/CN109904154A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728270A (en) * | 2008-10-24 | 2010-06-09 | 北大方正集团有限公司 | Groove type DMOS tube and preparation method thereof |
| CN103337523A (en) * | 2013-06-19 | 2013-10-02 | 张家港凯思半导体有限公司 | Super potential barrier rectification device with inclined grooves, and manufacturing method thereof |
| CN207925475U (en) * | 2017-12-04 | 2018-09-28 | 贵州恒芯微电子科技有限公司 | A kind of trench gate super barrier rectifier |
| CN209312768U (en) * | 2019-02-28 | 2019-08-27 | 厦门芯一代集成电路有限公司 | A kind of super barrier rectifier of groove |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510079A (en) * | 2020-11-27 | 2021-03-16 | 龙腾半导体股份有限公司 | Charge balance groove super-barrier rectifier and manufacturing method thereof |
| CN114512402A (en) * | 2022-04-19 | 2022-05-17 | 深圳芯能半导体技术有限公司 | Groove type silicon carbide Schottky diode and manufacturing method thereof |
| CN116960189A (en) * | 2023-07-05 | 2023-10-27 | 重庆平伟实业股份有限公司 | High-efficiency Schottky contact super-barrier rectifier |
| CN117790423A (en) * | 2024-02-23 | 2024-03-29 | 芯联集成电路制造股份有限公司 | Semiconductor device and method for manufacturing the same, semiconductor integrated circuit and method for manufacturing the same |
| CN117790423B (en) * | 2024-02-23 | 2024-05-24 | 芯联集成电路制造股份有限公司 | Semiconductor device and method for manufacturing the same, semiconductor integrated circuit and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109904154A (en) | A kind of super barrier rectifier of groove and preparation method thereof | |
| CN103718297B (en) | Super-junction schottky-pin-diode | |
| WO2020151088A1 (en) | Super-junction power vdmos having extremely low reverse recovery charge | |
| CN101710593A (en) | Schottky diode | |
| CN105810754B (en) | A kind of metal-oxide-semiconductor diode with accumulation layer | |
| CN114050187A (en) | Integrated trench gate power semiconductor transistor with low characteristic on-resistance | |
| US8716784B2 (en) | Semiconductor device and associated fabrication method | |
| CN106356401A (en) | Field limiting ring terminal structure for power semiconductor device | |
| CN210805778U (en) | SiC-MOS device structure | |
| CN113990923A (en) | Silicon carbide double-groove MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with trench diode | |
| CN109037071A (en) | A kind of preparation method of shield grid power device | |
| CN203300654U (en) | Oblique-trench Schottky barrier rectifying device | |
| CN103325846B (en) | A kind of manufacture method of valley gutter Schottky barrier rectification element | |
| CN102709317A (en) | Low-threshold voltage diode | |
| CN209312768U (en) | A kind of super barrier rectifier of groove | |
| CN109148566A (en) | Silicon carbide MOSFET device and its manufacturing method | |
| CN109119490A (en) | A kind of slot grid diode of composite construction | |
| CN109119489A (en) | A kind of metal-oxide-semiconductor diode of composite construction | |
| CN115602734A (en) | Novel silicon carbide power diode with high forward current density | |
| CN111211160B (en) | Vertical GaN power diode | |
| CN106229342A (en) | A kind of metal-oxide-semiconductor diode of many accumulation layers | |
| CN112510079A (en) | Charge balance groove super-barrier rectifier and manufacturing method thereof | |
| CN102244106A (en) | Schottky diode | |
| CN106783954B (en) | A kind of low-power channel schottky rectifying device and its manufacturing method | |
| CN215299260U (en) | Groove gate type super barrier rectifying device with low conduction voltage drop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |