CN117790423B

CN117790423B - Semiconductor device and method for manufacturing the same, semiconductor integrated circuit and method for manufacturing the same

Info

Publication number: CN117790423B
Application number: CN202410199362.1A
Authority: CN
Inventors: 王聪; 宋健; 戚蓥梦; 黄艳
Original assignee: Xinlian Integrated Circuit Manufacturing Co ltd
Current assignee: Xinlian Integrated Circuit Manufacturing Co ltd
Priority date: 2024-02-23
Filing date: 2024-02-23
Publication date: 2024-05-24
Anticipated expiration: 2044-02-23
Also published as: CN117790423A

Abstract

The invention provides a semiconductor device and a preparation method thereof, and a semiconductor integrated circuit and a preparation method thereof. In the semiconductor device, the first transistor device is arranged in the cell region, the super barrier rectifying region is formed in the rectifying region, the first gate dielectric layer and the first gate electrode in the first transistor device are formed in the first groove, and the second gate dielectric layer and the second gate electrode in the super barrier rectifier are formed on the top surface of the substrate, so that the gate structure on the top surface of the substrate in the super barrier rectifier can be prepared more flexibly, and the simplification of the process is facilitated. Further, the gate structure of the super-barrier rectifier can be combined with the preparation process of the planar gate structure of other devices (such as the second transistor device in the BCD device) so as to parasitically form the gate structure of the super-barrier rectifier by utilizing the preparation process of the planar gate structure of the other devices which are integrally arranged, thereby greatly simplifying the preparation process of the integrated circuit and effectively reducing the preparation cost.

Description

Semiconductor device and method for manufacturing the same, semiconductor integrated circuit and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same, and a semiconductor integrated circuit and a method for manufacturing the same.

Background

In the prior art, the commonly used rectifiers generally include schottky barrier rectifiers and super barrier rectifiers (SBR, super Barrier Rectifier), wherein the super barrier rectifiers SBR can provide a low barrier environment for majority carriers in a MOS channel, can achieve lower reverse voltage and lower reverse leakage current, and are widely used in power semiconductor devices due to the advantages of higher stability and reliability.

Taking a shielded gate field effect transistor (SHIELDED GATE TRENCH, SGT) as an example, a shielding electrode is arranged below the gate electrode, so that the gate-drain capacitance can be greatly reduced, the electric field of the device is optimized, the breakdown voltage is improved, the drift region of the SGT device also has higher impurity carrier concentration, and the on-resistance can be correspondingly reduced. For the semiconductor device with the shielded gate field effect transistor, in order to realize quick switching, increase reverse recovery speed and reduce power consumption when the transistor is turned off, a super barrier rectifier SBR can be additionally arranged in the semiconductor device so as to increase the turn-off speed of the device in the turn-off process of the transistor.

Currently, when the super barrier rectifier SBR is integrally provided, it is generally provided in a structure similar to that of an integrally provided transistor device, and the gate dielectric layer in the super barrier rectifier SBR and the gate dielectric layer in the transistor device are respectively provided to different thicknesses. For example, referring to fig. 5, a structure is illustrated in fig. 5 in which a super barrier rectifier SBR is integrally provided in an SGT device, the SGT device including a first gate dielectric layer 23A and a first gate electrode 24A disposed within a first trench 20A, the super barrier rectifier SBR including a second gate dielectric layer 23B and a second gate electrode 24B disposed within a second trench 20B. The thickness of the second gate dielectric layer 23B is smaller than that of the first gate dielectric layer 23A, so that the super barrier rectifier SBR has a lower turn-on voltage, and thus can be turned on when the SGT device is turned off, so as to serve as a current drain channel.

Since the second gate dielectric layer 23B in the super barrier rectifier SBR and the first gate dielectric layer 23A in the SGT device need to be set to different thicknesses to meet the requirements of the respective devices. For this reason, when preparing the first gate dielectric layer 23A and the second gate dielectric layer 23B, it is generally necessary to remove the dielectric material in the second trench 20B after preparing the first gate dielectric layer 23A, and to prepare the second gate dielectric layer 23B on the sidewall of the second trench 20B again, which is complicated in preparation process and high in cost.

Disclosure of Invention

The invention aims to provide a semiconductor device, the manufacturing process of which is easy to simplify and is beneficial to reducing the manufacturing cost.

To this end, the present invention provides a semiconductor device comprising: a substrate defining a cellular region and a rectifying region; a first transistor device formed in the cellular region, the first transistor device comprising: a first trench formed in the substrate; a first gate dielectric layer and a first gate electrode formed in the first trench; and a super barrier rectifier formed in the rectifying region, the super barrier rectifier comprising: and a second gate dielectric layer and a second gate electrode formed on the top surface of the substrate, wherein the thickness of the second gate dielectric layer is smaller than the thickness of the first gate dielectric layer.

Optionally, the first transistor device includes a shielded gate field effect transistor, and a shielding electrode is further formed in the first trench, where the shielding electrode is located below the first gate electrode.

Optionally, the first transistor device further includes a first well region and a first source region formed in the substrate at a side of the first trench, and the first well region extends to a deeper position of the substrate with respect to the first source region, so that the first gate electrode and the first well region have a portion overlapping each other. The super barrier rectifier further includes a second well region and a second source region formed in the substrate at a side of the second gate electrode and extending to below the second gate electrode in a direction of the second gate electrode, and the second well region extends to a larger size below the second gate electrode with respect to the second source region so that the second gate electrode and the second well region have portions overlapping each other.

Optionally, a dimension of a portion of the second gate electrode overlapping the second well region in a width direction is smaller than or equal to a dimension of a portion of the first gate electrode overlapping the first well region in a height direction.

Optionally, a second trench is further formed in the rectifying region, the second trench is formed on a side of the second gate structure facing away from the second source region, and a conductive material layer is formed in the second trench.

Optionally, at least two rectifying units are disposed in the same rectifying area, and the second groove is disposed between adjacent rectifying units.

Optionally, at least two rectifying units are disposed in the same rectifying region, at least one second gate electrode is formed in the rectifying region, and the second gate electrode forms a gate electrode shared by the two rectifying units on two sides of the second gate electrode.

Optionally, the semiconductor device has a device region including a plurality of cell regions, and the rectifying region is disposed between part of adjacent cell regions in the device region; and/or the rectifying region is arranged at the edge of the device region.

Optionally, an inversion doped region is further formed in the substrate of the rectifying region, and the conductivity type of the inversion doped region is opposite to that of the substrate.

The invention also provides a preparation method of the semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate is defined with a cellular region and a rectifying region; etching the substrate to form a first groove at least in the substrate of the cell area; forming a first gate dielectric layer and a first gate electrode in a first trench of the cellular region for forming a first transistor device; and forming a second gate dielectric layer and a second gate electrode on the top surface of the substrate of the rectifying region for forming a super barrier rectifier, wherein the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer.

Optionally, the preparation method further comprises: forming a second trench in the substrate of the rectifying region while etching the substrate to form the first trench; and filling a conductive material layer in the second groove.

Optionally, forming the first gate dielectric layer and the first gate electrode further includes, before the first trench in the cellular region: filling the first groove and the second groove with a conductive material layer, and etching back the conductive material layer in the first groove to reduce the height of the conductive material layer in the first groove so as to form a shielding electrode; and then, forming the first gate dielectric layer and the first gate electrode in a space of the first trench higher than the shielding electrode.

Optionally, the preparation method further comprises: forming a first well region and a second well region, wherein the first well region is formed in the substrate of the cell region, and the second well region is formed in the substrate of the rectifying region; and forming a first source region and a second source region in the first well region and the second well region, respectively.

Optionally, the preparation method further comprises: an inversion doped region is formed within a substrate of the rectifying region, the inversion doped region having a conductivity type opposite to a conductivity type of the substrate.

The present invention also provides a semiconductor integrated circuit including: a substrate defining a first region and a second region; a semiconductor device as described above, wherein a first transistor device of the semiconductor device is disposed in a cell region of the first region, and a super barrier rectifier of the semiconductor device is disposed in a rectifying region of the first region; and a second transistor device disposed in the second region, the second transistor device including: a third gate dielectric layer and a third gate electrode formed on the top surface of the substrate. The second gate dielectric layer in the super barrier rectifier and the third gate dielectric layer in the second transistor device have the same thickness and are smaller than the first gate dielectric layer in the first transistor device.

Optionally, the semiconductor integrated circuit includes a BCD device disposed in the second region, the BCD device including the second transistor device.

The invention also provides a preparation method of the semiconductor integrated circuit, which comprises the following steps: providing a substrate, wherein the substrate is defined with a first area and a second area; forming a first transistor device in a cell region of the first region and forming a super barrier rectifier in a rectifying region of the first region by adopting the preparation method of the semiconductor device; and, the preparation method further comprises: forming a third gate dielectric layer and a third gate electrode on the top surface of the substrate in the second region, for forming a second transistor device; and forming the second gate dielectric layer in the rectifying region while preparing the third gate dielectric layer, wherein the thicknesses of the second gate dielectric layer and the third gate dielectric layer are smaller than the thickness of the first gate dielectric layer.

Optionally, the second gate electrode is formed in the rectifying region at the same time as the third gate electrode is prepared.

Optionally, the semiconductor integrated circuit includes a BCD device formed in the second region, the BCD device including the second transistor device.

In the semiconductor device provided by the invention, the first transistor device is arranged in the cell region, the super barrier rectifying region is formed in the rectifying region, wherein the gate structure (comprising the first gate dielectric layer and the first gate electrode) of the first transistor device is formed in the first groove, and the gate structure (comprising the second gate dielectric layer and the second gate electrode) of the super barrier rectifier is formed on the top surface of the substrate, so that the gate structure of the super barrier rectifier positioned on the top surface of the substrate can be prepared more flexibly, and the simplification of the process is facilitated.

Furthermore, the grid structure of the super barrier rectifier and the preparation process of the planar grid structure of other devices can be combined with each other. For example, for a semiconductor integrated circuit further integrated with a BCD device, the gate dielectric layer of the CMOS transistor and the gate dielectric layer of the superbarrier rectifier may be prepared simultaneously according to the thickness requirement of the gate dielectric layer of the CMOS transistor in the BCD device. That is, based on the structural characteristics of the super barrier rectifier in the disclosure, the gate structure of the super barrier rectifier can be parasitically formed by using the preparation process of the planar gate structure of other devices (such as BCD devices) which are integrally arranged, so that the preparation process of the integrated circuit is greatly simplified, and the preparation cost is effectively reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. It is apparent that the drawings in the following description are only some embodiments of the invention.

Fig. 1 to 5 are schematic structural views of a semiconductor device during the fabrication process thereof.

Fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

Fig. 7 is a schematic view of another structure of a semiconductor device according to an embodiment of the present invention.

Fig. 8 is a schematic view of another structure of a semiconductor device according to an embodiment of the present invention.

Fig. 9 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the invention.

Fig. 10 to 16 are schematic structural views of a semiconductor device according to an embodiment of the present invention during a fabrication process.

Fig. 17 is a schematic diagram of a semiconductor integrated circuit according to an embodiment of the invention.

Fig. 18 is a flow chart illustrating a method for manufacturing a semiconductor integrated circuit according to an embodiment of the invention.

Fig. 19-22 are schematic diagrams illustrating a semiconductor integrated circuit according to an embodiment of the present invention during a manufacturing process.

Wherein, the reference numerals are as follows: 10/100-substrate; 10A/100A-cell region; 10B/100B-rectifying section; 20A/200A-first trenches; 20B/200B-second trenches; a layer of 21-dielectric material; a layer of 22-conductive material; 210-a layer of field dielectric material; 220-conductive material; 210A-a first field dielectric layer; 220B-a second field dielectric layer; 22A/22B/220A-shielding electrode; 220B-a layer of conductive material; 23A/230A-a first gate dielectric layer; 23B/230B-a second gate dielectric layer; 24A/240A-first gate electrode; 24B/240B-second gate electrode; 250A-a first well region; 250B-a second well region; 260A-a first source region; 260B-a second source region; 270-an inversion doped region; 310-a third gate dielectric layer; 320-a third gate electrode; 330-a third source/drain region; 340-third well region.

Detailed Description

As described in the background art, in the prior art, when the super barrier rectifier is integrally arranged in the semiconductor device, the manufacturing process is complicated and the cost is high. For example, referring to fig. 1-5, a schematic diagram of a super barrier rectifier integrated in an SGT device during fabrication is shown in fig. 1-5.

Referring first to fig. 1, a substrate 10 is provided, and a first trench 20A is formed in a cell region 10A of the substrate 10, and a second trench 20B is formed in a rectifying region 10B of the substrate 10, the first trench 20A being for accommodating a gate structure of an SGT device, the second trench 20B being for accommodating a gate structure of a superbarrier rectifier.

Next, as shown in fig. 2, a dielectric material layer 21 and a conductive material layer 22 are formed in each trench.

Next, referring to fig. 3, an etch back process is performed to reduce the height of the conductive material layer 22 in each trench, thereby forming a shield electrode 22A/22B at the bottom of each trench, after which each trench may be filled with a second dielectric material layer.

With continued reference to fig. 3, a photolithography process is performed to form a first mask layer (not shown) covering the rectifying region 10B and exposing the cell region 10A, so that the second dielectric material layer in the cell region 10A may be etched to form a gate separation layer, and then a first gate dielectric layer 23A of a first thickness is formed on the trench sidewalls exposed by the first trench 20A.

Next, referring to fig. 4, a photolithography process is performed to form a second mask layer (not shown) covering the cell region 10A and exposing the rectifying region 10B, and the second dielectric material layer in the rectifying region 10B is etched to form an inter-gate separation layer, and then a second gate dielectric layer 23B of a second thickness is formed on the trench sidewall exposed by the second trench 20B, wherein the second thickness of the second gate dielectric layer 23B is smaller than the first thickness of the first gate dielectric layer 23A.

Referring to fig. 5, a first gate electrode 24A and a second gate electrode 24B are formed in the first trench 20A of the cell region 10A and the second trench 20B of the rectifying region 10B, respectively.

In the above preparation process, when the first gate dielectric layer 23A and the second gate dielectric layer 23B with different thicknesses are prepared, the trench regions of the cell region 10A and the trench regions of the rectifying region 10B need to be alternately covered, so that the exposed trench regions are sequentially processed, which makes the process more complicated. And, when a photoresist is formed to block the first trench by performing a photolithography process, the photoresist may be formed in the first trench, thereby also easily causing a problem that the photoresist remains in the trench when the photoresist is removed.

To this end, the present invention provides a novel semiconductor device integrated with a superbarrier rectifier, the semiconductor device comprising a first transistor device and a superbarrier rectifier integrated on a substrate. Wherein a first transistor device is disposed in a cellular region of a substrate, the first transistor device comprising: a first trench formed in the substrate; and the first gate dielectric layer and the first gate electrode are formed in the first groove. And a super barrier rectifier formed in the rectifying region of the substrate, the super barrier rectifier comprising: and the second gate dielectric layer and the second gate electrode are formed on the top surface of the substrate, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer.

That is, in the semiconductor device provided by the invention, the gate structure of the super-barrier rectifier is different from the gate structure of the first transistor device, the gate structure of the first transistor device is arranged in the groove of the substrate, and the gate structure of the super-barrier rectifier is arranged on the top surface of the substrate, so that the gate structure of the super-barrier rectifier can be prepared more flexibly, and the simplification of the process is facilitated.

The semiconductor device and the method for manufacturing the same according to the present invention are described in further detail below with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It will be appreciated that relative terms such as "above," "below," "top," "bottom," "above," and "below" as illustrated in the figures may be used to describe various element relationships to one another. These relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element, for example, will now be below the element.

Fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, and the semiconductor device includes a first transistor device and a super-barrier rectifier integrally disposed on a substrate 100 as shown in fig. 6. Specifically, the substrate 100 defines a cell region 100A and a rectifying region 100B, the first transistor device is disposed in the cell region 100A of the substrate 100, and the super barrier rectifier is formed in the rectifying region 100B of the substrate 100. In this embodiment, a case where the first transistor device includes a shielded gate field effect transistor (SGT device) will be described as an example.

Referring specifically to fig. 6, the first transistor device includes: a first trench 200A formed in the substrate of the cell region 100A, a first gate dielectric layer 230A and a first gate electrode 240A formed in the first trench 200A. In a specific example, the first transistor device includes a shielded gate field effect transistor (SGT device), in which a first field dielectric layer 210A and a shielding electrode 220A are further formed in the first trench 200A, the first field dielectric layer 210A is formed on the trench inner wall of the lower portion of the first trench 200A, and the shielding electrode 220A is filled in the lower portion space of the first trench 200A; and a first gate dielectric layer 230A is formed on the trench inner wall of the upper portion of the first trench 200A, a first gate electrode 240A is formed in the upper portion space of the first trench 200A to be located above the shielding electrode 220A, and an isolation layer is further provided between the shielding electrode 220A and the first gate electrode 240A to isolate the shielding electrode 220A and the first gate electrode 240A from each other.

And, the super barrier rectifier includes: a second gate dielectric layer 230B and a second gate electrode 240B formed on the top surface of the substrate of rectifying region 100B, wherein the thickness of the second gate dielectric layer 230B of the superbarrier rectifier is less than the thickness of the first gate dielectric layer 230A of the first transistor device. Therefore, when the first transistor device is turned off, the super barrier rectifier can still be turned on under lower voltage to serve as a current discharge channel, trailing current of the device or peak current brought by turn-off moment is reduced, quick turn-off of the device is realized, and reliability and switching frequency of the device are improved. In a specific example, the thickness of the first gate dielectric layer 230A in the first transistor device may be, for example, 300A or more, and the thickness of the second gate dielectric layer 230B in the super barrier rectifier may be, for example, 180A or less.

It should be noted that, the super barrier rectifier in the present disclosure is a planar gate structure (including the second gate dielectric layer 230B and the second gate electrode 240B), which is different from the trench gate structure (including the first gate dielectric layer 230A and the first gate electrode 240A) of the first transistor device, so that the gate structure of the super barrier rectifier can be more flexibly manufactured, which is beneficial to simplifying the process, reducing the manufacturing difficulty of the device, and increasing the process window.

With continued reference to fig. 6, the first transistor device further includes: the first well region 250A and the first source region 260A are formed in the substrate at the side of the first trench 200A, and the first well region 250A extends to a deeper position of the substrate with respect to the first source region 260A such that the first gate electrode 240A and the first well region 250A have a portion overlapping each other. Specifically, when the on voltage is applied to the first gate electrode 240A, a conductive channel along the height direction may be formed inversely in a portion of the first well region 250A extending downward with respect to the first source region 260A.

And, the super barrier rectifier further includes: the second well region 250B and the second source region 260B are formed in the substrate at the side of the second gate electrode 240B and extend to below the second gate electrode 240B in the direction of the second gate electrode, and the second well region 250B extends to a larger size below the second gate electrode 240B with respect to the second source region 260B so that the second gate electrode 240B and the second well region 250B have portions overlapping each other. When the super barrier rectifier is in the on state, the second well region 250B may be inverted in a portion extending laterally with respect to the second source region 260B to form a conductive channel along the width direction.

In an example, a dimension L2 of a portion where the second gate electrode 240B and the second well region 250B overlap each other may also be made smaller than a dimension L1 of a portion where the first gate electrode 240A and the first well region 250A overlap each other in the height direction, that is, L2+.l 1. Specifically, the width dimension L2 of the portion where the second gate electrode 240B and the second well region 250B overlap each other is the length dimension of the conductive channel of the super-barrier rectifier, and the height dimension L1 of the portion where the first gate electrode 240A and the first well region 250A overlap each other is the length dimension of the conductive channel of the first transistor device, so that the on-voltage of the super-barrier rectifier is further ensured to be lower than the on-voltage of the first transistor device by making the length dimension of the conductive channel of the super-barrier rectifier be less than or equal to the length dimension of the conductive channel of the first transistor device. It should be appreciated that when the length dimension of the conduction channel of the superbarrier rectifier is equal to the length dimension of the conduction channel of the first transistor device (i.e., l2=l1), then the superbarrier rectifier can be enabled to turn on at a lower voltage relative to the first transistor device due to the smaller thickness of the second gate dielectric layer 230B of the superbarrier rectifier; when the length dimension of the conducting channel of the super-barrier rectifier is smaller than the length dimension of the conducting channel of the first transistor device (i.e., L2 < L1), the on-voltage of the super-barrier rectifier is further reduced based on the smaller thickness of the second gate dielectric layer 230B of the super-barrier rectifier.

With continued reference to fig. 6, a second trench 200B is further formed in the rectifying region 100B, the second trench 200B being disposed on a side of the second gate electrode 240B facing away from the second source region 260B, and a conductive material layer 220B being formed in the second trench 200B, thereby being capable of being used to form a field plate structure, and being beneficial to improving a reverse breakdown voltage of the device. Further, a second field dielectric layer 210B is further formed on the inner wall of the second trench 200B, and a conductive material layer 220B is formed on the second field dielectric layer 210B.

The depth of the second trench 200B in the rectifying region 100B may be identical to the depth of the first trench 200A in the cell region 100A, and both may be formed simultaneously in the same process step. And, the first field dielectric layer 210A in the first trench 200A and the second field dielectric layer 210B in the second trench 200B may be simultaneously prepared to have the same thickness, specifically, the thicknesses of the first field dielectric layer 210A and the second field dielectric layer 210B may be correspondingly adjusted according to the voltage-resistant performance of the device, which is not particularly limited herein, and when the device needs to achieve a higher voltage-resistant performance, the first field dielectric layer 210A and the second field dielectric layer 210B with larger thicknesses may be formed.

In a specific example, at least two rectifying units may be disposed within the same rectifying section 100B, so that at least two current bleed channels may be formed. Further, when the second trench 200B filled with the conductive material layer 220B is formed in the rectifying region 100B, the second trench 200B may be disposed between adjacent rectifying units, for example, as shown in fig. 6, the second gate electrode 240B, the second source region 260B and the second well region 250B are formed on opposite sides of the second trench 200B.

Further, the substrate 100 may have a first conductivity type. Wherein, in the cellular region 100A, the first well region 250A has the second conductivity type, the first source region 260A has the first conductivity type, and both the first well region 250A and the first source region 260A are extended inward from the top surface of the substrate 100 to a predetermined depth, at which time the portion of the substrate located under the first well region 250A may constitute a drift region of the first transistor device having the first conductivity type. And, in the rectifying region 100B, the second well region 250B has the second conductivity type, the second source region 260B has the first conductivity type, and both the second well region 250B and the second source region 260B extend inward from the top surface of the substrate 100, where the portion of the substrate outside the second well region 250B may constitute a drift region of the super barrier rectifier having the first conductivity type. After the first transistor device is turned off, carriers of the first conductivity type injected into the drift region in the cell region 100A cannot be timely extracted in the cell region 100A, and at this time, the super-barrier rectifier is in an on state, so that the carriers of the first conductivity type can be rapidly extracted through a current discharge channel formed in the rectifying region 100B, trailing current of the device or peak current brought by turn-off moment is reduced, and reliability and switching frequency of the device are improved.

For example, the semiconductor device may include a plurality of cell regions 100A, the plurality of cell regions 100A being disposed within a device region, and a rectifying region 100B may be disposed between a portion of adjacent cell regions 100A within the device region; and/or, a rectifying region 100B is provided at the edge of the device region. For example, one example of disposing rectifying section 100B between adjacent ones of cell sections 100A in the plurality of cell sections 100A is illustrated in fig. 6.

In the alternative, and with particular reference to fig. 7, an inversion doped region 270 may also be provided within the substrate of rectifying region 100B, the inversion doped region 270 having a conductivity type opposite to that of substrate 100. Specifically, the inversion doped region 270 may be disposed on the current drain path of the super barrier rectifier, for example, the inversion doped region 270 may be disposed below the second well region 250B.

As described above, the substrate 100 has the first conductivity type, and the inversion doped region 270 has the second conductivity type, that is, the inversion doped region 270 of the second conductivity type is formed in the drift region of the first conductivity type, and in an example, the drift region may be an N-type drift region, and the inversion doped region 270 is a P-type doped region. After the first transistor device is turned off, the first conductive type carriers injected into the drift region in the cell region 100A may be rapidly extracted through the current bleed channel formed in the rectifying region 100B, and meanwhile, the first conductive type carriers (for example, N-type ions) in the drift region may be further recombined in the second conductive type inversion doped region 270 (for example, P-type doped region), so as to accelerate the extraction speed of the first conductive type carriers, further reduce the turn-off time of the first transistor device, improve the turn-off loss of the device, and improve the reliability and switching frequency of the device.

In the examples of fig. 6 and 7, the second trench 200B is provided in the rectifying region 100B, however, other examples may not provide the second trench 200B, as long as the voltage withstanding requirement of the device can be satisfied. For example, in the example of fig. 8, at least one second gate electrode 240B is formed in the rectifying region 100B, and the second gate electrode 240B may constitute a gate electrode shared by two rectifying units on both sides thereof, and thus, a second well region 250B and a second source region 260B are formed on both sides of the second gate electrode 240B, whereby two rectifying units may be constituted by the second gate electrode 240B and the second well region 250B and the second source region 260B on both sides, and the two rectifying units share one second gate electrode 240B.

Based on the semiconductor device as described above, the present disclosure also provides a method of manufacturing the semiconductor device as described above. Referring specifically to fig. 9, the method for manufacturing the semiconductor device includes the following steps.

In step S110, a substrate is provided, where a cellular region and a rectifying region are defined on the substrate.

Step S120, etching the substrate to form a first trench at least in the substrate of the cellular region.

In step S130, a first gate dielectric layer and a first gate electrode are formed in the first trench of the cellular region.

And step S140, forming a second gate dielectric layer and a second gate electrode on the top surface of the substrate of the rectifying region, wherein the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer.

One preparation method in this example is described in detail below with reference to fig. 10 to 16. In this embodiment, a shielded gate field effect transistor is formed in a cell region.

In step S110, referring specifically to fig. 10, a substrate 100 is provided, and the substrate 100 defines a cellular region 100A and a rectifying region 100B. Wherein the cell region 100A is used to further form a first transistor device (e.g., a shielded gate field effect transistor SGT); and, rectifying region 100B is used to further form super barrier rectifier SBR.

In a specific example, the substrate 100 may include a base (not shown) of the second conductivity type and an epitaxial layer (not shown) of the first conductivity type formed on the base, for example, the substrate 100 includes a P-type base and an N-type epitaxial layer. Wherein the epitaxial material within the cell region 100A and the rectifying region 100B may constitute a drift region of the corresponding device.

In step S120, with continued reference to fig. 10, the substrate 100 is etched to form a first trench 200A at least within the substrate 100 of the cellular region 100A.

In an alternative example, the second trench 200B may be formed in the rectifying region 100B at the same time as etching the substrate 100 to form the first trench 200A. That is, the first trench 200A and the second trench 200B may be simultaneously prepared and formed in the same step, so that the first trench 200A and the second trench 200B may have the same or similar trench depth.

In a subsequent process, a first gate dielectric layer and a first gate electrode may be formed in the first trench 200A to further fabricate a first transistor device. In this embodiment, a first field dielectric layer, a shielding electrode, a first gate dielectric layer and a first gate electrode may be formed in the first trench 200A, so as to further prepare a shielded gate field effect transistor. And forming a second field dielectric layer and a conductive material layer in the second trench 200B for constituting a field plate structure of a Super Barrier Rectifier (SBR).

In a specific example, referring to fig. 11-12, before forming the first gate dielectric layer and the first gate electrode of the first transistor device, the method further includes: a first field dielectric layer 210A and a shield electrode 220A are formed within the first trench 200A. The preparation processes of the first field dielectric layer 210A and the shielding electrode 220A may be respectively integrated with the preparation processes of the second field dielectric layer 210B and the conductive material layer 220B. For example, referring first to fig. 11, a field dielectric material layer 210 is formed on both the inner wall of the first trench 200A and the inner wall of the second trench 200B; next, the first trench 200A and the second trench 200B are filled with a conductive material 220; referring to fig. 12, the rectifying region 100B may be covered, and the conductive material 220 in the first trench 200A in the cell region 100A may be etched back to reduce the height of the conductive material in the first trench 200A, thereby forming a shielding electrode 220A; and etching the field dielectric material layer 210 in the first trench 200A, and reserving the field dielectric material layer at the lower part of the first trench 200A to form a first field dielectric layer 210A; thereafter, an isolation layer may be formed on the shielding electrode 220A for isolating the shielding electrode 220A and a gate electrode formed later from each other. Wherein the field dielectric material layer and the conductive material within the second trench 200B are preserved for constituting the second field dielectric layer 210B and the conductive material layer 220B in the field plate structure.

Thereafter, step S130 may be continued, and specifically, referring to fig. 12 and 13, a first gate dielectric layer 230A and a first gate electrode 240A are formed in the cellular region 100A. As shown in fig. 12, a first gate dielectric layer 230A is formed on the trench sidewalls of the first trench 200A higher than the shield electrode 220A. The first gate dielectric layer 230A may be formed by an oxidation process, and the thickness of the first gate dielectric layer 230A may be, for example, 300A or more. Next, as shown in fig. 13, a first gate electrode 240A is formed in the first trench 200A, and the first gate electrode 240A is correspondingly located above the shield electrode 220A.

In the alternative, and with specific reference to fig. 14, an ion implantation process may also be used to form an inversion doped region 270 within the rectifying region 100B, the inversion doped region 270 having a conductivity type opposite to that of the substrate 100. For example, the substrate 100 may have an N-type material layer, and the counter doped region 270 may be a P-type doped region.

Next, step S140 is performed, and specifically referring to fig. 15, a second gate dielectric layer 230B and a second gate electrode 240B are formed on the top surface of the substrate of the rectifying region 100B, wherein the thickness of the second gate dielectric layer 230B is smaller than the thickness of the first gate dielectric layer 230A. For example, the second gate dielectric layer 230B in the superbarrier rectifier may have a thickness of 180 a or less.

In a specific example, at least two rectifying units may be formed within the same rectifying region 100B. In the case where the second trench 200B is formed in the rectifying region 100B, the second gate dielectric layer 230B and the second gate electrode 240B stacked on both sides of the second trench 200B may be formed to form rectifying units on both sides of the second trench 200B. And, in the case where the second trench 200B is not provided in the rectifying region 100B, the second gate dielectric layer 230B and the second gate electrode 240B may be utilized as a gate structure shared by adjacent rectifying units.

It should be noted that, based on the fact that the gate structure of the super-barrier rectifier is a planar gate structure, a well region may be formed in the rectifying region 100B and the cell region 100A by preferably using an ion implantation process before the gate structure of the super-barrier rectifier is formed. Referring specifically to fig. 15, a first well region 250A is formed in the cellular region 100A, and a second well region 250B is formed in the rectifying region 100B. Wherein the first well regions 250A are formed between adjacent first trenches 200A and laterally extend to the trench sidewalls of the corresponding first trenches 200A; and, the second well region 250B may be disposed to be spaced apart from the second trench 200B, and in preparing the second gate electrode 240B, the second gate electrode 240B is formed between the second well region 250B and the second trench 200B such that the second gate electrode 240B partially covers the second well region 250B.

Further, referring to fig. 16, the method further includes: a first source region 260A is formed in the first well region 250A and a second source region 260B is formed in the second well region 250B. Wherein the first source region 260A extends inwardly into the first well region 250A from the top of the first well region 250A, i.e., the first well region 250A has a portion extending downward with respect to the first source region 260A, and a dimension L1 of the portion of the first well region 250A extending downward in the height direction corresponds to a length dimension of the conductive channel of the first transistor device. And, the second source region 260B extends inward from the top of the second well region 250B while the second source region 260B also extends laterally toward the second gate electrode 240B to below the second gate electrode 240B without exceeding the area extent of the second well region 250B, i.e., the second well region 250B has a portion extending laterally with respect to the second source region 260B, the dimension L2 of the portion of the second well region 250B extending laterally in the width direction, i.e., the length dimension corresponding to the conduction channel of the superbarrier rectifier. The dimension L2 of the portion of the second well region 250B extending laterally with respect to the second source region 260B in the width direction may be smaller than or equal to the dimension L1 of the portion of the first well region 250A extending downward with respect to the first source region 260A in the height direction, that is, L2 is smaller than or equal to L1.

It should be noted that, since the gate structure of the super-barrier rectifier is formed on the top surface of the substrate, and the gate structure of the first transistor device is preferentially formed in the first trench 200A before the gate structure of the super-barrier rectifier is prepared, the problem that photoresist is easily remained in the first trench 200A when the gate structure of the super-barrier rectifier is prepared is effectively avoided.

For example, as shown in fig. 3 and fig. 4, a photoresist (not shown) is required to be formed in the prior art to cover the first trench 20A, so that a second gate dielectric layer 23B with a smaller thickness can be formed in the second trench 20B, and then the photoresist is removed, where the photoresist filled in the first trench 20A is easy to remain in the first trench, thereby affecting the performance of the finally formed first transistor device. However, in the present embodiment, when the gate structure of the super barrier rectifier is fabricated, the gate structure of the first transistor device is already formed in the first trench 200A, so that the risk of photoresist remaining in the first trench 200A is effectively reduced.

The present disclosure also provides a semiconductor integrated circuit including the semiconductor device described above therein. Referring specifically to fig. 17, the semiconductor integrated circuit includes: a substrate 100; and a first transistor device, a super barrier rectifier, and a second transistor device formed on the substrate 100.

The substrate 100 defines a first region 110 and a second region 120, and the first region 110 may further include a cell region 100A and a rectifying region 100B. A first transistor device is formed within the cell region 100A of the first region 110, the first transistor device comprising: a first trench 200A formed in the substrate, and a first gate dielectric layer 230A and a first gate electrode 240A formed in the first trench 200A. A super barrier rectifier is formed in the rectifying region 100B of the first region 110, the super barrier rectifier comprising: a second gate dielectric layer 230B and a second gate electrode 240B formed on the top surface of the substrate. And, a second transistor device is formed in the second region 120, the second transistor device comprising: a third gate dielectric layer 310 and a third gate electrode 320 formed on the top surface of the substrate.

In one example, the first transistor device may include a shielded gate field effect transistor (SGT device). And, BCD devices may be formed in the second region 120 of the substrate 100, and may include bipolar transistors, CMOS transistors, and DMOS transistors, only one of which is illustrated in fig. 17 (the second transistor device is, for example, a CMOS transistor).

Further, the second gate dielectric layer 230B in the rectifying region 100B and the third gate dielectric layer 310 in the second region 120 have the same thickness and are each smaller than the thickness of the first gate dielectric layer 230A in the first transistor device. In a specific example, the second gate dielectric layer 230B and the third gate dielectric layer 310 may be simultaneously prepared in the same process step. And, the third gate electrode 320 in the second region 120 may also be prepared simultaneously with the second gate electrode 240B in the rectifying region 100B.

The present disclosure also provides a method of manufacturing a semiconductor integrated circuit, the method comprising: providing a substrate, wherein the substrate is defined with a first area and a second area; the semiconductor device is formed by the method, and specifically comprises the steps of forming a first transistor device in a cell region of a first region and forming a super barrier rectifier in a rectifying region of the first region. And, the preparation method further comprises: a third gate dielectric layer and a third gate electrode are formed on the top surface of the substrate in the second region for forming a second transistor device. The third gate dielectric layer in the second region and the second gate dielectric layer in the rectifying region are prepared simultaneously in the same process step, that is, the second gate dielectric layer is formed in the rectifying region while the third gate dielectric layer is formed in the third region, and the thicknesses of the second gate dielectric layer and the third gate dielectric layer are smaller than the thickness of the first gate dielectric layer. Therefore, the performance requirements of all devices can be met, and meanwhile, the process is simplified.

In one example, BCD devices are formed in a second region of the substrate, with the second transistor devices described above forming part of the BCD devices. Specifically, the BCD device may include bipolar transistors, CMOS transistors, and DMOS transistors, and the second transistor device may be formed, for example, as a CMOS transistor in the BCD device.

And the first transistor device within the cell region may be a power device, including, for example, a shielded gate field effect transistor (SGT device). In practical application, for example, according to the thickness requirement of the gate dielectric layer of the CMOS tube in the BCD device, a second gate dielectric layer of the super barrier rectifier is formed in the rectifying region, and a third gate dielectric layer of the CMOS tube is formed in the second region.

In order to more clearly explain the method of manufacturing the semiconductor integrated circuit in this embodiment, a specific example will be described below with reference to fig. 18 and fig. 19 to 22. Fig. 8 is a schematic flow chart of a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, and fig. 19 to 22 are schematic structural diagrams of the semiconductor integrated circuit according to an embodiment of the present invention during the manufacturing process, and the method for manufacturing the semiconductor integrated circuit may include the following steps.

First, step S210 is performed, and referring specifically to fig. 19, a substrate 100 is provided, and a first region 110 and a second region 120 are defined on the substrate 100, where the first region 110 further has a cell region 100A and a rectifying region 100B.

Next, step S220 is performed, and as shown in fig. 19, a first trench 200A and a first gate dielectric layer 230A and a first gate electrode 240A located in the first trench 200A are formed in the cellular region 100A, for forming a gate structure of the first transistor device.

In a specific example, the second trench 200B and the conductive material layer located in the second trench 200B are further formed in the rectifying region 100B, so as to form a field plate structure of the super barrier rectifier. The first trench 200A in the cell region 100A and the second trench 200B in the rectifying region 100B may be formed simultaneously in the same etching step.

In this embodiment, taking the first transistor device as an example of the shielded gate field effect transistor, after the first trench 200A is formed, the method further includes; forming a first field dielectric layer 210A and a shield electrode 220A in a lower space of the first trench 200A; next, a first gate dielectric layer 230A and a first gate electrode 240A are formed in an upper space of the first trench 200A.

Further, the fabrication process of the field plate structure corresponding to the first trench 200A may be integrated with the fabrication process of the first transistor device, for example, including: after etching the substrate 100 to form the first trench 200A and the second trench 200B, simultaneously forming a field dielectric material layer of a sufficient thickness on the inner walls of the first trench 200A and the second trench 200B, and filling the first trench 200A and the second trench 200B with a conductive material; next, the rectifying region 100B is covered, and the conductive material in the first trench 200A is etched back to form a shielding electrode 220A, and the field dielectric material layer in the first trench 200A is etched to form a first field dielectric layer 210A; thereafter, a first gate dielectric layer 230A and a first gate electrode 240A are formed in an upper space of the first trench 200A. Thus, a gate structure of the first transistor device may be formed in the cell region 100A, and a field plate structure may be formed in the rectifying region 100B using the field dielectric material layer and the conductive material remaining in the second trench 200B.

In an alternative, with continued reference to fig. 19, the method further includes: an inversion doped region 270 is formed within rectifying region 100B, the inversion doped region 270 having a conductivity type opposite to the conductivity type of the substrate region in which it is located. For example, the substrate 100 may have an N-type material layer (e.g., an N-type epitaxial layer), and the inversion doped region 270 may be a P-type doped region.

Next, step S230 is performed, specifically referring to fig. 20, to perform a first ion implantation process to simultaneously form a first well region 250A in the substrate of the cellular region 100A of the first region 110 and a second well region 250B in the substrate of the rectifying region 100B; and performing a second ion implantation process to form a third well region 340 within the substrate of the second region 120.

That is, the first well region 250A and the second well region 250B within the first region 110 may also be simultaneously formed using the same ion implantation process (first ion implantation process). And, the third well region 340 within the second region 120 may be used, for example, to form a well region of a CMOS device. It should be appreciated that the order of the first ion implantation process and the second ion implantation process is not limited, and the first ion implantation process may be preferentially performed, or the second ion implantation process may be preferentially performed.

Next, step S240 is performed, specifically referring to fig. 21, in which a second gate dielectric layer 230B is formed on the top surface of the substrate of the rectifying region 100B and a third gate dielectric layer 310 is formed on the top surface of the substrate of the second region 120 by using the same gate dielectric material layer; and forming a second gate electrode 240B on the substrate top surface of the rectifying region 100B and a third gate electrode 320 on the substrate top surface of the second region 120 using the same gate conductive material layer.

Specifically, a gate dielectric material layer and a gate conductive material layer may be sequentially formed on the top surface of the substrate 100; thereafter, the gate conductive material layer and the gate dielectric material layer are patterned to form a second gate dielectric layer 230B and a second gate electrode 240B stacked on the substrate top surface of the rectifying region 100B, and a third gate dielectric layer 310 and a third gate electrode 320 stacked on the substrate top surface of the second region 120.

Next, step S250 is performed, specifically referring to fig. 22, a third ion implantation process is performed to simultaneously form a first source region 260A in the first well region 250A and a second source region 260B in the second well region 250B; and, performing a fourth ion implantation process to form third source/drain regions 330 in the third well regions 340 of the second region 120.

That is, the first source region 260A in the cell region 100A and the second source region 260B in the rectifying region 100B may also be simultaneously formed by the same ion implantation process (third ion implantation process). And, the third source/drain region 330 within the second region 120 may be used, for example, to constitute a source/drain region of a CMOS device, which is specifically formed on both sides of the third gate electrode. It should be appreciated that the order of the third ion implantation process and the fourth ion implantation process is not limited, and the third ion implantation process may be preferentially performed, or the fourth ion implantation process may be preferentially performed.

In the method for manufacturing a semiconductor integrated circuit as described above, a field plate structure located in the rectifying region may be parasitically formed in the process of manufacturing the gate structure of the first transistor device in the cell region 100A; in the process of preparing the gate structure of the second transistor device in the BCD device, a gate structure located in the rectifying region is parasitically formed. That is, the super barrier rectifier can be formed parasitically by utilizing the preparation process of the first transistor device and the preparation process of the second transistor device, so that the preparation process of the integrated circuit is greatly simplified, and the preparation cost is effectively reduced.

It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. And, while the present invention has been disclosed in terms of preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

It should be further appreciated that the terms "first," "second," "third," and the like in the description are used merely for distinguishing between various components, elements, steps, etc. in the description and not for indicating a logical or sequential relationship between various components, elements, steps, etc., unless otherwise indicated. It should also be understood that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses.

Claims

1. A semiconductor device, comprising:

A substrate defining a cellular region and a rectifying region;

A first transistor device formed in the cellular region, the first transistor device comprising: a first trench formed in the substrate; a first gate dielectric layer and a first gate electrode formed in the first trench; a first well region and a first source region formed in the substrate at a side of the first trench, the first well region extending to a deeper position of the substrate with respect to the first source region such that the first gate electrode and the first well region have a portion overlapping each other; and

A super barrier rectifier formed in the rectifying region, the super barrier rectifier comprising: a second gate dielectric layer and a second gate electrode formed on the top surface of the substrate, wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; and a second well region and a second source region formed in the substrate at the side of the second gate electrode, and each of the second well region and the second source region extends to below the second gate electrode in the direction of the second gate electrode, the second well region extending to a larger size below the second gate electrode with respect to the second source region so that the second gate electrode and the second well region have a portion overlapping each other.

2. The semiconductor device of claim 1, wherein the first transistor device comprises a shielded gate field effect transistor, a shield electrode further formed within the first trench, the shield electrode being located below the first gate electrode.

3. The semiconductor device according to claim 1, wherein a dimension of a portion of the second gate electrode and the second well region overlapping each other in a width direction is equal to or smaller than a dimension of a portion of the first gate electrode and the first well region overlapping each other in a height direction.

4. The semiconductor device according to claim 1, wherein a second trench is further formed in the rectifying region, the second trench being formed on a side of the second gate electrode facing away from the second source region, and a conductive material layer being formed in the second trench.

5. The semiconductor device according to claim 4, wherein at least two rectifying units are provided in the same rectifying region, and the second trench is provided between adjacent rectifying units.

6. The semiconductor device according to claim 1, wherein at least two rectifying units are provided in the same rectifying region, and at least one second gate electrode is formed in the rectifying region, the second gate electrode constituting a gate electrode common to the two rectifying units on both sides thereof.

7. The semiconductor device according to claim 1, wherein the semiconductor device has a device region including a plurality of cell regions, the rectifying region being provided between a part of adjacent cell regions within the device region; and/or the rectifying region is arranged at the edge of the device region.

8. The semiconductor device according to any one of claims 1 to 7, wherein an inversion doped region having a conductivity type opposite to that of the substrate is further formed in the substrate of the rectifying region.

9. A method of manufacturing a semiconductor device, comprising:

Providing a substrate, wherein the substrate is defined with a cellular region and a rectifying region;

etching the substrate to form a first groove at least in the substrate of the cell area;

forming a first gate dielectric layer and a first gate electrode in a first trench of the cellular region for forming a first transistor device; and

Forming a second gate dielectric layer and a second gate electrode on the top surface of the substrate of the rectifying region for forming a super barrier rectifier, wherein the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer;

the preparation method further comprises the following steps: forming a first well region and a second well region, wherein the first well region is formed in the cell region and is positioned in the substrate at the side edge of the first groove, and the second well region is formed in the rectifying region and is positioned in the substrate at the side edge of the second gate electrode; and forming a first source region and a second source region, the first source region being formed in the first well region and having a portion extending to a deeper position of the substrate relative to the first source region, the second source region being formed in the second well region and having a portion extending in a direction toward the second gate electrode relative to the second source region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the method for manufacturing further comprises:

Forming a second trench in the substrate of the rectifying region while etching the substrate to form the first trench; and filling a conductive material layer in the second groove.

11. The method of manufacturing a semiconductor device of claim 10, wherein forming a first gate dielectric layer and a first gate electrode prior to forming in the first trench of the cell region further comprises: filling the first groove and the second groove with a conductive material layer, and etching back the conductive material layer in the first groove to reduce the height of the conductive material layer in the first groove so as to form a shielding electrode;

And then, forming the first gate dielectric layer and the first gate electrode in a space of the first trench higher than the shielding electrode.

12. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, further comprising: an inversion doped region is formed within a substrate of the rectifying region, the inversion doped region having a conductivity type opposite to a conductivity type of the substrate.

13. A semiconductor integrated circuit, comprising:

A substrate defining a first region and a second region;

a semiconductor device as claimed in any one of claims 1 to 8, wherein a first transistor device of the semiconductor device is disposed within a cell region of the first region, and wherein a superbarrier rectifier of the semiconductor device is disposed within a rectifying region of the first region; and

A second transistor device disposed in the second region, the second transistor device comprising: a third gate dielectric layer and a third gate electrode formed on the top surface of the substrate;

the second gate dielectric layer in the super barrier rectifier and the third gate dielectric layer in the second transistor device have the same thickness and are smaller than the first gate dielectric layer in the first transistor device.

14. The semiconductor integrated circuit of claim 13, wherein the semiconductor integrated circuit comprises a BCD device disposed within the second region, the BCD device comprising the second transistor device.

15. A method for manufacturing a semiconductor integrated circuit, comprising:

providing a substrate, wherein the substrate is defined with a first area and a second area;

Forming a first transistor device in a cell region of the first region and forming a super barrier rectifier in a rectifying region of the first region using the method of manufacturing a semiconductor device as claimed in any one of claims 9 to 12; and

The preparation method further comprises the following steps: forming a third gate dielectric layer and a third gate electrode on the top surface of the substrate in the second region, for forming a second transistor device; and forming the second gate dielectric layer in the rectifying region while preparing the third gate dielectric layer, wherein the thicknesses of the second gate dielectric layer and the third gate dielectric layer are smaller than the thickness of the first gate dielectric layer.

16. The method for manufacturing a semiconductor integrated circuit according to claim 15, wherein the second gate electrode is formed in the rectifying region at the same time as the third gate electrode.

17. The method of manufacturing a semiconductor integrated circuit according to claim 15, wherein the semiconductor integrated circuit includes a BCD device formed in the second region, the BCD device including the second transistor device.