JPH05283701A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with which no damage is given to a semiconductor region when it is formed on a insulating film of the semiconductor device to be double-doped using an electrode body and a mask body as a mask after the electrode side face on the insulating film has been protected by a special mask body formed by RIE. CONSTITUTION:The title manufacturing method consists of a mask-forming process in which a mask body 10, covering the side face of an electrode body 7, is formed by ion-etching on the side face of the electrode body 7 on the insulating film 81 of a semiconductor substrate 1, a double diffusion region forming process in which double diffusion regions 4 and 5 are formed on the substrate 1 by double-doping impurities using the electrode body 7 and the mask body 10 as a mask, and a semiconductor region forming process in which semiconductor regions of prescribed shape are formed on the prescribed region of an insulating film 82 after the mask body 10 has been formed. As a result, the damage caused on semiconductor regions 11 and 12 can be prevented by RIE without having substantial extension of process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrode body and a semiconductor region on an insulating film.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 62-22
Japanese Patent No. 9866 discloses a power semiconductor device in which a plurality of vertical channel double-diffused insulated gate transistors (DMOS) are integrated, in which a polysilicon region is formed on an insulating film and the polysilicon region is used for temperature detection. Forming a junction diode of Japanese Patent Application Laid-Open No. 2-288366 filed by the applicant of the present invention discloses a power semiconductor device in which a plurality of DMOSs are integrated, in which a polysilicon region is formed on an insulating film and the polysilicon region is used for high voltage protection. It discloses forming a Zener diode.

As described above, in this type of power semiconductor device, it is known that semiconductor elements such as diodes are integrated on an insulating film to protect the device. In these diodes, a polysilicon film is usually deposited on a field oxide film, and the polysilicon film is photo-etched to form a polysilicon region having a predetermined shape. Usually, a thin oxide film is formed to protect the surface of the polysilicon region. Then, in a subsequent step, the polysilicon region is generally doped for junction formation. The steps up to the formation of the polysilicon region are performed before the gate insulating film and the gate electrode of the DMOS are formed in order to reduce damage to the surface of the substrate and shorten the steps, and thereafter, the surface of the substrate for the DMOS is formed. Is usually cleaned by thermal oxidation, oxide film etching, etc., and then the gate electrode forming step is usually performed.

[0004]

The applicant of the present invention is DM
In a vertical semiconductor device such as an OS, a special mask body is formed by reactive ion etching (RIE) on a side surface of an electrode body such as a gate electrode formed on a semiconductor substrate with an insulating film interposed therebetween. Also, there is proposed a power semiconductor device which is effective in reducing the withstand voltage and the on-resistance by double-doping the well region and the source region on the surface portion of the semiconductor substrate using the mask body as a mask (Japanese Patent Application No. Hei 2-264701).
However, when RIE is performed after forming such a gate electrode in order to integrate the above-mentioned diode in the device using the mask body, the RIE etches back the polysilicon region or roughens the surface. Has occurred. Although it is possible to form a thick protective mask pattern on the polysilicon region, the steps of forming, patterning, removing, etc., and contamination by these steps pose a problem.

The present invention has been made in view of the above problems. After the side surfaces of the electrode body on the insulating film are protected by a special mask body formed by RIE, the electrode body and the mask body are used as a mask for double doping. It is an object of the present invention to provide a semiconductor device capable of avoiding damage to the semiconductor region when forming the semiconductor region on the insulating film of the semiconductor device.

[0006]

A method of manufacturing a semiconductor device according to the present invention comprises an electrode body forming step of forming an insulating film on a semiconductor substrate and an electrode body on the insulating film, and the substrate and the electrode body. A mask body forming step of forming an insulating film for the side wall on the insulating film, forming a mask body covering the side surface of the electrode body by reactive ion etching the insulating film for the side wall, and using the electrode body and the mask body as a mask Double-diffusion region forming step of forming a double-diffusion region by double-doping impurities on the surface of the substrate, and a semiconductor forming a predetermined-shape semiconductor region on a predetermined region of the insulating film after forming the mask body. And a region forming step.

[0007]

As described above, in the semiconductor device of the present invention, the side surface of the electrode body on the insulating film is protected by a special mask body formed by RIE, and then double doping is performed using the electrode body and the mask body as a mask. In forming the semiconductor region on the insulating film of the semiconductor device, the semiconductor region is formed after the mask body is formed. Therefore, the semiconductor region is prevented from being damaged by RIE without a significant process extension, and the semiconductor region is formed in the semiconductor region. It is possible to prevent the characteristics of the semiconductor element from deteriorating.

[0008]

1 is a sectional view showing an embodiment of the present invention.
Shown in. In this semiconductor device, 1 is an N ⁺ silicon substrate (semiconductor substrate), 2 is an N ⁻ epitaxial layer, 31 is a deep P ⁻ well region, 32 is a P ⁻ well region for relaxing an electric field, 4 is a P ⁻ channel well region, 5 is N of DMOS
⁺ Source region, 6 is a P ⁺ contact region, 7 is a gate electrode made of doped polysilicon (electrode body in the present invention), 81 is a gate insulating film made of a silicon oxide film, 8
2 is a thick silicon oxide film (field oxide film), 83 is a silicon oxide film for protecting the upper surface of the gate electrode 7, and 84 is B.
An interlayer insulating film made of a silicon oxide film such as PSG, 91 to 95 are electrode portions made of aluminum, 10 is a mask body for covering the side surface of the gate electrode made of a silicon oxide film, 11
Is a polysilicon region for the polysilicon resistor (semiconductor region in the present invention), and 12 is a polysilicon region for the Zener diode (semiconductor region in the present invention).

The N ⁺ source region 5 is formed on the surface of the P ⁻ well region 31 together with the P ⁻ channel well region 4 by double ion implantation from the opening 13 defined by the mask body 10 as described later. .. P ^- well region 32
Are formed simultaneously with the deep P ^- well region 31. In this embodiment, a large number of DMOS cells are arranged on a chip, each cell has a large number of channel well regions 4 each having a substantially square planar shape, and a gate having a lattice pattern having substantially square openings above the channel well regions 4. An electrode 7 and a mask body 10 that covers the side surface of the gate electrode 7 are formed.

The manufacturing process of the above device will be described below with reference to FIGS.
Will be described in detail. First, as shown in FIG.
N of 0.01 Ω · cm or less⁺Prepare the silicon substrate 1,
1x10 on it¹⁶Atom / cm³N^-Epitaxial
Form layer 2 to a thickness of 7 to 15 μm. Then N^-D
Silicon oxide film as a mask on the epitaxial layer 2
(Not shown) about 7000 angstrom
It Next, deep P^-To form the well regions 31 and 32
The silicon oxide film is photo-etched to
3 to 5 x 10¹³b under the conditions of dose / cm square and 60 keV
Inject on. Next, drive-in (1170 ℃, 4 ~
5 hours, N₂) And do a deep P ^-Well regions 31, 32
To form.

Next, the silicon oxide film is removed, and thereafter a thick silicon oxide film (field oxide film) 82 having a thickness of about 9000 angstrom is formed, and the other portions are removed except the P ^- well region 32. , Then about 300
A gate insulating film 81 of about 1000 Å is formed by a thermal oxidation method. Next, 300 by LPCVD method.
A polysilicon film having a thickness of 0 to 5000 angstroms and being subjected to phosphorus diffusion is formed, the surface is oxidized to form a thin silicon oxide film (not shown), and then a silicon oxide film having a thickness of about 1 μm is formed thereon. Is deposited by the CVD method,
The polysilicon film and the silicon oxide film are photo-etched to form the gate electrode 7 and the silicon oxide film 83 covering the upper surface of the gate electrode 7. Next, the gate electrode 7
A thin silicon oxide film (not shown) is formed on the side surface of the substrate by oxidation.

Next, as shown in FIG. 3, a CVD silicon oxide film 15 of TEOS having a good step coverage is formed on the entire surface.
It is formed in a thickness of about μm. Next, as shown in FIG. 4, the CVD silicon oxide film 15 is etched back by reactive ion etching to form a mask body 10 of the CVD silicon oxide film 15 on the side surface of the gate electrode 7. The width Lm at the lowermost portion of the mask body 10 is the film thickness of the gate electrode 7 and the silicon oxide film 83 thereon, that is, the silicon oxide film 83 after etching back from the surface of the epi layer 2.
Is determined by the distance to the upper surface of the film and the TEOS film thickness before etchback.

Next, as shown in FIG. 5, a thin silicon oxide film 19 is formed on the exposed surface of the epi layer 2 by oxidation, and a low-concentration polysilicon film (not shown) having a thickness of about 3000 to 5000 angstrom is formed thereon. No.) is formed and the polysilicon film is photo-etched to form polysilicon regions 11 and 12 on the field insulating film 82. Next, the surfaces of the polysilicon regions 11 and 12 are thermally oxidized to form thin silicon oxide films 11a and 11b.

Next, as shown in FIG. 1, a silicon oxide film 1 is formed.
Boron is penetrated through 9, 11a, and 11b to form 6 × 10 ^{13 to} 9 boron.
Ion implantation is performed under the conditions of × 10 ¹³ dose / cm square and 40 keV, and further drive-in is performed at 1170 ° C. for about 100 minutes to form a shallow P ⁻ channel well region 4 on the surface of the epitaxial layer 2. Next, using a resist mask patterned by photolithography,
3~5 × 10 ¹⁵ dose / cm square, P in the conditions of 100 keV ^-
Phosphorus is ion-implanted into the surface of the channel well region 4 and the right half of the polysilicon region 12, and the P ⁻ well region 4 is formed.
Of the N ⁺ source region 5 is formed on the surface, to form the N ⁺ polysilicon region 12a. Next, the mask is removed and 5
Boron is ion-implanted under the conditions of ˜7 × 10 ¹³ dose / cm 2 and 40 keV to form a P ⁺ region 6 for well contact at the center of the surface of the well region 4, and to form a polysilicon region 11
As a P ⁺ resistance line, and P in the left half of the polysilicon region 12.
⁺ Polysilicon region 12b is formed. As a result, the polysilicon region 12 becomes a polycrystalline Zener diode.

Next, annealing is performed in an N ₂ atmosphere to produce N _2.
^{The +} source region 5, the P ⁺ contact region 6 and the polysilicon regions 11 and 12 are activated. The end of the N ⁺ region 5 on the side of the gate electrode is defined by the end position of the mask body 10 regardless of the shape of the resist mask, and as a result, the DMOS channel length under the gate electrode is the same as the above two ion implantations. Is determined by the difference in the lateral spread of.

Next, an interlayer insulating film 84 made of, for example, BPSG is deposited on the entire surface by CVD, and a predetermined region of the interlayer insulating film 84 is removed by a photolithography process to form a contact opening. Next, the electrode portions 91 to 95 made of aluminum are formed. A drain electrode (not shown) of the DMOS is also formed on the back surface of the substrate 1. As a result, a semiconductor device having a P ⁺ polysilicon resistance and a Zener diode on the field insulating film 82 together with a large number of vertical DMOS power transistors is completed.

Here, the width Lm of the mask body 10 is 0.85 times or less the depth of the N ⁺ source region 5 in FIG. In other words, published in February 1980, "IEEE
Transactions on Electron Devices "VOL.ED-2"
7, NO. 2, P.I. As described in 356-367, since the lateral diffusion distance of the ion-implanted region is approximately 0.85 times the vertical diffusion distance, Lm is 0.85 of the depth of the N ⁺ source region 5. If it is set to be equal to or less than twice, the tip of the N ⁺ source region 5 reaches directly under the gate electrode 7. Also, P
^- the tip of the channel well region 4 further enters just below the gate electrode 7 from the front end of the N ⁺ source region 5.

The features of the DMOS in which the side surface of the gate electrode is covered with the mask body 10 formed by RIE will be described below. In this DMOS, since the lateral diffusion of the double-doped impurity ions starts from the outer end of the mask body 10, various conditions are required as compared with the conventional case where the lateral diffusion starts from the end of the gate electrode. If it is the same, the lateral dimension of the DMOS cell is reduced by the width Lm of the mask body, the DMOS integration degree is increased, and the ON resistance can be reduced.

Further, in this embodiment, Al
If the distance between the electrode gate and the electrode is the same, the distance from the end of the contact surface between the aluminum electrode and the N ⁺ source region 5 to the boundary between the N ⁺ source region 5 and the P ⁻ channel well region decreases. The resistance is reduced by the amount corresponding to the reduction in the distance of the N ⁺ source region 5. Further, in this embodiment, the mask body 10 is
Since the lateral width of the N ^- epi layer immediately below the gate electrode 7, that is, the lateral width of the vertical channel portion formed there, is increased by twice the width Lm, the JFET resistance loss at this portion can be reduced.

Furthermore, in this embodiment, it is possible to reduce the gate / source capacitance which was difficult to reduce in the conventional structure. That is, in this embodiment, the gate electrode 7 is formed by the width Lm of the mask body 10.
And the source region 5 are reduced in overlap, and accordingly, the gate / source capacitance, that is, the input capacitance of the device is reduced, and the excellent effect that this DMOS can be driven at high speed by an element having a small current driving capability can be obtained. It is also advantageous for ensuring the breakdown voltage between the gate and the source.

The operation of this device will be described below. The electrode portion 91 is grounded, and the substrate 1 is connected to a positive potential power source through a back electrode portion (not shown) and a load. When a positive common control voltage is applied to the gate electrode 7, the source region 5 is electrically connected to the N ⁺ substrate 1 through the N-type channel on the surface of the well region 4.
The well region 4 is biased to the same potential as the source region 5.

The polysilicon region 11 serves as a resistance line, and the polysilicon region 12 serves as a Zener diode.
Although integrated with the MOS, these are not formed on the surface of the epitaxial layer 2 and therefore are not affected by the DMOS potential fluctuation. In this embodiment, the polysilicon regions 11 and 12 are formed by RIE of the mask body 10.
Since it is performed after the above, the polysilicon regions 11 and 1
It is possible to avoid the problem that 2 is etched back by RIE and damaged.

In the above embodiment, the polysilicon region 1 is used.
Although the doping process for 1 and 12 is shared with the doping process for DMOS, it is natural that they can be performed independently of each other. In the above embodiment, the DMOS is used as the power element, but the IG
Of course, it can be changed to BT or the like. Further, it goes without saying that laser annealing of the polysilicon regions 11 and 12 and formation of MOS transistors in the polysilicon regions 11 and 12 are possible.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention,

2 is a sectional view showing a manufacturing process of the device of FIG.

3 is a sectional view showing a manufacturing process of the device of FIG.

4 is a sectional view showing a manufacturing process of the device of FIG.

5 is a cross-sectional view showing a manufacturing process of the device of FIG. 1,

[Explanation of symbols]

1 is an N ⁺ silicon substrate (semiconductor substrate), 2 is an N ⁻ epitaxial layer, 31 and 32 are P ⁻ well regions 4, P ⁻ channel well regions, 5 are N ⁺ source regions, and 7 is a gate electrode (referred to in the present invention). Electrode body), 81 is a gate insulating film, 82 is a silicon oxide film (field insulating film), 10 is a mask body, 1
Reference numerals 1 and 12 are polysilicon regions (semiconductor regions in the present invention).

Claims (1)

[Claims] 1. An electrode body forming step of forming an insulating film on a semiconductor substrate and forming an electrode body on the insulating film; and forming a sidewall insulating film on the substrate and the electrode body to form the sidewall insulating film. A mask body forming step of forming a mask body covering the side surface of the electrode body by reactive ion etching the film; and dope the surface of the substrate doubly with impurities by using the electrode body and the mask body as a mask. A semiconductor device comprising: a double diffusion region forming step of forming a heavy diffusion region; and a semiconductor region forming step of forming a semiconductor region having a predetermined shape on a predetermined region of the insulating film after forming the mask body. Production method.