CN109903713B - Display compensation circuit and display compensation method - Google Patents
Display compensation circuit and display compensation method Download PDFInfo
- Publication number
- CN109903713B CN109903713B CN201910166303.3A CN201910166303A CN109903713B CN 109903713 B CN109903713 B CN 109903713B CN 201910166303 A CN201910166303 A CN 201910166303A CN 109903713 B CN109903713 B CN 109903713B
- Authority
- CN
- China
- Prior art keywords
- display compensation
- circuit
- pulse width
- width modulation
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a display compensation circuit and a display compensation method.A time schedule controller reads display compensation parameters stored in a memory, a pulse width modulation circuit carries out display compensation according to the display compensation parameters, and an anti-interference circuit triggers the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters; when the factory calibration and screening are carried out, the display compensation circuit controls the display compensation circuit by sending different commands under different working states, and the display compensation circuit directly controls the switch of the GOA signal of the pulse width modulation circuit, so that the interference signal is recovered when the signal reading is finished, the GOA signal is closed when the reset signal is restarted, and the technical problem that the existing display compensation circuit is interfered when the signal reading communication is carried out is solved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display compensation circuit and a display compensation method.
Background
When factory calibration and screening are performed, as shown in fig. 1, the display compensation circuit performs read-write operation on data in the display area through read signal communication, the display compensation circuit needs to be restarted once after the read-write operation is performed once, and when the restart is performed through a reset signal, the pulse width modulation circuit outputs a GOA signal before the data is read and written by the timing controller, so that the communication of the SPI signal is disturbed, the read signal communication is abnormal, and the timing controller cannot accurately read and write the data.
Namely, the prior display compensation circuit has the technical problem that the read signal is interfered.
Disclosure of Invention
The invention provides a display compensation circuit and a display compensation method, which aim to solve the technical problem that a read signal is interfered in the conventional display compensation circuit.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the embodiment of the invention provides a display compensation circuit, which comprises a time schedule controller, a pulse width modulation circuit and an anti-jamming circuit, wherein the time schedule controller is used for reading display compensation parameters stored in a memory, the pulse width modulation circuit is used for performing display compensation according to the display compensation parameters, the anti-jamming circuit is used for triggering the pulse width modulation circuit to stop working in the display compensation circuit provided by the invention when the time schedule controller reads the display compensation parameters, and the anti-jamming circuit is also used for triggering the pulse width modulation circuit to start working after the time schedule controller finishes reading the display parameters.
In the display compensation circuit provided by the invention, the anti-jamming circuit is used for receiving a completion signal from the time schedule controller and determining that the time schedule controller completes reading of the display compensation parameters when the completion signal is received.
In the display compensation circuit provided by the invention, the anti-jamming circuit comprises a microprocessor in the pulse width modulation chip.
In the display compensation circuit provided by the invention, the anti-interference circuit is used for detecting a reset signal of the time schedule controller and determining that the time schedule controller starts to read the display compensation parameters when the reset signal is detected.
The embodiment of the invention provides a display compensation method which comprises the steps that a time schedule controller reads display compensation parameters stored in a memory, a pulse width modulation circuit carries out display compensation according to the display compensation parameters, and an anti-interference circuit triggers the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters.
In the display compensation method provided by the invention, the anti-interference circuit triggers the pulse width modulation circuit to start working after the time schedule controller finishes reading the display parameters.
The display compensation method provided by the invention further comprises the steps that the anti-interference circuit receives a completion signal from the time schedule controller, and when the completion signal is received, the time schedule controller is determined to complete the reading of the display compensation parameters.
In the display compensation method provided by the invention, the anti-interference circuit triggers the pulse width modulation circuit to stop working when the microprocessor in the pulse width modulation chip reads the display compensation parameters through the time schedule controller.
The display compensation method provided by the invention further comprises the steps that the anti-interference circuit detects a reset signal of the time schedule controller, and when the reset signal is detected, the time schedule controller is determined to start to read the display compensation parameters.
The invention has the beneficial effects that: the invention provides a display compensation circuit and a display compensation method, wherein the display compensation circuit comprises a time schedule controller, a pulse width modulation circuit and an anti-interference circuit, the time schedule controller is used for reading display compensation parameters stored in a memory, the pulse width modulation circuit is used for performing display compensation according to the display compensation parameters, and the anti-interference circuit is used for triggering the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters; when the factory calibration and screening are carried out, the display compensation circuit controls the display compensation circuit by sending different commands under different working states, and the display compensation circuit directly controls the switch of the GOA signal of the pulse width modulation circuit, so that the interference signal is recovered when the signal reading is finished, the GOA signal is closed when the reset signal is restarted, and the technical problem that the existing display compensation circuit is interfered when the signal reading communication is carried out is solved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a circuit diagram of a conventional display compensation circuit.
Fig. 2 is a circuit diagram of a display compensation circuit according to an embodiment of the invention.
Fig. 3 is a flowchart of a display compensation method according to an embodiment of the present invention.
Fig. 4 is a circuit diagram of a display device according to an embodiment of the invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Aiming at the technical problem that the read signal communication of the existing display compensation circuit is interfered, the embodiment of the invention can solve the problem.
As shown in fig. 2, the display compensation circuit 2 provided by the present invention includes a timing controller 201, a pulse width modulation circuit 202, and an anti-jamming circuit 203, wherein:
the timing controller 201 is configured to read a display compensation parameter stored in the memory;
the pulse width modulation circuit 202 is configured to perform display compensation according to the display compensation parameter;
the anti-jamming circuit 203 is configured to trigger the pulse width modulation circuit 22 to stop working when the timing controller 201 reads the display compensation parameter.
In this embodiment, the display compensation circuit includes a timing controller, a pulse width modulation circuit, and an anti-jamming circuit, where the timing controller is configured to read a display compensation parameter stored in a memory, the pulse width modulation circuit is configured to perform display compensation according to the display compensation parameter, and the anti-jamming circuit is configured to trigger the pulse width modulation circuit to stop working when the timing controller reads the display compensation parameter; when the factory calibration and screening are carried out, the display compensation circuit controls the display compensation circuit by sending different commands under different working states, and the display compensation circuit directly controls the switch of the GOA signal of the pulse width modulation circuit, so that the interference signal is recovered when the signal reading is finished, the GOA signal is closed when the reset signal is restarted, and the technical problem that the existing display compensation circuit is interfered when the signal reading communication is carried out is solved.
In an embodiment, the immunity circuit 203 is further configured to trigger the pulse width modulation circuit 202 to start operating after the timing controller 201 completes reading the display parameter.
In this embodiment, after the timing controller finishes data reading, the pulse width modulation circuit starts to operate under the control of the anti-jamming circuit, the pulse width modulation circuit plays a role of a driving circuit here, and when data reading starts next time, the pulse width modulation circuit is closed under the control of the anti-jamming circuit. And after the next data reading is finished, the whole circuit circularly works in the way through the control recovery of the anti-interference circuit.
In one embodiment, the immunity circuit 203 is configured to receive a completion signal from the timing controller 201, and determine that the timing controller 201 completes reading the display compensation parameter when the completion signal is received.
In this embodiment, the timing controller controls the anti-jamming circuit to operate by the completion signal.
In one embodiment, the immunity circuitry 203 includes a microprocessor within the pulse width modulation chip.
In one embodiment, the immunity circuit 203 is configured to detect a reset signal of the timing controller 201, and determine that the timing controller 201 starts to read the display compensation parameter when the reset signal is detected.
In this embodiment, the reset signal indicates that the whole circuit will perform the next data reading, and after the reset signal is detected, when the anti-jamming circuit detects that the timing controller starts to read the display compensation data, the anti-jamming circuit needs to control the pulse width modulation circuit to stop working at this time in order to prevent the GOA signal of the pulse width modulation circuit from interfering with the SPI read signal.
In one embodiment, as shown in fig. 3, the display compensation method provided by the present invention comprises the following steps:
step S301: the time schedule controller reads the display compensation parameters stored in the memory;
step S302: the pulse width modulation circuit carries out display compensation according to the display compensation parameter;
step S303: and the anti-interference circuit triggers the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters.
The display compensation method provided by the embodiment comprises the steps that a time sequence controller reads display compensation parameters stored in a memory; the pulse width modulation circuit carries out display compensation according to the display compensation parameter; the anti-interference circuit triggers the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters; when the factory calibration and screening are carried out, the display compensation circuit controls the display compensation circuit by sending different commands under different working states, and the display compensation circuit directly controls the switch of the GOA signal of the pulse width modulation circuit, so that the interference signal is recovered when the signal reading is finished, the GOA signal is closed when the reset signal is restarted, and the technical problem that the existing display compensation circuit is interfered when the signal reading communication is carried out is solved.
In an embodiment, the method shown in fig. 3 further includes triggering the pulse width modulation circuit to start operating after the timing controller finishes reading the display parameter.
In one embodiment, the method of fig. 3 further includes the interference rejection circuit receiving a completion signal from the timing controller and determining that the timing controller completes reading the display compensation parameter when the completion signal is received.
In one embodiment, the method shown in fig. 3 further includes the step of triggering the pwm circuit to stop operating when the timing controller reads the display compensation parameter through a microprocessor in the pwm chip.
In one embodiment, the method of fig. 3 further includes the interference rejection circuit detecting a reset signal of the timing controller and determining that the timing controller starts to read the display compensation parameter when the reset signal is detected.
The invention will now be further illustrated with reference to specific examples.
As shown in fig. 1, when a Demura (optical compensation) function is debugged, a Tcon (timing controller 101) on a main control board CB communicates through an SPI (serial peripheral interface), so that a memory Flash on a printed circuit board XB integrated with an active drive integrated circuit (S-IC) is read and written, data reading is performed after each Demura operation is performed by restarting, and restarting is performed through a Reset function built in the Tcon. When Tcon starts Reset when Demura is done, PWM (pulse width modulation circuit 102) outputs GOA signal before Tcon downloads data, which interferes SPI communication, for example, SPI signal should normally be WP of 3.3V, and is interfered and deformed by CK signal, resulting in SPI signal distortion, at this time SPI communication is abnormal, resulting in Tcon not being able to download Demura data on XB.
In order to avoid that the output of the PWM after the Tcon performs Reset affects the normal communication of the SPI, an anti-interference mechanism is introduced in this embodiment, in order to ensure that the three-in-one PWM stops outputting immediately after the Tcon starts the Reset, and after the Reset is completed, the Tcon communicates Demura data on the download XB through the SPI, and then the PWM resumes working.
In one embodiment, as shown in fig. 4, the display device provided by the present invention includes a main control board CB41, a printed circuit board XB42 and a display panel 43, the main control board CB41 is connected to the printed circuit board XB42 through a connector 44, and the printed circuit board XB42 is directly connected to the display panel 43 through a connection terminal; wherein the content of the first and second substances,
the main control board CB41 is configured to read a display compensation parameter stored in the printed circuit board XB42, control the printed circuit board XB42 to perform display compensation on the display panel 43 according to the display compensation parameter, and stop controlling the printed circuit board XB42 to perform display compensation on the display panel 43 according to the display compensation parameter when the display compensation parameter is read;
the printed circuit board XB42 is used for storing the display compensation parameter and performing display compensation of the display panel 43 according to the display compensation parameter;
the display panel 43 is driven by the printed circuit board XB42 to operate.
In one embodiment, as shown in fig. 4, a memory 421 and a driving circuit COF422 (including a gate driving integrated circuit G-IC and a source driving integrated circuit S-IC) are disposed on the printed circuit board XB42, wherein the memory 421 is used for storing the display compensation parameter, and the driving circuit COF422 is used for performing the display compensation of the display panel 43 according to the display compensation parameter.
In one embodiment, as shown in fig. 4, the main control board CB41 is provided with a timing controller Tcon411, a pulse width modulation circuit PWM412 and an interference rejection circuit MCU413, wherein:
the time sequence controller Tcon411 is used for reading display compensation parameters stored in a memory;
the pulse width modulation circuit PWM412 is used for carrying out display compensation according to the display compensation parameter;
the anti-jamming circuit MCU413 is configured to trigger the pulse width modulation circuit 412 to stop working when the timing controller 411 reads the display compensation parameter.
In this embodiment, the MCU is used to implement real-time monitoring of Reset (Reset) signals of Tcon, the Reset signals will be pulled up in the normal operating state of the system, and the Reset signals will be pulled down after the Tcon starts the Reset function; this anti-jamming mechanism is divided into two states: when the MCU monitors that the Reset signal is at a low level, the MCU immediately sends an OFF command to the PWM, and the PWM stops outputting; then the Tcon normally downloads the effective data of the Flash on the XB through SPI communication; and when the Tcon reads the effective data, sending an instruction to the MCU, immediately sending an ON instruction to the PWM by the MCU, and recovering signal output by the PWM to perform display compensation. The embodiment changes the existing Tcon and PWM parallel working mode into a serial working mode, and can effectively avoid the interference of the SPI communication by PWM signals when the Tcon starts the Reset function.
In one embodiment, the immunity circuit MCU413 is a microcontroller MCU within the pulse width modulation circuit PWM 412.
In an embodiment, the anti-jamming circuit MCU413 is further configured to trigger the pulse width modulation circuit PWM412 to start to operate after the timing controller Tcon411 finishes reading the display parameter.
In this embodiment, after the timing controller finishes data reading, the pulse width modulation circuit starts to operate under the control of the anti-jamming circuit, the pulse width modulation circuit plays a role of a driving circuit here, and when data reading starts next time, the pulse width modulation circuit is closed under the control of the anti-jamming circuit. And after the next data reading is finished, the whole circuit circularly works in the way through the control recovery of the anti-interference circuit.
In an embodiment, the immunity circuit MCU413 is configured to receive a completion signal from the timing controller Tcon411, and determine that the timing controller Tcon411 completes reading the display compensation parameter when receiving the completion signal.
In this embodiment, the timing controller controls the anti-jamming circuit to operate by the completion signal.
In one embodiment, the immunity circuit MCU413 is configured to detect a reset signal of the timing controller Tcon411, and determine that the timing controller Tcon411 starts to read a display compensation parameter when the reset signal is detected.
In this embodiment, the reset signal indicates that the whole circuit will perform the next data reading, and after the reset signal is detected, when the anti-jamming circuit detects that the timing controller starts to read the display compensation data, the anti-jamming circuit needs to control the pulse width modulation circuit to stop working at this time in order to prevent the GOA signal of the pulse width modulation circuit from interfering with the SPI read signal.
According to the above embodiments:
the invention provides a display compensation circuit and a display compensation method, wherein the display compensation circuit comprises a time schedule controller, a pulse width modulation circuit and an anti-interference circuit, the time schedule controller is used for reading display compensation parameters stored in a memory, the pulse width modulation circuit is used for performing display compensation according to the display compensation parameters, and the anti-interference circuit is used for triggering the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters; when the factory calibration and screening are carried out, the display compensation circuit controls the display compensation circuit by sending different commands under different working states, and the display compensation circuit directly controls the switch of the GOA signal of the pulse width modulation circuit, so that the interference signal is recovered when the signal reading is finished, the GOA signal is closed when the reset signal is restarted, and the technical problem that the existing display compensation circuit is interfered when the signal reading communication is carried out is solved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A display compensation circuit, comprising:
the time sequence controller is used for reading the display compensation parameters stored in the memory;
the pulse width modulation circuit is used for carrying out display compensation according to the display compensation parameters;
and the anti-interference circuit is used for triggering the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters.
2. The display compensation circuit of claim 1, wherein the immunity circuit is further configured to trigger the pulse width modulation circuit to start operating after the timing controller completes reading the display compensation parameter.
3. The display compensation circuit of claim 1, wherein the immunity circuit is configured to receive a completion signal from the timing controller and to determine that the timing controller completes reading the display compensation parameter upon receiving the completion signal.
4. The display compensation circuit of claim 1, wherein the immunity circuit comprises a microprocessor within a pulse width modulation chip.
5. The display compensation circuit of claim 1, wherein the immunity circuit is configured to detect a reset signal from the timing controller and determine that the timing controller is to begin reading the display compensation parameter when the reset signal is detected.
6. A display compensation method, comprising:
the time schedule controller reads the display compensation parameters stored in the memory;
the pulse width modulation circuit carries out display compensation according to the display compensation parameter;
and the anti-interference circuit triggers the pulse width modulation circuit to stop working when the time schedule controller reads the display compensation parameters.
7. The display compensation method of claim 6, further comprising triggering the pulse width modulation circuit to start operating after the timing controller completes reading the display compensation parameter.
8. The display compensation method of claim 6, further comprising the immunity circuit receiving a completion signal from the timing controller and determining that the timing controller completes reading the display compensation parameter upon receiving the completion signal.
9. The display compensation method of claim 6, further comprising the step of triggering the pwm circuit to stop operating when the timing controller reads the display compensation parameter through a microprocessor in the pwm chip.
10. The display compensation method of claim 6, further comprising the interference rejection circuit detecting a reset signal of the timing controller and determining that the timing controller starts reading the display compensation parameters when the reset signal is detected.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910166303.3A CN109903713B (en) | 2019-03-06 | 2019-03-06 | Display compensation circuit and display compensation method |
| PCT/CN2019/085928 WO2020177212A1 (en) | 2019-03-06 | 2019-05-08 | Display compensation circuit and method, and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910166303.3A CN109903713B (en) | 2019-03-06 | 2019-03-06 | Display compensation circuit and display compensation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109903713A CN109903713A (en) | 2019-06-18 |
| CN109903713B true CN109903713B (en) | 2020-11-24 |
Family
ID=66946521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910166303.3A Active CN109903713B (en) | 2019-03-06 | 2019-03-06 | Display compensation circuit and display compensation method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109903713B (en) |
| WO (1) | WO2020177212A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110930920B (en) * | 2019-11-21 | 2022-07-12 | Tcl华星光电技术有限公司 | Display device and driving method thereof |
| CN110910848A (en) * | 2019-11-28 | 2020-03-24 | Tcl华星光电技术有限公司 | Driving circuit and driving method of liquid crystal display |
| CN110969979B (en) * | 2019-12-25 | 2021-09-03 | Tcl华星光电技术有限公司 | Driving circuit and driving method of display panel |
| US11120731B2 (en) | 2019-12-25 | 2021-09-14 | Tcl China Star Optoelectronics Technology Co., Ltd. | Driving circuit for display panel and method of driving same |
| CN111681585B (en) * | 2020-06-05 | 2023-10-13 | Tcl华星光电技术有限公司 | Driving circuit of display panel and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499824A (en) * | 2002-11-04 | 2004-05-26 | 李治福 | Method for raising quality of image on liquid crystal display device |
| KR20060060959A (en) * | 2004-12-01 | 2006-06-07 | 삼성에스디아이 주식회사 | Electron emission display apparatus having efficient driving apparatus |
| CN102354484A (en) * | 2011-09-20 | 2012-02-15 | 深圳市华星光电技术有限公司 | Light emitting diode (LED) dimming driving device, method and liquid crystal display |
| CN105427822A (en) * | 2015-12-29 | 2016-03-23 | 深圳市华星光电技术有限公司 | Gray-scale compensation data resetting device and method |
| CN106125367A (en) * | 2016-08-26 | 2016-11-16 | 深圳市华星光电技术有限公司 | A kind of method and device detecting Mura offset data exception |
| CN107045849A (en) * | 2017-02-20 | 2017-08-15 | 昆山龙腾光电有限公司 | Time sequence control device, method and display device |
| CN109147668A (en) * | 2018-09-25 | 2019-01-04 | 京东方科技集团股份有限公司 | External compensation method, driving unit and the display panel of display panel |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7246189B2 (en) * | 2005-11-18 | 2007-07-17 | Vetra Systems Corporation | Method and apparatus for enhancing universal serial bus |
| US9269305B2 (en) * | 2012-09-11 | 2016-02-23 | Apple Inc. | Reduced backlight turn on time |
| CN105700210B (en) * | 2016-04-29 | 2019-04-05 | 深圳市华星光电技术有限公司 | LCD display panel and its manufacturing method |
| CN106098017B (en) * | 2016-08-25 | 2019-02-22 | 深圳市华星光电技术有限公司 | A kind of driving method and driving device reducing electromagnetic interference |
| CN106847224A (en) * | 2017-04-06 | 2017-06-13 | 深圳市华星光电技术有限公司 | LCD data recording tool parallel method and system |
| CN107526979A (en) * | 2017-08-28 | 2017-12-29 | 惠科股份有限公司 | The guard method of software data and its system in display panel |
| CN108447452B (en) * | 2018-03-28 | 2020-03-27 | 惠科股份有限公司 | Display device and driving method thereof |
-
2019
- 2019-03-06 CN CN201910166303.3A patent/CN109903713B/en active Active
- 2019-05-08 WO PCT/CN2019/085928 patent/WO2020177212A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499824A (en) * | 2002-11-04 | 2004-05-26 | 李治福 | Method for raising quality of image on liquid crystal display device |
| KR20060060959A (en) * | 2004-12-01 | 2006-06-07 | 삼성에스디아이 주식회사 | Electron emission display apparatus having efficient driving apparatus |
| CN102354484A (en) * | 2011-09-20 | 2012-02-15 | 深圳市华星光电技术有限公司 | Light emitting diode (LED) dimming driving device, method and liquid crystal display |
| CN105427822A (en) * | 2015-12-29 | 2016-03-23 | 深圳市华星光电技术有限公司 | Gray-scale compensation data resetting device and method |
| CN106125367A (en) * | 2016-08-26 | 2016-11-16 | 深圳市华星光电技术有限公司 | A kind of method and device detecting Mura offset data exception |
| CN107045849A (en) * | 2017-02-20 | 2017-08-15 | 昆山龙腾光电有限公司 | Time sequence control device, method and display device |
| CN109147668A (en) * | 2018-09-25 | 2019-01-04 | 京东方科技集团股份有限公司 | External compensation method, driving unit and the display panel of display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109903713A (en) | 2019-06-18 |
| WO2020177212A1 (en) | 2020-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109903713B (en) | Display compensation circuit and display compensation method | |
| CN106874054B (en) | Method and system for on-line upgrading module program in repeater | |
| EP3308284A1 (en) | Test for 50 nanosecond spike filter | |
| JP2011254984A (en) | Game machine | |
| CN111028799B (en) | Driving circuit and driving method of display panel | |
| JP5208165B2 (en) | Game machine | |
| US6119610A (en) | Sewing machine controller | |
| US11289040B2 (en) | Driving circuit and driving method of liquid crystal display | |
| JP2014028170A (en) | Game machine | |
| CN111477154B (en) | Communication structure of display panel and display panel | |
| JP2011254985A (en) | Game machine | |
| CN108897248A (en) | A kind of self―tuning control and mobile robot | |
| CN112988465A (en) | Method for automatically recovering operation of single chip microcomputer in upgrading failure | |
| CN109801660A (en) | Read-write operation control method, memory and the display panel of display panel | |
| JP5599233B2 (en) | Game machine | |
| TW202127243A (en) | Display system and method of automatically adjusting display-panel parameters | |
| CN106569861B (en) | Chip IAP data updating control method and system | |
| CN106096702B (en) | Compensate the method and device postponed caused by the extended line of safe digital card | |
| CN109510524B (en) | Motor position information storage method and device | |
| CN111414272B (en) | Electronic device and reset method thereof | |
| CN113590153B (en) | Firmware upgrading method, system, equipment and medium of CPLD | |
| CN219800133U (en) | Device for preventing reset circuit from interrupting Boot programming | |
| EP4300320A1 (en) | Method for serial peripheral interface (spi) operating-mode synchronization between an spi host and an spi device, and spi bus synchronization apparatus | |
| JPH0855079A (en) | Iic external control circuit | |
| JPH10124348A (en) | Computer monitoring device and power window system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |