CN111681585B

CN111681585B - Driving circuit of display panel and display device

Info

Publication number: CN111681585B
Application number: CN202010503353.9A
Authority: CN
Inventors: 肖波
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2020-06-05
Filing date: 2020-06-05
Publication date: 2023-10-13
Anticipated expiration: 2040-06-05
Also published as: CN111681585A

Abstract

The application discloses a driving circuit of a display panel and a display device. According to the application, the memory is accessed to obtain Demura data when the enabling signal of the first level is received by adding the enabling signal and controlling the time sequence by the time sequence controller, and the GOA time sequence control signal is output to control the GOA signal output to the display panel to be output-free, so that the GOA signal is prevented from interfering with the transmission signal between the time sequence controller and the memory, and the reading stability of the Demura data in the memory read by the time sequence controller is improved.

Description

Driving circuit of display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a driving circuit of a display panel and a display device capable of improving the reading stability of Demura data required for debugging the display panel.

Background

In order to optimize the display effect of the display panel, a memory is placed on a Source side (Source) printed circuit board (Printed Circuit Board Assembly, PCBA for short) for storing compensation data of the display effect of the panel, demura data. The PCBA refers to a printed circuit board formed by the whole process that a PCB blank is subjected to SMT loading or DIP plug-in. The panel production line stores the debugged compensation data in a memory through online debugging. When power on, the Timing Controller (TCON) will call corresponding Demura data from the memory, and provide the demux data to the timing controller for integration and output to improve the display effect of the panel.

The timing controller reads Demura data from the memory through SPI (Serial Peripheral Interface ) transmission signals, and SPI communication is adopted between the timing controller and the memory. If the data in the memory is correctly called, the SPI transmission signal must be kept stable in the reading process, otherwise, if the external interference causes failure of SPI communication between the time sequence controller and the memory, the purpose of improving the display panel effect cannot be achieved.

Interference comes mainly from two aspects: 1) When the display panel works, a Source drive chip (Source IC) on the Source side PCBA charges the panel, so that the whole system has high power consumption and high power system noise; 2) The GOA (Gate Driver on Array, array substrate row driving) signal output to the panel by the Level Shifter (LS) is a square wave signal with high frequency and high voltage difference, and the internal layout (layout) wire of the PCBA itself may also cause interference to other signals (such as SPI transmission signals) due to parasitic capacitance.

In the prior art, the scheme for avoiding interference is to shorten the connecting wires, add shielding layers to the wires and reduce the interference of external debugging environment as much as possible. However, the existing solutions cannot avoid signal interference from the PCBA itself.

Therefore, how to improve the stability of Demura data required for debugging a display panel becomes a technical problem that the development of the existing display panel debugging technology needs improvement.

Disclosure of Invention

The application aims to provide a driving circuit of a display panel and a display device, which can avoid interference of GOA signals output to the panel on SPI transmission signals between a time sequence controller and a memory and improve the reading stability of Demura data required by display panel debugging.

In order to achieve the above object, the present application provides a driving circuit of a display panel, the driving circuit comprising: a memory for storing demra data for compensating for a display effect of the display panel; a level shifter for outputting GOA signals to the display panel; and a timing controller for accessing the memory to acquire the demux data in response to an enable signal, and outputting a GOA timing control signal to the level shifter to control the output of the GOA signal.

In order to achieve the above object, the present application also provides a display device including: a display panel; and a driving circuit, wherein the driving circuit adopts the driving circuit.

The application has the advantages that: according to the driving circuit of the display panel, the enabling signal is added and the time sequence is controlled by the time sequence controller, so that when the enabling signal of the first level is received, the memory is accessed to acquire Demura data, and meanwhile, the GOA time sequence control signal is output to control the GOA signal output to the display panel to be output nothing, so that the GOA signal output to the display panel by the level converter is avoided, SPI transmission signal quality between the time sequence controller and the memory is interfered, and the reading stability of Demura data in the memory read by the time sequence controller is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a driving circuit of a display panel according to the present application;

FIG. 2 is a driving timing diagram of a driving circuit of the display panel according to the present application;

fig. 3 is a schematic diagram of a display device according to the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar components or components having like or similar functions throughout. The terms first, second, third and the like in the description and in the claims and in the drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the objects so described may be interchanged where appropriate. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware circuits or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

According to the driving circuit of the display panel, the enabling signal is added and the time sequence is controlled by the time sequence controller, so that when the enabling signal of the first level is received, the memory is accessed to obtain Demura data, and meanwhile, the GOA time sequence control signal is output to control the GOA signal output to the display panel to be output nothing, so that the GOA signal output to the display panel by the level converter is avoided, and SPI transmission signal quality between the time sequence controller and the memory is interfered. In the debugging stage of the production line machine, when the memory is required to be accessed, the output time of the level converter can avoid the reading time of the Demura data in the memory read by the time sequence controller by controlling the time sequence controller, so that the interference of GOA signals on SPI transmission signal quality is avoided, and the reading stability of the Demura data in the memory read by the time sequence controller is improved.

Referring to fig. 1-2, fig. 1 is a block diagram of a driving circuit of a display panel according to the present application, and fig. 2 is a driving timing diagram of the driving circuit of the display panel according to the present application. The driving circuit 10 of the display panel of the present application includes: a memory 11, a level shifter 12 and a timing controller 13.

Specifically, the memory 11 is used for storing Demura data for compensating for the display effect of a display panel (not shown). After each time the display device is powered on (power on), the timing controller 13 first reads the Demura data in the memory 11, then performs processing compensation on the received data signal (for example, data to be displayed), and finally outputs the data signal to the display panel for display.

Due to limitations of crystallization process, when LTPS TFTs (low temperature polysilicon thin film transistors) are fabricated on a large area glass substrate, TFTs at different positions often have non-uniformity in electrical parameters such as threshold voltage, mobility, etc.; this non-uniformity translates into current and brightness differences in the display device and is perceived by the human eye, the Mura phenomenon.

In order to stabilize the display effect of the display panel, a compensation method is required, and there are two modes, i.e., internal compensation and external compensation. External compensation can be further classified into an optical decimation type and an electrical decimation type according to the difference of the data decimation method. The optical extraction method is to extract the brightness signal by an optical CCD photographing method after the back plate is lightened, namely the De-Mura technology. The optical extraction mode has the advantages of simple structure and flexible method, and is widely adopted at the present stage. Demura data generated by using the De-Mura technology is burned into a memory unit to process and compensate a received data signal (e.g., data to be displayed) in a subsequent data processing, thereby compensating a display effect of the display panel.

In a further embodiment, the memory 11 is a Flash memory (Flash). Since data stored in a Flash memory (Flash) can be saved even after power is turned off, demura data can be stored in an external memory Flash. In other embodiments, demura data may also be stored in EEPROM (Electrically Erasable Programmable read only memory, erasable memory).

Specifically, the level shifter 12 is configured to output a GOA (Gate Driver on Array, array substrate row driving) signal to the display panel. Specifically, the level shifter 12 is configured to output a GOA signal to a panel GOA area 18 of the display panel. The GOA signal is a square wave signal with high frequency and high voltage difference.

Specifically, the timing controller (TCON IC) 13 is configured to access the memory 11 to obtain the Demura data in response to an enable signal, and output a GOA timing control signal (GOA timing control signal) to the level shifter 12 to control the output of the GOA signal.

In a further embodiment, the timing controller 13 is configured to: accessing the memory 11 while outputting the GOA timing control signal controlling the GOA signal to be output-free when the enable signal of a first level is received; is configured to: when the enable signal of the second level is received, the access to the memory 11 is ended, and the GOA timing control signal for controlling the GOA signal to be normally outputted is outputted. That is, when the memory 11 needs to be accessed to acquire demux data, the output time of the level shifter 12 can be controlled by the timing controller 13 to avoid the reading time of the demux data in the memory 11 by the timing controller 13, so that the interference of the GOA signal on the quality of the transmission signal between the timing controller 13 and the memory 11 is avoided, and the reading stability of the demux data in the memory 11 by the timing controller 13 is improved.

In a further embodiment, the timing controller 13 accesses the memory 11 through an SPI transmission signal to acquire the Demura data. SPI (Serial Peripheral Interface ) is a high-speed, full duplex, synchronous communication bus, and occupies only four wires on the pins of the chip, saving space on the layout of PCBA, providing convenience.

In a further embodiment, the enable signal is an SPI enable signal spi_en.

In a further embodiment, the timing controller 13 is provided with an I/O port (pin) 131, the I/O port 131 being adapted to be connected to an external debug device 19. The timing controller 13 receives the enable signal generated by the debug apparatus 19 through the I/O port 131. That is, in the production line machine debugging stage, when the debugging device 19 needs to access the memory 11 through the timing controller 13, an enabling signal is generated to the timing controller 13; furthermore, the timing controller outputs a GOA timing control signal to the level shifter 12 to control the GOA signal to be output, so that the output time of the level shifter 12 can avoid the reading time of the timing controller 13 for reading the demux data in the memory 11, thereby avoiding the interference of the GOA signal on the SPI transmission signal quality between the timing controller 13 and the memory 11, and improving the reading stability of the timing controller 13 for reading the demux data in the memory 11.

In a further embodiment, the level shifter 12 and the timing controller 13 are provided on the same Control Board (CB) 130. Preferably, the level shifter 12 may be integrated with a power manager, a Gamma voltage generator, etc. in the same chip, so as to improve the integration level of the peripheral circuit and facilitate the narrow frame of the panel.

In a further embodiment, the driving circuit further comprises a source driver 14; the memory 11 is disposed on a Printed Circuit Board (PCBA) 140 on which the source driver 14 is disposed. The source driver 14 charges the panel (provides a Data signal) through a source-side Chip On Film (COF) 17.

The driving principle of the driving circuit of the display panel of the present application will be described below with reference to fig. 2.

The timing controller 13 adds an I/O pin to receive the enable signal spi_en. The enable signal spi_en may be generated by an external debug device 19. When the timing controller 13 needs to access the memory 11, the enable signal spi_en is at a high level H; when the access of the timing controller 13 to the memory 11 is finished, the enable signal spi_en is at the low level L.

As shown in part a of fig. 2: after the display device is powered on (power on), the driving voltage VDD jumps to a high level; during the period when the timing controller 13 needs to access the memory 11 (as shown by the dashed box in the part a), the enable signal spi_en is at a high level H, and the GOA timing control signal output by the timing controller 13 to the level shifter 12 is at a low level L, so that the GOA signal output by the level shifter 12 to the panel is not output, and there is no GOA signal with high frequency and high voltage switching, so that no interference is caused to the SPI transmission signal (shown as a plurality of pulse signals); at this time, the panel internal Gate (Gate) signal is in an off state, and the source driver 14 cannot charge the panel, so that the power consumption of the whole system is small, and the interference of the power supply system on the SPI transmission signal is also small. Therefore, the stability of the timing controller 13 to read the Demura data in the memory 11 is improved.

As shown in part b of fig. 2: in contrast, in the existing driving mode without adding the enable signal spi_en, during the period (as shown by the dashed box in the b part) when the timing controller 13 needs to access the memory 11, the output time of the GOA signal output by the level shifter 12 coincides with the reading time of the demux data in the memory 11 read by the timing controller 13, so that the high-frequency, high-differential-pressure GOA signal output by the level shifter 12 will interfere the SPI transmission signal between the timing controller 13 and the memory 11; and at this time, the source driver 14 charges the panel, which also makes the whole system consume large power and the power system noise large, so as to cause interference to the SPI transmission signal.

Based on the same inventive concept, the application also provides a display device.

Referring to fig. 3, a schematic diagram of a display device according to the present application is shown. The display device 30 includes a display panel 31 and a driving circuit 32. The driving circuit 32 is the driving circuit shown in fig. 1 according to the present application. The component connection manner and the working principle of the driving circuit 32 have been described in detail before, and will not be described again here.

The above description of the embodiments is only for helping to understand the technical solution of the present application and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A driving circuit of a display panel, the driving circuit comprising:

a memory for storing demra data for compensating for a display effect of the display panel;

a level shifter for outputting GOA signals to the display panel; and

a timing controller for accessing the memory to obtain the Demura data in response to an enable signal, and directly outputting a GOA timing control signal to the level shifter to control the output of the GOA signal;

when the enabling signal is at a high level, the GOA time sequence control signal output to the level converter by the time sequence controller is at a low level, and the GOA signal output to the display panel by the level converter is not output.

2. The drive circuit of claim 1, wherein the timing controller is configured to access the memory while outputting the GOA timing control signal that controls the GOA signal to be output-free when the enable signal of a first level is received.

3. The drive circuit of claim 1, wherein the timing controller is further configured to terminate access to the memory when the enable signal of a second level is received, while outputting the GOA timing control signal that controls normal output of the GOA signal.

4. The drive circuit of claim 1, wherein the timing controller accesses the memory via an SPI transmission signal to acquire the Demura data.

5. The drive circuit of claim 1, wherein the enable signal is an SPI enable signal.

6. The driving circuit according to claim 1, wherein the timing controller is provided with an I/O port for connection to an external debugging device; the timing controller receives the enable signal generated by the debug apparatus through the I/O port.

7. The drive circuit of claim 1, wherein the level shifter is disposed on the same control board as the timing controller.

8. The driving circuit of claim 1, wherein the driving circuit further comprises a source driver; the memory is arranged on a printed circuit board where the source driver is arranged.

9. A display device, characterized in that the display device comprises:

a display panel; and

a driving circuit employing the driving circuit as claimed in any one of claims 1 to 8.