CN111681585A

CN111681585A - Display panel's drive circuit and display device

Info

Publication number: CN111681585A
Application number: CN202010503353.9A
Authority: CN
Inventors: 肖波
Original assignee: TCL China Star Optoelectronics Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd
Priority date: 2020-06-05
Filing date: 2020-06-05
Publication date: 2020-09-18
Anticipated expiration: 2040-06-05
Also published as: CN111681585B

Abstract

The application discloses a drive circuit of a display panel and a display device. This application is through newly increasing an enable signal and by time schedule controller control time sequence to when receiving the enable signal of first level, visit the memory in order to obtain the Demura data, output GOA time schedule control signal simultaneously and do not have the output with the GOA signal of control output to display panel, thereby avoid GOA signal interference transmission signal between time schedule controller and the memory, improved the reading stability ability that time schedule controller reads the Demura data in the memory.

Description

Display panel's drive circuit and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel driving circuit and a display device capable of improving Demura data reading stability required by debugging of a display panel.

Background

In order to optimize the display effect of the display panel, a memory is disposed on a Source side (Source) Printed Circuit Board (PCBA) for storing compensation data-Demura data of the display effect of the panel. The PCBA refers to a printed circuit board formed by a PCB blank board after the whole process of SMT loading or DIP plug-in. And the panel production line stores the debugged compensation data in the memory through online debugging. After power on, the Timing Controller (TCON) will call the corresponding Demura data from the memory, and provide it to the timing controller for integration and output, so as to improve the display effect of the panel.

The time schedule controller reads Demura data from the memory through SPI (Serial Peripheral Interface) transmission signals, and SPI communication is adopted between the time schedule controller and the memory. If the data in the memory is to be called correctly, the SPI transmission signal must be kept as a stable signal in the reading process, otherwise, once external interference causes failure of SPI communication between the timing controller and the memory, the purpose of improving the effect of the display panel cannot be achieved.

Interference comes primarily from two aspects: 1) when the display panel works, a Source driving chip (Source IC) on a Source side PCBA charges the panel, the power consumption of the whole system is large, and the noise of a power supply system is large; 2) a GOA (Gate Driver on Array, Array substrate row drive) signal output to the panel by a Level Shifter (LS) is a square wave signal with high frequency and high voltage difference, and a layout (layout) routing in the PCBA itself may cause interference to other signals (such as SPI transmission signals) due to parasitic capacitance.

The scheme for avoiding interference in the prior art is to shorten a connecting wire, add a shielding layer to the wire and reduce the interference of an external debugging environment as much as possible. However, existing solutions do not avoid signal interference from the PCBA itself.

Therefore, how to improve the stability of Demura data required by the debugging of the display panel becomes a technical problem that the development of the debugging technology of the existing display panel needs to be improved.

Disclosure of Invention

An object of the application is to provide a display panel's drive circuit and display device, can avoid exporting the interference of the GOA signal of panel to the SPI transmission signal between time schedule controller and the memory, improve the required Demura data of display panel debugging and read stability.

To achieve the above object, the present application provides a driving circuit of a display panel, the driving circuit including: a memory for storing Demura data for compensating the display effect of the display panel; a level shifter for outputting GOA signals to the display panel; and the time schedule controller is used for responding to an enabling signal, accessing the memory to acquire the Demura data and outputting a GOA time schedule control signal to the level converter to control the output of the GOA signal.

To achieve the above object, the present application also provides a display device including: a display panel; and the driving circuit adopts the driving circuit.

The application has the advantages that: this application display panel's drive circuit, through newly-increased enabling signal and by time schedule controller control time sequence, in order when receiving the enabling signal of first level, visit the memory in order to obtain the Demura data, output GOA time sequence control signal simultaneously and do not have the output with the GOA signal of control output to display panel, thereby avoid the GOA signal that level shifter exported display panel, the SPI transmission signal quality between interference time schedule controller and the memory, the stability can of reading of Demura data in the time schedule controller reading memory has been improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a block diagram of a driving circuit of a display panel according to the present invention;

FIG. 2 is a driving timing diagram of a driving circuit of a display panel according to the present invention;

FIG. 3 is a schematic diagram of a display device according to the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The terms "first," "second," "third," and the like in the description and in the claims of the present application and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware circuits or integrated circuits, or in different networks and/or processor means and/or microcontroller means.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

This application display panel's drive circuit, through newly-increased enabling signal and by time schedule controller control time sequence to when the enabling signal of receiving first level, visit the memory in order to obtain the Demura data, output GOA time sequence control signal does not have the output with the GOA signal of control output to display panel simultaneously, thereby avoid level shifter to export the GOA signal of display panel, disturb the SPI transmission signal quality between time schedule controller and the memory. In production line board debugging stage promptly, when needs visit the memory, control through time schedule controller, can make the output time of level shifter avoid time schedule controller to read the read time of the Demura data in the memory to avoid GOA signal to SPI transmission signal quality's interference, improve the read stability ability of time schedule controller reading Demura data in the memory.

Fig. 1 is a structural diagram of a driving circuit of a display panel of the present application, and fig. 2 is a driving timing diagram of the driving circuit of the display panel of the present application. The drive circuit 10 of the display panel of the present application includes: a memory 11, a level shifter 12 and a timing controller 13.

Specifically, the memory 11 is used for storing Demura data for compensating a display effect of a display panel (not shown). After each time the display device is powered on, the timing controller 13 first reads Demura data in the memory 11, then processes and compensates received data signals (for example, data to be displayed), and finally outputs the data signals to the display panel for displaying.

Due to limitations of crystallization processes, when LTPS TFTs (low temperature polysilicon thin film transistors) are fabricated on large-area glass substrates, TFTs at different positions often have non-uniformity in electrical parameters such as threshold voltage, mobility, and the like; this non-uniformity translates into current and brightness differences of the display device and is perceived by the human eye, i.e., the Mura phenomenon.

In order to stabilize the display effect of the display panel, a compensation method needs to be adopted, and there are two methods of internal compensation and external compensation. The external compensation may be classified into an optical extraction type and an electrical extraction type according to a data extraction method. The optical extraction type is a De-Mura technique in which a brightness signal is extracted by an optical CCD photographing method after a back plate is lighted. The optical extraction method has the advantages of simple structure and flexible method, and is widely adopted at present. The Demura data generated by the De-Mura technology is burned into the storage unit to process and compensate the received data signal (such as data to be displayed) in the subsequent data processing, so as to compensate the display effect of the display panel.

In a further embodiment, the memory 11 is a Flash memory (Flash). Since data stored in a Flash memory (Flash) can be stored even after power failure, Demura data can be stored in an external memory Flash. In other embodiments, the Demura data may also be stored in an EEPROM (Electrically Erasable Programmable read only memory).

Specifically, the level shifter 12 is configured to output a GOA (Gate Driver on array) signal to the display panel. Specifically, the level shifter 12 is used for outputting the GOA signal to the panel GOA area 18 of the display panel. The GOA signal is a square wave signal with high frequency and high pressure difference.

Specifically, the timing controller (TCON IC)13 is configured to access the memory 11 to obtain the Demura data in response to an enable signal, and output a GOA timing control signal (GOA timing control signal) to the level shifter 12 to control the output of the GOA signal.

In a further embodiment, the timing controller 13 is configured to: accessing the memory 11 while outputting the GOA timing control signal controlling no output of the GOA signal when receiving the enable signal of a first level; and is configured to: when the enable signal of the second level is received, the access to the memory 11 is ended, and the GOA timing control signal controlling the normal output of the GOA signal is output. That is, when it is necessary to access the memory 11 to obtain Demura data, the timing controller 13 controls the output time of the level shifter 12 to avoid the read time of the timing controller 13 for reading Demura data in the memory 11, so as to avoid interference of GOA signals on the quality of transmission signals between the timing controller 13 and the memory 11, and improve the read stability of the timing controller 13 for reading Demura data in the memory 11.

In a further embodiment, the timing controller 13 accesses the memory 11 through an SPI transmission signal to acquire the Demura data. The SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus, and occupies only four wires on the pins of the chip, saving the pins of the chip, and providing convenience for saving space on the layout of the PCBA.

In a further embodiment, the enable signal is an SPI enable signal SPI _ EN.

In a further embodiment, the timing controller 13 is provided with an I/O port (pin)131, and the I/O port 131 is used for connecting with an external debugging device 19. The timing controller 13 receives the enable signal generated by the debug device 19 through the I/O port 131. That is, in the production line machine debugging stage, when the debugging device 19 needs to access the memory 11 through the timing controller 13, an enable signal is generated to the timing controller 13; and then the timing controller outputs a GOA timing control signal to the level shifter 12 to control the GOA signal not to be output, so that the output time of the level shifter 12 can avoid the reading time of the timing controller 13 for reading the Demura data in the memory 11, thereby avoiding the interference of the GOA signal on the SPI transmission signal quality between the timing controller 13 and the memory 11, and improving the reading stability of the timing controller 13 for reading the Demura data in the memory 11.

In a further embodiment, the level shifter 12 and the timing controller 13 are disposed on the same Control Board (CB) 130. Preferably, the level shifter 12 may also be integrated with a power manager, a Gamma voltage generator, and the like in the same chip, so as to improve the integration level of the peripheral circuit, which is beneficial to the narrow frame of the panel.

In a further embodiment, the driving circuit further includes a source driver 14; the memory 11 is disposed on a Printed Circuit Board (PCBA)140 on which the source driver 14 is disposed. The source driver 14 charges the panel (provides a Data signal) through a source side Chip On Film (COF) 17.

The driving principle of the driving circuit of the display panel of the present invention will be described below with reference to fig. 2.

The timing controller 13 adds an I/O pin to receive the enable signal SPI _ EN. The enable signal SPI _ EN may be generated by an external debug device 19. When the timing controller 13 needs to access the memory 11, the enable signal SPI _ EN is at a high level H; when the access of the timing controller 13 to the memory 11 is finished, the enable signal SPI _ EN is at a low level L.

As shown in part a of fig. 2: after the display device is powered on, the driving voltage VDD jumps to a high level; during the period that the timing controller 13 needs to access the memory 11 (as shown by the dashed box in the part a), the enable signal SPI _ EN is at the high level H, and the GOA timing control signal output by the timing controller 13 to the level shifter 12 is at the low level L, so that the GOA signal output by the level shifter 12 to the panel is not output, and there is no GOA signal with high frequency and high voltage switching, and therefore no interference is caused to the SPI transmission signal (shown as multiple pulse signals); at this time, a Gate (Gate) signal inside the panel is in an off state, and the source driver 14 cannot charge the panel, so that the power consumption of the whole system is low, and the interference of the power supply system to the SPI transmission signal is also small. Therefore, the stability of the timing controller 13 in reading the Demura data in the memory 11 is improved.

As shown in part b of fig. 2: in contrast, in the conventional driving method without adding the enable signal SPI _ EN, during the period when the timing controller 13 needs to access the memory 11 (as shown by the dashed box in part b), the output time of the level shifter 12 outputting the GOA signal coincides with the reading time of the timing controller 13 reading the Demura data in the memory 11, so that the high-frequency and high-voltage difference GOA signal output by the level shifter 12 may interfere with the SPI transmission signal between the timing controller 13 and the memory 11; and at this time, the source driver 14 charges the panel, which also causes the power consumption of the whole system to be large, the noise of the power system to be large, and the interference to the SPI transmission signal to be caused.

Based on the same inventive concept, the application also provides a display device.

Referring to fig. 3, a schematic diagram of a display device according to the present application is shown. The display device 30 includes a display panel 31 and a driving circuit 32. The driving circuit 32 is the driving circuit shown in fig. 1 of the present application. The connection mode and the operation principle of the components of the driving circuit 32 have been described in detail previously, and thus are not described herein again.

The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A driving circuit of a display panel, the driving circuit comprising:

a memory for storing Demura data for compensating the display effect of the display panel;

a level shifter for outputting GOA signals to the display panel; and

and the time sequence controller is used for responding to an enabling signal, accessing the memory to acquire the Demura data and outputting a GOA time sequence control signal to the level converter to control the output of the GOA signal.

2. The driving circuit of claim 1, wherein the timing controller is configured to access the memory while outputting the GOA timing control signal controlling no output of the GOA signal when receiving the enable signal of a first level.

3. The driving circuit of claim 1, wherein the timing controller is further configured to end the access to the memory while outputting the GOA timing control signal controlling the normal output of the GOA signal when receiving the enable signal of a second level.

4. The driving circuit of claim 1, wherein the timing controller accesses the memory through an SPI transfer signal to obtain the Demura data.

5. The drive circuit of claim 1, wherein the enable signal is an SPI enable signal.

6. The driving circuit according to claim 1, wherein the timing controller is provided with an I/O port for connecting with an external debugging device; the timing controller receives the enable signal generated by the debugging device through the I/O port.

7. The driving circuit of claim 1, wherein the level shifter is disposed on a same control board as the timing controller.

8. The driving circuit of claim 1, wherein the driving circuit further comprises a source driver; the memory is arranged on the printed circuit board where the source electrode driver is arranged.

9. A display device, characterized in that the display device comprises:

a display panel; and

a driver circuit employing the driver circuit as claimed in any one of claims 1 to 8.