JP2011254985A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine, suitably operated even after the CPUs of the respective control parts are reset.SOLUTION: A main control part is configured to transmit an initial operation command when its CPU is reset, and a presentation control part 22 includes: an initial processing (ST46-ST52) executed when the CPU is reset; and a routine processing (ST54-ST63) of advancing the presentation operation while the memory storage of a volatile memory is updated. The initial processing includes a maintenance step (ST48-ST50) of determining the storage content of the volatile memory based on predetermined data and maintaining the storage content of the volatile memory under a predetermined condition when the correctness is acknowledged in the storage content. The routine processing includes: a backup step (ST63) of writing the predetermined data to the volatile memory; and an initial step (ST52) of returning the presentation operation to the initial state when the initial operation command is received.

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly, to a gaming machine that solves a trouble such as a power failure.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a gaming state is determined by a jackpot lottery executed on the condition that a game ball wins at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing.

  For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation.

  Further, before the final result is finalized, a notice effect is also executed in which a character appears or the effect movable body starts to rotate, and a big hit state is invited. The effect movable body, for example, rotates for a predetermined angle in a predetermined direction during an effect operation that is likely to reach a big hit state, and notifies the lottery result with a predetermined reliability.

JP 2009-000411 A JP 2008-259920 A JP 2008-245679 A

  By the way, in general, a gaming machine is a single unit that controls production operations such as lamp production, audio production, and image production based on a main control unit that centrally controls gaming operations and control commands from the main control unit. Alternatively, the sub-control unit is divided into a plurality of sub-control units. In addition, while the power consumption of modern gaming machines has been increasing, a large number of gaming machines are densely arranged in the gaming hall, so that each gaming machine operates in a very poor noise environment. Will do.

  Therefore, a part of the main control unit and sub control unit constituting the gaming machine may malfunction due to noise, and as a result of the program runaway, the CPU may be abnormally reset by a watchdog timer or the like. As a situation assumed in such a case, the main control unit is operating normally, but only the sub control unit is abnormally reset, and the main control unit is abnormally reset, the sub control unit is Typically, it is operating normally.

  In such a case, if the main control unit is operating normally, the impression to the player is better if the rendering operation in the sub-control unit that has been abnormally reset is continued as much as possible. On the other hand, when the CPU of the main control unit is reset, it is desirable to return the effect operation to the initial state regardless of whether the power is reset or abnormal reset.

  That is, since the power of the CPU of the main control unit is reset when the power to the gaming machine is turned on, all the rendering operations should be returned to the initial state. On the other hand, when the CPU of the main control unit is abnormally reset, the game operation in the main control unit returns to the initial state, so that the operation is continued even when the presentation control of the sub control unit is normally executed. There is no.

  The present invention has been made based on the above idea, and an object thereof is to provide a gaming machine that operates properly even after the CPU of each control unit is reset.

  In order to achieve the above object, the present invention executes a lottery process caused by a predetermined switch signal and centrally controls the game operation based on the lottery result, and supports the progress of the game operation. A main control unit configured to be able to maintain the stored contents of the volatile memory updated even after the DC power supply is shut off, and a sub-control unit that executes a rendering operation based on an instruction from the main control unit. A gaming machine that can shift to a gaming state advantageous to the player when winning the lottery process, and the main control unit is configured to transmit an initial operation command when the CPU is reset, The control unit is an initial process that is executed when the CPU of the sub-control unit is reset, a steady process that is repeatedly executed after the initial process is completed, and advances the rendering operation while updating the storage content of the volatile memory, Have In the initial processing of the sub-control unit, the storage content of the volatile memory is determined based on predetermined data, and if the storage content is valid, the storage content of the volatile memory is determined under predetermined conditions. On the other hand, the steady process of the sub-control unit is provided with a backup process for writing predetermined data in the volatile memory and an initial process for returning the rendering operation to the initial state upon receiving an initial operation command. It has been.

  The maintenance process of the present invention maintains the storage content of the volatile memory under a predetermined condition when the storage content of the volatile memory is recognized as valid. Therefore, when only the CPU of the sub-control unit is abnormally reset, there is a possibility that the rendering operation can be continued, and a countermeasure that does not give the player a sense of incongruity is possible.

  On the other hand, when the CPU of the main control unit is reset, an initial command is transmitted, and the sub-control unit receiving the command returns the production operation to the initial state even during normal operation. There is no inconsistency that only the control operation of the control unit returns to the initial state.

  The main control unit of the present invention preferably stops the progress of the game operation in response to the interruption of the AC power supplied to the gaming machine, and transmits an interruption command indicating that to the sub-control unit. When the sub-control unit receives the power interruption command, the sub-control unit stops the progress of the rendering operation, and after writing the data that is denied in the determination process to the volatile memory, the sub-control unit DC power supply It is configured to wait for being blocked.

  The present invention is preferably configured such that when the number of maintenance processes exceeds a predetermined value, the stored contents of the volatile memory are erased even if the stored contents are valid. Preferably, the sub-control unit controls a movable effect by the effect movable body, and in the effect reset process, the effect movable body is driven to accommodate the effect movable body in the origin area.

  Further, in the present invention, when the game operation is not proceeding normally, the first reset circuit for forcibly resetting the CPU of the main control unit and when the rendering operation is not proceeding normally It is preferable that a second reset circuit for forcibly resetting the CPU of the sub-control unit is provided.

  The sub-control unit of the present invention operates based on an upstream sub-control unit that operates based on an instruction from the main control unit, an instruction received from the main control unit via the upstream sub-control unit, and an upstream sub-control unit And a downstream sub-control unit that operates based on an instruction from.

  In this case, the upstream sub-control unit is preferably configured to include the maintenance process and the effect reset process, and the downstream sub-control unit is equivalent to the maintenance process of the upstream sub-control unit. It is preferable to have a process. The downstream sub-control unit preferably performs the effect operation using the display device, and the upstream sub-control unit preferably outputs the audio signal and executes the effect operation.

  In addition, it is preferable that a power reset circuit is provided that detects the input of AC power and outputs a system set signal to the sub-control unit. Note that the gaming machine of the present invention is typically a bullet ball game machine or a revolving game machine.

  As described above, according to the present invention, even if the CPU of the main control unit or the sub control unit is reset, the subsequent operation is appropriate.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram showing a circuit configuration of an effect control unit. It is drawing explaining the structure and operation | movement of a rotation motor and an origin switch. It is drawing explaining the structure and operation | movement of a raising / lowering motor and an origin switch. It is a flowchart explaining the main process of a main control part. It is a flowchart explaining the power interruption process of a main control part. It is a flowchart explaining the process of an effect control part. It is a flowchart explaining the command analysis process of an effect control part. It is a flowchart explaining a motor process. It is a flowchart explaining an origin detection process. It is a flowchart explaining a retry process. It is a flowchart explaining the first half of an initial operation process. It is a flowchart explaining the second half of the initial operation process. It is a flowchart explaining the latter half of an initial stage operation process about a raising / lowering motor. It is a flowchart explaining the main process of an image control part. It is a flowchart explaining the command analysis process of an image control part. It is a time chart explaining operation | movement at the time of power activation of a game machine. It is a time chart explaining operation | movement at the time of power activation of a game machine. It is a circuit diagram which shows the circuit structure of a power supply board. It is a circuit diagram of the reset circuit of a main control part and a payout control part. It is a time chart which shows operation | movement of a power supply monitoring part and a reset circuit.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a speaker is disposed below the glass door 6.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided in an annular shape on the surface of the game board 5, and a central opening HO extending toward the back side is provided in the approximate center. It has been. A display device DISP composed of a liquid crystal color display is arranged at the bottom of the central opening HO.

  In addition, an effect movable body AMU is disposed so as to be movable up and down in a space formed in front of the display device DISP. The effect movable body AMU includes a fixed member FIX that is held up and down by being held by the lifting mechanism ALV, and a rotating member ROT that is supported and rotated by the fixed member FIX. In the normal state, the effect movable body AMU stands by in the origin area suspended by the lifting mechanism ALV.

  A symbol starting port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged at appropriate positions in the game area 5a. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The display device DISP is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DISP has a special symbol display part Da to Dc in the center and a normal symbol display part 19 in the upper right part. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  The symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws, and when the stop symbol after the fluctuation of the normal symbol display unit 19 hits and the symbol is displayed, the opening and closing claws are displayed. It is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects. In addition, as a kind of notice effect, the effect movable body AMU may descend to the position of the central opening HO. Then, the lowered effect movable body AMU is rotated clockwise or counterclockwise and then raised to the original position.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DISP, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Thus, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the image control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 28 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 30 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the image control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been turned on to the power supply board 20. The power is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 28, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with a power supply voltage VB (12 V) supplied from the main control unit 21. Each switch signal indicating a winning state to the symbol starting port 15 is converted to a TTL level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). Then, the data is transmitted to the main control unit 21.

  As shown in FIG. 4, the effect control unit 22 stores a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by an effect movable body, and data transfer, a control program for the one-chip microcomputer 40, and the like. EPROM 41 to be played, an audio reproduction output circuit 42 for reproducing and outputting an audio signal based on an instruction from the one-chip microcomputer 40, and an audio memory 43 for storing compressed audio data which is original data of the audio signal to be reproduced And a watchdog timer WDT.

  The one-chip microcomputer 40 includes a parallel input / output port PIO. The parallel port PIO also outputs drive data Φ1 to Φ4 for causing the effect movable body AMU to function together with the control command CMD ′ and the strobe signal STB ′. The effect movable body AMU is moved up and down by a lifting motor MO that constitutes the lifting mechanism ALV, and is driven to rotate by a rotary motor MT disposed on the fixed member FIX. The elevating motor MO and the rotating motor MT are composed of stepping motors and are driven via driver circuits 45A and 45B, respectively. Further, an origin switch ORG is provided in relation to the rotary motor MT and the lift motor MO, and the switch signal (origin detection signal) SN is input to the parallel port PIO.

  The watchdog timer WDT is reset by a clear pulse periodically supplied from the one-chip microcomputer 40. When the clear pulse is interrupted due to a program runaway or the like, a reset signal RESET is output. As a result, the one-chip microcomputer 40 is forcibly reset to the initial state, and the program runaway state is solved.

  As shown in FIG. 4, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are sent to the one-chip microcomputer 40 of the effect control board 22 via the buffer 48 of the effect interface board 27. Is supplied. The interrupt signal STB is supplied to the interrupt terminal INT of the one-chip microcomputer. Then, the effect control unit 22 acquires the control command CMD by the reception interrupt process activated by the strobe signal STB.

  The control command CMD acquired by the effect control unit 22 includes (1) an abnormality notification and other notification control commands, and (2) a control for specifying an outline of various effect operations resulting from winning at the symbol start opening. Commands (variation pattern commands) are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of winning or failing in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command CMD, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified.

  For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ related to the rendered symbol effect is output. Further, during the advance notice operation using the effect movable body AMU, the rotary motor MT is rotated after the elevating motor MO is rotated.

  At the timing of rotating the lifting motor MO, drive control to the rotary motor MT is also started, and the rotary motor MT changes from a non-drive state in which free rotation is possible to a drive state in which a stationary posture is maintained. Therefore, even if the effect movable body AMU is moved up and down quickly, there is no possibility that the horizontal posture of the effect movable object AMU is broken when stopped.

  In order to realize such a symbol effect synchronized with the effect operation, the effect control unit 22 outputs a control command CMD ′ to the effect interface board 27 together with a strobe signal (interrupt signal) STB ′ for the image control unit 23. To do. When the notification control command related to the display device or other control commands is received, the effect control unit 22 outputs the control command to the effect interface board 27 together with the interrupt signal STB ′. .

  Corresponding to the configuration of the effect control board 22, the effect interface board 27 is configured to receive an 8-bit control command CMD 'and a 1-bit interrupt signal STB'. These data CMD ′ and STB ′ are output to the image control board 23 via the buffer circuit 46 as they are. The effect interface board 27 receives a lamp driving signal output from the effect control unit 22 and supplies the signal to the LED lamp group via the lamp connection board 34. As a result, a lamp effect corresponding to the control command CMD output from the main control unit 21 is realized.

  The image control unit 23 receives a control command via the effect interface board 27 and executes an image control operation, a VDP that drives the display device DISP based on an instruction of the one-chip microcomputer, It has a graphic ROM, a control ROM, and a watchdog timer WDT that forcibly resets the one-chip microcomputer.

  The system reset signal SYS is supplied via the effect interface board 27 to the reset terminal RESET of the built-in CPU of the one-chip microcomputer of the effect control unit 22 and the image control unit 23. Each CPU is reset.

  Next, the rotation motor MT that rotates the effect movable body AMU will be described. As shown in FIG. 5, the effect movable body AMU of the embodiment is driven by a driver circuit 45 </ b> B and a rotary motor MT mounted on the effect control board 22. More specifically, the illustrated effect movable body AMU includes a rotation motor MT that rotates in one direction in a steady state and a rotation member ROT that is rotationally driven via gears G1 and G2. (See FIG. 5 (a)).

  As shown in FIG. 5B, the rotary motor MT is configured by, for example, a two-phase excited stepping motor, and the driver circuit 45B is configured by including a Darlington-connected transistor Tr and a damper diode Dp. Yes. In this embodiment, the rotating member ROT geared to the rotating motor MT rotates at a 360/245 ° pitch, and when the rotating motor MT receives the driving pulses Φ1 to Φ4 of 245 steps, the rotating member ROT. Rotates once.

  The drive pulses Φ1 to Φ4 are generated, for example, by outputting 4-bit drive data 0101, 1001, 1010, 0110 to the driver circuit 45B, and changing the output drive data causes the rotary motor MT to perform one step. Step through every corner. When the drive data does not change, the rotary motor MT stops in a restrained state. On the other hand, when the non-drive data (0000) is output to the driver circuit 45B, the rotary motor MT is in an unconstrained state in which it can freely rotate.

  In the effect movable body AMU, an origin switch ORG that detects that the rotating member ROT has reached the origin position is arranged. Therefore, even if the rotational torque of the rotary motor MT becomes insufficient with respect to the effect movable body AMU, the effect movable body AMU can be rotated exactly once. That is, if the rotational torque of the rotary motor MT is insufficient, there is a possibility that the effect movable body AMU cannot be rotated exactly once with the driving pulses Φ1 to Φ4 of 245 steps, but the origin switch ORG is provided. Therefore, it is not necessary to control the rotation angle 360 ° with the number of steps of the drive pulse. For example, when the rotational speed is increased by gear coupling, the rotational torque is reduced, so that the origin switch ORG is significant.

  Specifically, the origin switch ORG includes a photo interrupter PH having a light emitting part and a light receiving part, and a light shielding piece SH that blocks inspection light emitted from the light emitting part. Note that the light emitting unit is configured by a photodiode, and the light receiving unit is configured by a phototransistor (see FIG. 5C). Therefore, the origin detection signal SN is normally at the L level (OFF level) as the output of the phototransistor, but is at the H level (ON level) in the light shielding state by the light shielding piece SH.

  The origin detection signal SN becomes H level for a predetermined time (N1 + N2) corresponding to the rotational speed V of the rotating member ROT and the circumferential width of the photo interrupter PH and the light shielding piece SH (see FIG. 5D). ). Therefore, in this embodiment, the light shielding piece SH is defined as an origin region having a region that maintains the inspection light of the photo interrupter PH in a shielded state. Then, a position where the forward reference time N1 has elapsed since the light shielding piece SH rotating in the forward direction at the constant speed V starts to shield the inspection light of the photo interrupter PH is defined as the origin position. On the contrary, the position where the light shielding piece SH rotating in the reverse direction at a constant speed starts to shield the inspection light from the photointerrupter PH for the reverse reference time N2 also becomes the origin position.

  Therefore, the total time that the light shielding piece SH exists in the origin region is N1 + N2 in the effect movable body AMU that rotates at the constant speed V. Further, as shown in FIG. 5D, when the effect movable body AMU rotates at a constant speed V, the lap time from the passage of the origin to the arrival of the origin again becomes M. The lap time M corresponds to the step angle θ (= 360 ° / 245) and the time interval τ at which the drive pulses Φ1 to Φ4 are updated (the time during which the rotating member ROT advances by the step angle θ). 245 * τ. Further, the rotation angles that advance between the forward reference time N1 and the backward reference time N2 are N1 / τ * θ and N2 / τ * θ, respectively.

  As described above, FIG. 5 illustrates the case where the production movable body AMU rotates. However, the production movable body AMU is not necessarily limited to such an embodiment. For example, the production movable body AMU is configured by a rack and a pinion, such as the lifting motor MO. It is also preferable to reciprocate. In this case, when the pinion is rotated, the rack meshed with the pinion moves, and the movable member MV moves together with the effect movable body AMU.

  FIG. 6 is a diagram illustrating the relationship between the movable member MV and the lifting motor MO. A light shielding piece SH is disposed at the left end of the movable member MV, and stopper mechanisms (mechanical locks) that prevent further movement are disposed at both ends of the movement path of the movable member MV. Further, a photo interrupter PH is arranged in the vicinity of the left mechanical lock, and the inspection light is shielded when the light shielding piece SH enters here.

  As is apparent from the above configuration, the movable range of the movable member MV is from the position where the left end of the movable member MV is in contact with the left mechanical lock to the position where the right end of the movable member MV is in contact with the right mechanical lock. . For convenience, in the following description, the left side in FIG. 6 is the origin side, and the right side in FIG. 6 is the end point side (or the MAX side). The movement toward the end point is defined as the forward direction, and the movement toward the origin is defined as the reverse direction.

  Also in this embodiment, the light shielding piece SH that moves in the reverse direction at a constant speed V shields the inspection light of the photointerrupter PH, with the area where the light shielding piece SH maintains the inspection light of the photointerrupter PH in the shielding state as the origin area. The position where the reference time N has elapsed since the start of the operation is defined as the origin position.

  In FIG. 6C, the movable range (maximum movement distance L) of the left end of the movable member MV is indicated by a dashed arrow, and the origin detection signal SN corresponds to the position of the left end of the movable member MV. It changes like 6 (b). As shown in FIG. 6A, when the movable member MV moves at a constant speed V, the left end of the movable member MV leaves the origin-side mechanical lock, and then the right end of the movable member MV contacts the end-side mechanical lock. The moving time until it is done is M.

  Assuming that the lifting motor MO rotates by one step angle over a unit time τ, the rack moves corresponding to the maximum moving distance L shown in FIG. 6C, assuming that the rack moves by the unit distance UN. The time M is M = τ * L / UN (L = UN * M / τ). Further, during this reference time N, the number of steps of the drive pulses Φ1 to Φ4 supplied to the lifting motor MO is N / τ, and the moving distance of the movable member MV is UN * N / τ.

  7 to 18 are flowcharts for explaining the operation contents of each part of the gaming machine GM shown in FIG. 7 to 8 show the operation of the main control unit 21, FIGS. 9 to 17 show the operation of the effect control unit 22, and FIGS. 18 to 19 show the operation of the image control unit 23. In the following description, the lift motor MO is hardly mentioned, but the description of the rotary motor MT is applicable to the lift motor MO as it is in principle.

  First, the main control unit 21 will be schematically described. The main control unit 21 includes a main process (FIG. 7) that is started by a CPU reset, and a timer interrupt that is started every predetermined time and that mainly executes control operations. Processing (not shown). Note that a Z80 CPU (Zilog) equivalent product is built in the one-chip microcomputer that realizes these processes.

  The main process (CPU reset process) shown in FIG. 7 is started when the initialization switch SW is turned off and the power is turned on, such as when recovering from a power failure, and when the game hall is opened. As described above, the initialization switch SW may be turned on to turn on the power. The main process of FIG. 7 is also started when the watchdog timer built in the reset circuit RST is activated or when the CPU is forcibly reset due to noise superimposed on the reset terminal.

  In addition, the broken line of FIG. 7 has abbreviated the operation | movement content of the production | generation control part 22 and the image control part 23, and the production | generation control part 22 respond | corresponds to CPU reset, and the origin detection process (FIG. 11 of FIG. 11). SS5) is executed, and the image controller 23 displays the initial screen on the display device DISP in response to the CPU reset.

  In the main control unit 21, in response to the CPU reset, the CPU is set to an interrupt disabled state, and the CPU stack pointer is set to an initial value (ST1). Each part of the one-chip microcomputer is initialized (ST1). In these processes, the work area of the built-in RAM is not used. For example, the control parameter stored in the ROM is simply read into the CPU register and written in place. Note that such an operation not using the work area is continued until the process of step ST6.

  Next, the RAM clear signal CLR is acquired from the input port, and the level is stored in the CPU register (ST2). The RAM clear signal CLR indicates the ON / OFF operation state of the initialization switch SW by a staff member when the power is turned on. Therefore, when the acquisition timing of the RAM clear signal CLR is delayed, the clerk releases the switch and misses the ON operation. However, in this embodiment, the RAM clear signal CLR is acquired promptly after the power is reset. Such a situation does not occur.

  When the process of step ST2 is completed, a predetermined standby time is consumed while outputting a clear pulse to the watchdog timer of the reset circuit RST (ST3, ST4). By this time consumption processing, the preparation operation of the control units 22 and 23 that should receive the control command from the main control unit 21 is reliably completed. That is, at the timing when the time consumption process (ST3, ST4) is finished, the effect control unit 22 starts executing the steady process (ST54 to ST63), and the image control unit 23 executes the steady process (SE7 to SE14). The consumption time is designed to start.

  Subsequently, the power supply abnormality signal ABN1 output from the power supply board 20 is acquired, and the same processing is repeated until it changes to a normal level (ST5 to ST6). This takes into consideration that the power supply voltage Vcc may not drop completely even after the processing of ST40 in FIG. That is, even if the watchdog timer function is exhibited and the CPU is reset at the timing when the power interruption process of FIG. 8 is completed and the infinite loop process is repeated, the subsequent process does not proceed to step ST7 and subsequent steps. .

  If such a standby process (ST5 to ST6) is not provided, the RAM data (the basic data of the checksum calculation and the backup flag BFL set in ST33) is rewritten by the steady process that has progressed after step ST7. The data is saved even after the power is turned off. In such a case, in the next day determination, the backup flag BFL = 0 or the checksum value backed up on the previous day (ST36) does not match the checksum value calculated after powering on the next day. Precious backup processing (ST36) is wasted.

  Further, the processes in steps ST5 to ST6 function effectively even in a momentary power interruption state in which the AC power supply is interrupted for a moment, including the case where the power switch is quickly turned OFF → ON. That is, even in the instantaneous power failure state, the power supply abnormality signals ABN1 and ABN2 are supplied to the main control unit 21 and the payout control unit 24, so the main control unit 21 starts the power supply monitoring process of FIG. Depending on the pulse width of the power supply abnormality signal ABN1, there is a possibility that the processing of steps ST25 to ST31 is completed and the processing proceeds to backup processing. However, even if such a situation occurs, the CPU is then reset by the watchdog timer function. At that time, the game operation up to that point is resumed by passing the processing of steps ST5 to ST6. The

  Even in such a case, if it is determined in step ST6 that the power supply abnormality signal ABN1 is at the normal level (H), the rewriting operation of the built-in RAM is permitted (ST7). As described above, the work area of the built-in RAM is not used in the processing of steps ST1 to ST6.

  Next, the CPU transmits an initial operation command to the effect control unit 22 (ST8). This initial operation command is a control command for normally executing the movable effect by the effect movable body AMU, but has undergone the time consumption processing of steps ST3 to ST4, so at this timing, the preparation control unit 22 is ready for reception. Is definitely complete.

  As indicated by the broken line, the effect control unit 22 that has received the initial operation command executes an initial operation process of the rotary motor MT. In addition, the image control unit 23 that has received the initial command transferred from the effect control unit 22 displays, for example, “PLEASE WAIT” on the display device DISP.

  Following the process of step ST8, after transmitting a clear pulse to the watchdog timer, the level of the power-on signal received from the payout control unit 24 is determined (ST9, ST10). In the present embodiment, since the main control unit 21 and the payout control unit 24 independently perform the power supply reset operation, the rising operation of the payout control unit 24 may be delayed beyond the standby time of steps ST3 to ST4. There is also.

  However, even in such a case, the rising operation delay of the payout control unit 24 can be absorbed through the determination process of step ST10. Also, in the unlikely event that the payout control unit 24 is not functioning normally due to some trouble, the game operation is not started simply by repeating the processing of steps ST9 to ST10. No situation occurs and there is no risk of distrust to the player.

  On the other hand, if it is confirmed by the determination in step ST10 that the payout control unit 24 is operating normally, the level of the RAM clear signal acquired in advance in the process of step ST2 is determined (ST11). Here, assuming that the RAM clear signal is in the ON state, the entire area of the built-in RAM is cleared to zero (ST18). Therefore, the value of the backup flag BFL set in the process of step ST33 in FIG. 8 becomes zero together with other checksum values.

  Next, a RAM clear command for notifying that the RAM area has been cleared to zero is output to the effect control unit 22 (ST18), and a notification timer is initialized (ST20). The notification timer manages a notification time (for example, 30 seconds) for notifying the hall computer that the RAM area has been cleared to zero. With this sufficient notification time, for example, even if an abnormal situation occurs in which the CPU is abnormally reset due to an illegal act, the hall computer can reliably grasp the situation. It should be noted that the illegal player may intentionally execute the RAM clear process (ST18) to return the random value used in the lottery process for determining whether or not to invite the big hit state to the initial value. is there.

  Returning to the determination process of step ST11, the description will be continued. When the CPU is forcibly reset by the watchdog timer or when the CPU is restored from the power failure state, the RAM clear signal is in the OFF state. In such a case, following the determination in step ST11, the contents of the backup flag BFL are determined (ST12). The backup flag BFL is data indicating that the operation of the power interruption process of FIG. 8 has been executed. In this embodiment, the backup flag BFL is set to the ON level (5AH) in the process of step ST33 when the power is shut off. Then, it is cleared to zero in the process of step ST28 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST12 to step ST18 to return the operation of the gaming machine to the initial state.

  On the other hand, if backup flag BFL = 5AH, checksum calculation for calculating the checksum value is executed (ST13). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST14).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power interruption process (FIG. 8) executed when the power is turned off (ST36). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST14.

  However, if the checksum calculation (ST36) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged after that until the checksum calculation (ST13) of the main process is executed. In such a case, the determination result in step ST14 is inconsistent. If data corruption is detected due to a discrepancy in the determination results, the process proceeds to step ST18, RAM clear processing is executed, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST14 that the checksum value obtained by the checksum calculation (ST13) matches the stored value at the SUM address, the process proceeds to step ST15.

  Then, the backup return command, the stored number display command, and the game state display command are transmitted to the effect control unit 22 in this order (ST15 to ST16). If the gaming machine at the time of power-off is in a non-gaming state, a demo command is transmitted to the effect control unit accordingly (ST17). By receiving these control commands, the sub-control unit can start the operation corresponding to the gaming state resumed by the main control unit 21 that has been restored to backup.

  Note that the stored number display command means the number of start suspensions of effect operations related to special symbols and normal symbols, and indicates the number of game balls that have passed through the symbol start port 17 and the gate 18 continuously. The game state display command indicates a game state to be resumed. For example, it is specified whether or not the game state to be backed up is a probability change state.

  When a series of processing (ST15 to ST17, ST18 to ST20) related to backup recovery or RAM clear is completed in this way, CTC (Counter Timer Circuit) that outputs an interrupt signal for starting a timer interrupt operation (not shown) is initialized. (ST21). Then, with the CPU set to the interrupt disabled state (ST25), update processing is executed for various counters (ST23), and then the CPU is returned to the interrupt enabled state and returns to step ST22.

  By the way, as shown by the broken line, the production control unit 22 that has received the backup return command turns off the lamp and makes the sound output silent. The image control unit 23 that has received the backup return command transferred from the effect control unit 22 displays, for example, “Recovered from power failure. Please restart the game” on the display device DISP.

  On the other hand, the effect control unit 22 that has received the RAM clear command turns on the lamps and generates a RAM clear sound for a predetermined time (30 seconds). As will be described later, in this embodiment, even if other errors occur, the crime prevention function is high because the output of the RAM clear sound is always continued for a predetermined time. The image control unit 23 that has received the RAM clear command transferred from the effect control unit 22 displays a special symbol in a predetermined manner (for example, 7.3.1) on the display device DISP.

  Although the CPU reset process (main process) has been described above, the timer interrupt process is periodically executed every 2 mS with the main process interrupted. In the timer interrupt process, a control process including a watchdog timer clear process and a power interruption process shown in FIG. 8 is executed each time.

  In the power interruption process, first, the power supply abnormality signal ABN1 supplied from the power supply board 20 is repeatedly acquired through the input port (ST25). Then, on the condition that the level of the power supply abnormality signal ABN1 coincides twice continuously (ST26), the level is determined (ST37). Here, when the power supply abnormality signal ABN1 is not at an abnormal level, the abnormality number counter and the backup flag BFL are cleared to zero and the processing is terminated (ST28, ST29).

  On the other hand, if the power supply abnormality signal ABN1 is at the abnormal level, the abnormality number counter is incremented (+1) (ST30), and it is determined whether the counting result exceeds the upper limit value MAX (ST31). This is because the acquired data from the input port may be garbled due to the influence of noise or the like, and the acquired data continuously maintains the abnormal level and the upper limit value MAX (for example, , MAX = 2), it is determined that the AC power supply is actually shut off.

  Thus, in this embodiment, even when the power is shut off, the backup process is not started immediately, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large-capacity capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST31, when the count value of the abnormality number counter matches the upper limit value MAX, the abnormality number counter is cleared to zero (ST32), and then the backup flag BFL is set to the ON level (= 5AH). (ST33). Next, in order to indicate that the main control unit 21 performs a backup operation, an electric power interruption command is transmitted to the effect control unit 22 (ST34 to ST35).

  The power interruption command is composed of a power interruption A command and a power interruption B command each having a 16-bit length, and is transmitted continuously every 8 bits in this order. The reason for adopting such a configuration is to prevent the power interruption situation from being erroneously reported to the effect control unit 22 due to the influence of noise or the like.

  When the transmission of the power interruption command is completed, the same calculation as the process of step ST13 of the main process is executed for the same work area (work area), and the calculation result is stored (ST36).

  Thereafter, the RAM access prohibited state is set (ST37), and the output data of all output ports is cleared (ST38). When the above backup process is completed, the generation of the interrupt signal INT is prohibited by the setting process for the CTC, and the CPU is set to the interrupt disabled state, and the DC power supply voltage is lowered while repeating the infinite loop process (ST39 to ST39). ST40). Since the power interruption process is executed during the timer interrupt process, the CPU may originally be in an interrupt disabled state, but in the present embodiment, again, in order to eliminate a malfunction due to a drop in power supply voltage, The CPU is set to disable interrupts, and output of the interrupt signal INT from the CTC is also prohibited.

  By the way, the power-off process of FIG. 8 is started rapidly within 2 mS which is a timer interruption period after the AC power supply is cut off, and is quickly ended. On the other hand, the drop in power supply voltage Vcc to a predetermined level is considerably delayed due to the influence of a smoothing capacitor arranged in a power supply circuit or the like.

  As long as the power supply voltage Vcc does not drop to a predetermined level, the watchdog timer of the main control unit 21 continues to function. Therefore, there is a possibility that the CPU is abnormally reset by the watchdog timer during the infinite loop process after the power interruption process is started and all processes are completed.

  However, as described above, in this embodiment, the standby process of steps ST5 to ST6 is provided, so that the backup process is not wasted. Note that the total processing time of the power monitoring process is set to be shorter than the clear pulse output cycle (2 mS), and the watchdog timer is not started until the power monitoring process is completed.

  By the way, the elapsed time τ1 from when the watchdog timer of the main control unit 21 finally receives the clear pulse until the reset signal is output to the CPU is determined by the watchdog timer of the effect control unit 22 or the image control unit 23. The elapsed time τ2 and τ3 from when the last clear pulse is received until the reset signal is output to the CPU is set to be approximately the same (τ1≈τ2≈τ3). Therefore, the watchdog timer of the main control unit 21 does not start much earlier than the watchdog timers of the other control units 22 and 23. The significance of this configuration will be described later.

  Next, the operation of the effect control unit 22 that executes the effect operation based on the control command received from the main control unit 21 will be described. As shown in FIG. 9, the production control unit 22 includes a main process (a) that is started when the CPU is reset, a reception interrupt process (b) that is activated by the strobe signal STB, and a first process that is activated every 10 mS. The timer interrupt process (c) and the second timer interrupt process (d) activated every 2 mS are included.

  As shown in FIG. 9D, in the second timer interrupt process, the lamp effect process (ST67) for driving the illumination lamp and the effect motor process (ST68) for driving the effect movable body AMU as required are 2 mS. It is executed every time. FIG. 9E shows a main part of error processing executed in CPU reset processing (main processing).

  As shown in FIG. 9A, in the main process (CPU reset process), the initial setting in the one-chip microcomputer 40 is executed (ST46), and then the backup determination process is executed (ST47). The backup determination process is a process for determining the validity of the data stored in the backup process (ST63). Data stored in the backup process (ST63) is not particularly limited. For example, (1) a sum value of a checksum operation for predetermined data in the RAM area, (2) specific data discretely stored in the RAM area, (3) Backup data in which predetermined data in the RAM area is stored in another area can be exemplified.

  In the backup determination process, it is also determined whether an important operation flag indicating the operation state is irrational. The irrationality in the operation flag is, for example, a case where both the operation flag indicating that the variation effect is being performed and the operation flag indicating that the jackpot operation is being set. In this gaming machine, after the variation effect is finished, the game shifts to a big hit operation, so the two operation flags cannot be set at the same time. If such a situation is detected, other saved data is stored. Even if legitimacy is recognized, it judges that it is not normal.

  In addition, even when the main control unit 21 is disconnected, but the direct current power supply of the effect control unit 22 is maintained, the backup determination (ST47) results in an abnormality determination through the process of step ST86 in FIG. . If the validity cannot be confirmed in the determination of step ST48, including such an exceptional case, the entire area of the RAM is initialized to cold start the production control unit 22 and the process of step ST52 is performed. Transition (ST51).

  By the way, unlike the main control unit 21 and the payout control unit 24, the production control unit 22 is not provided with a backup power supply, and therefore, it seems that there is no possibility that legitimate data can be detected in the backup determination process (ST47). However, the CPU is reset not only at the time of power reset corresponding to power-on, but also at the time of abnormal reset when the CPU reset signal becomes an active level due to noise or a watchdog timer.

  Therefore, in this embodiment, a backup determination process (ST47 to ST48) is provided in order to continue the game operation up to that time and to hot start the operation of the effect control unit 22 as much as possible when the CPU is reset abnormally. Yes.

  However, since not all data are determined in the backup determination process (ST47), the operation of the effect control unit 22 should be returned to the initial state when the CPU is repeatedly abnormally reset. Therefore, the abnormal counter is incremented (+1) to count the number of abnormal resets (ST49), and if the value of the abnormal counter exceeds a predetermined value (for example, 2), the RAM clear process in step ST51 to perform a cold start. (ST50).

  As described above, even when the CPU is abnormally reset, if the backup determination (ST47) makes a correct determination and the number of abnormal resets is equal to or less than the predetermined value, the effect control unit 22 is hot-started, and the game up to that point Operation continues.

  Subsequently, the effect control unit 22 sets the value of the motor operation flag FG of the rotary motor MT to 1 regardless of whether it is hot-started or cold-started (ST52). In addition, an abnormality flag ER indicating an abnormal state of the rotary motor MT is initialized to a normal level of 0, and an operation mode MD is initialized to 0. As will be described later, when the motor operation flag FG is set to 1, in the subsequent effect motor processing (ST68), the effect movable body AMU is driven to return to the origin position.

  Note that the return processing to the origin position is not limited to a cold start but is also performed during a hot start and does not return to the effect position of the effect movable body AMU. However, because (1) the production operation of the production movable body AMU is executed relatively rarely, and (2) the CPU is extremely rarely reset abnormally, the origin return operation is executed during hot start. There is no particular problem.

  Rather, the backup determination process (ST47) is not perfect, but if the situation that the effect movable body AMU cannot be recovered due to an erroneous hot start at the time of an abnormal reset of the CPU occurs, the effect movable body stopped at an unnatural position There is a risk that the AMU may cause discomfort to the player. In other words, if the configuration of this embodiment is adopted, the backup process (ST63) can be simplified corresponding to the simple backup determination process (ST47), and the CPU abnormality that occurs very rarely. It is possible to eliminate the waste of repeating excessive processing every 10 mS for resetting.

  Further, in an operation experiment in the development stage of a gaming machine, a configuration in which the origin detection process is always executed when the CPU is reset is very effective, which will be described later. However, as indicated by the broken line, it is not particularly prohibited to execute the process of step ST52 only during a cold start.

  When the process of step ST52 is completed, necessary initial settings are executed for the audio reproduction output circuit (audio reproduction IC) 42 (ST53). Thereafter, the CPU of the one-chip microcomputer 40 is set to the interrupt permitting state (ST54), and the random number value is updated (ST55) to wait for a timer interrupt at an interval of 10 mS (ST56). Note that the updated random value is used in the effect lottery process in order to randomize the effect operation.

  As shown in FIG. 9C, an interrupt flag is set every time a timer interrupt occurs at an interval of 10 mS (ST66). Therefore, in the process of step ST56 of the main process, it is repeatedly checked that the interrupt flag is turned ON. . When the interrupt flag is turned ON, the timer update process is executed after resetting it to OFF (ST57). The timers updated in the timer update process include an abnormality notification timer and a clear notification timer, which will be described later, and each timer is updated by a decrement (-1) process until it reaches zero.

  Subsequently, command analysis processing is executed for the control command (reception command) received in the reception interrupt processing (FIG. 9B) (ST58). The received command includes an initial operation command, a RAM clear command, a backup return command, a power interruption A command, a power interruption B command, etc. in addition to the variation pattern command.

  FIG. 10 is a flowchart showing the main part of the command analysis process. First, it is determined whether or not the newly received control command is a power interruption B command (ST80). As described above, the main control unit 21 continuously transmits the power interruption A command and the power interruption B command in this order. Therefore, when the effect control unit 22 receives the power interruption B command, And should have received a power interruption A command.

  However, since there is a possibility that the control command is erroneously transmitted due to noise, it is next determined whether or not the power interruption A command has already been received (ST81). If the power interruption command A is not received, it is considered that there is a communication abnormality such as reading out the power interruption A command or erroneous transmission of the power interruption B command. The command is discarded and the process returns to the main process (ST87).

  As described above, in this embodiment, unless the two power interruption commands are normally received, the power interruption process is not performed and the game control in the effect control unit 22 is continued. Abnormal interruptions are avoided. In addition, there is a possibility that the normally transmitted power-off command may be missed, but at best, the game control being executed only disappears suddenly at the time of power-off, and no particular problem occurs.

  By the way, when it is determined in step ST81 that the power interruption A command has been received, the power interruption A command and the power interruption B command are transmitted to the image control unit 23 in this order (ST82 to ST82). ST83).

  Next, all the lamps are turned off, and the operations of the rotary motor MT and the lift motor MO are stopped (ST84). At this time, if the effect movable body AMU is located outside the origin area, it is returned to the origin area. Therefore, after the power is turned off, the exposed state of the effect movable body AMU is not continued and the appearance is good. Further, the origin detection process (SS5) executed after the power supply is restored can be omitted or can be completed quickly.

  In this embodiment, the stop control is first executed for the lamp and the motor, so that the rate of power supply voltage drop can be suppressed and the subsequent processing can be completed with certainty.

  Subsequently, the operation of the chance button 11 is invalidated, and the sound effect is stopped and silenced so that the gaming machine does not operate abnormally when the power supply voltage drops (ST85). Next, a part of the backup data is intentionally changed and set to an interrupt disabled state (ST86), and a DC power supply is cut off while executing an infinite loop processing. The setting to the interrupt disabled state is the same processing as steps ST39 to ST40 in FIG. 8, and the count operation of the timer interrupt internal timer is stopped and the CPU is set to the interrupt disabled state.

  The backup data is data to be calculated in the backup determination process (ST47), and some data is intentionally destroyed, or an appropriate power interruption flag is changed from the reset state to the set state. Therefore, even if the DC power supply is not shut off due to a part of the backup data being modified, the operation of the effect control unit 22 is reliably performed in the initial state (cold start state) after the CPU reset by the watchdog timer. ). Since the interrupt disabled state is set, even when the DC power supply is not shut off, the timer interrupt process such as the 2 mS interrupt process (FIG. 9 (d)) is not started, and the rendering movable body AMU operates abnormally. There is nothing.

  Although the main control unit 21 has transmitted the power interruption command, it is not normally considered that the direct current power source of the effect control unit 22 is not cut off. However, (1) immediately after the AC power supply is cut off, the power supply abnormality signal ABN1 is output. (2) The voltage value of the DC power supply is maintained by a relatively large capacity capacitor, and the power consumption is large. Is immediately stopped (ST84). For example, when the AC power supply is in an instantaneous power interruption state, the direct current power supply of the effect control unit 22 may be maintained normally.

  In such a case, the infinite loop process executed after step ST86 is broken by the operation of the watchdog timer WDT and shifts to the CPU reset state. However, as described above, after the backup determination (ST47), the effect control unit 22 cold starts and returns to the initial operation (ST51). Since such a cold start operation is also realized in the image control unit 23, it is possible to particularly facilitate an operation experiment in the development stage of the gaming machine.

  Specifically, this type of gaming machine generally has a short life cycle (several months), so it is necessary to develop new models one after another, and it is necessary to urgently check the operation of the production contents. For this reason, even if the AC power supply is shut off, the fact that the DC power supply is maintained for several seconds may be a serious problem. That is, in a general gaming machine, even if the power switch for the AC power source is turned OFF → ON in order to return the production operation of the gaming machine to the initial state, unless the operation interval is secured for a long time, the production movable body AMU Does not return to the origin position and the display screen of the display device DISP remains, which becomes a major obstacle in an operation confirmation experiment.

  However, in this embodiment, when the main control unit 21 is disconnected, the RAMs of the control units 22 and 23 on the downstream side are cleared, the control operation returns to the initial state (ST51, SE6 in FIG. 17), and the origin is detected. Since the process (ST52) is also executed, even if the power switch of the AC power supply is quickly turned OFF → ON, the downstream control units 22 and 23 can be surely returned to the initial state, and an operation experiment of the rendering operation is performed. Can be repeated quickly.

  As described above, the power interruption process (ST81 to ST86) in the command analysis process of FIG. 10 has been described. If the newly received control command is the initial operation command, the initial operation command is changed to the downstream side. The image is transferred to the image controller 23 (ST89). Next, in order to perform the initial operation of the rotary motor MT, a flag setting process for a predetermined initial operation, such as setting the motor operation flag FG to 2, is executed (ST90).

  By the way, at this timing, there is a possibility that the origin detection process started due to the flag setting process (FG = 1) in step ST52 is not completed. However, even in such a case, when the motor operation flag FG is set to 2 (ST90), the origin detection process of the rotating motor MT being executed is interrupted and the initial operation process is started. However, since the same process as the origin detection process is executed in the shifted initial operation process, no problem occurs. When the motor operation flag FG is set to 2 and the abnormality flag ER = 1 and the rotation motor MT is in an abnormal state, the abnormality notification operation is started in the state of FG = 2. (Abnormality notification operation will be described later).

  On the other hand, if the newly received control command is a RAM clear command, the RAM clear command is transferred to the image control unit 23 (ST92). Next, a flag setting process for executing a RAM clear process, such as initial setting of a clear notification timer to a predetermined value (for example, 30 seconds), is executed (ST93). The RAM clear process is as shown by the broken line in FIG. 7, and all the illumination lamps are turned on by the process of step ST67, and the RAM clear sound is output as an alarm sound by the sound effect process of step ST62.

  If the newly received control command is a backup restoration command, the backup restoration command is transferred to the image control unit 23 (ST95). Thereafter, the effect control unit 22 continues the operation state at the time of power-on (lamp extinguishing, silence).

  On the other hand, after the player starts the game operation, the variation pattern command may be received. In that case, the effect command specified by the effect lottery is transmitted to the image control unit 23 (ST97). Further, a flag setting process necessary to start the production operation specified by the production command is executed (ST98).

  If the effect movable body AMU is included in the effect operation to be started, the motor operation flag FG = 0 and the retry flag RT = 0, and the rotation motor MT is not in an abnormal state (motor error). Under these conditions (ER = 0), the motor operation flag FG of the rotary motor MT is set to 3 (ST98). As a result, in the subsequent effect motor processing (ST68), a motor effect that rotates the effect movable body AMU is executed. The motor error means an abnormality in which the rotating motor MT does not rotate even after the retry process (SS4 in FIG. 11), or an abnormality in which the rotating motor MT does not function normally in the motor effect process (SS7 in FIG. 11). In either case, the abnormality flag ER = 1 is set. In this case, the motor effect for rotating the effect movable body AMU is skipped.

  In this embodiment, when the variation pattern command is received, if the motor operation flag FG = 1 and the origin detection operation is being performed, or if the retry flag RT = 1 and the retry operation is being performed, the motor The production operation is skipped. Therefore, the deficiency that the symbol effect in the image control unit 23 and the motor effect in the effect control unit 22 are not synchronized is prevented.

  By the way, although not shown in FIG. 10, the timer update process (ST57) and the command analysis process (ST58) cooperate, so that the motor operation flag FG is set to 1 in the process of step ST52. If necessary, the motor operation flag FG of the rotary motor MT is set to 1. More specifically, the motor operation flag FG returned from FG = 1 to the initial state (FG = 0) is a jackpot game at the start of the variation effect executed based on the variation pattern command or after the end of the variation effect. FG = 1 is set again at the beginning of the game, or at the start of a customer waiting demonstration that is executed a predetermined time after the player finishes the game.

  In accordance with the setting process of the motor operation flag FG, the abnormality flag ER is initialized to 0 indicating a normal state. This is because the origin detection process (SS5) is executed again at “at the start of the fluctuating effect”, “at the start of the big hit game”, or “at the start of the customer waiting demonstration”, thereby eliminating the abnormality of the rotary motor MT. This is for the purpose of illustration.

  That is, in the state where the abnormality flag ER = 1, the rotation motor MT is prohibited from being driven (SS1 in FIG. 11), but the rotation motor MT is in the non-drive state (SS9 in FIG. 11). As a result, the rotary motor MT shifts from the restrained state to the free rotating state (unconstrained state), so that the abnormal state may naturally recover due to vibration accompanying the payout of the game ball. Therefore, the return to the origin position of the rotary motor MT is attempted by the origin detection process (SS5) again. In addition, even if the origin detection process (SS5) is performed again, if an abnormality is recognized, the process proceeds to a retry process, and if the abnormality is still not resolved, the abnormality flag ER = 1 is set.

  In any case, when the command analysis processing (ST58) shown in FIG. 10 is completed, error processing is executed next (ST59). FIG. 9E shows error processing relating to a motor error of the rotary motor MT. As described above, the motor error is a state in which the abnormality flag ER = 1 and the rotation motor MT does not rotate even after the retry process (SS4), or in the motor effect process (SS7) It means an abnormality that did not function properly.

  In this embodiment, the driving process of the rotary motor MT is roughly divided into an origin detection process (FG = 1), an initial operation process (FG = 2), and a motor effect process (FG = 3) based on the motor operation flag FG. However (see FIG. 11), any of these processes may cause an abnormality in the rotary motor MT.

  However, in this embodiment, even if an abnormal situation of the motor is detected, in principle, the abnormality flag ER is only set to 1, and an initial setting command (see ST8 in FIG. 7) is sent from the main control unit 21. Unless it is received, the abnormal state is not notified. The main control unit 21 transmits an initial setting command only when the CPU is reset, so that the notification of the abnormal state is limited only when the CPU of the main control unit is reset.

  The reason for adopting such a configuration is that (1) the production movable body AMU operates rarely as a notice operation, and its importance is low compared to a game ball payout motor, etc. (2) Therefore, There is no urgent need to promptly notify the abnormality and dispatch the staff, (3) If the abnormality is reported without darkness, the player who is playing will be whitened and distrustful, (4) The rotating motor MT will rotate Even if it is impossible, it is based on the reason that, after that, it may be restored naturally based on vibrations associated with the payout of game balls.

  As described above, in this embodiment, the abnormality notification of the rotary motor MT is limited to when the CPU of the main control unit 21 is reset (typically, power reset), and therefore the motor error detected when the power is turned on. The notification does not disappear due to another notification operation executed thereafter. For example, if a motor error detected at the time of power-on is immediately notified by voice, the voice notification by the RAM clear command received after that causes the motor error voice notification to disappear and the attendant may overlook the abnormality of the rotary motor MT. .

  On the other hand, the fact that the RAM clear process (ST18) may be abused by an unauthorized player is as described with reference to FIG. 7, and therefore the RAM clear voice notification is extinguished and the motor error is notified by voice. This is very inappropriate for security and cannot be adopted.

  In order to realize the abnormality notification operation as described above, in the error process (ST59), as shown in FIG. 9 (e), first, the value of the abnormality flag ER is determined (ST69). If the abnormality flag is ER = 1, it is determined whether or not the value of the motor operation flag FG at that time is 2 (ST70). If the motor operation flag FG ≠ 2, then the other error processing is skipped regardless of the occurrence of a motor error (ER = 1).

  The reason why such an operation procedure is adopted is that the motor error of the rotary motor MT is not notified abnormally only after the initial setting command is received from the main control unit 21. The motor operation flag FG is automatically set to FG = 2 when receiving an initial setting command from the main control unit 21 (ST90 in FIG. 10), on condition that the abnormality flag ER = 0 (SS40), The execution of the initial operation process shown in FIGS. 14 to 15 is started.

  Therefore, the case where it is determined in step ST70 that the motor operation flag FG = 2 is executed when a motor error has occurred in the initial operation processing of FIGS. 14 to 15 or after the previous power-on. In the origin detection process (FIG. 13), either a motor error has already occurred.

  In any case, if the motor operation flag FG = 2, it is determined whether or not a notification start command related to a motor error has been transmitted to the image control unit 23 following the processing of step ST70. (ST71). If not yet transmitted, an abnormality notification timer for managing the abnormality notification time (for example, 60 seconds) is initialized (ST76), and a notification start command is transmitted to the image control unit 23 (ST77). In response to the notification start command, the image control unit 23 displays, for example, “servant error” superimposed on the image being displayed on the display device DISP.

  After the abnormality notification operation is started in this way, in the error processing (ST59) after the next time, the value of the clear notification timer is determined following the determination in step ST71 (ST72). The clear notification timer manages the clear notification time (= 30 seconds) executed after receiving the RAM clear command, and is initially set in the process of ST93 in FIG.

  Then, until the clear notification time expires, the motor control abnormality notification process (voice notification) in the effect control unit 22 is not started. This is because the RAM clear notification is surely continued for the abnormality notification time (30 seconds) with priority given to the RAM clear voice notification in consideration of illegal games and the like. If the clear notification time expires, the voice notification regarding the motor error is executed until the abnormality notification timer expires (ST74). If the abnormality notification timer expires, the voice notification of the motor error is terminated and the motor operation is completed. The flag FG is returned to 0 in the initial state (ST75). However, the abnormality flag ER remains at 1.

  Thus, the completion of the voice notification of the motor error does not mean that the motor error has been eliminated. However, since the voice notification of the motor error is executed before the opening of the game hall, it is sufficient for the staff who rushed to the gaming machine to solve the motor abnormality and to turn off the power switch of the gaming machine. It is understood.

  On the other hand, even if the motor error state is left unattended, since the abnormality flag ER = 1, the rotary motor MT is maintained in the free rotation state, and the “variation effect start”, “variation effect end”, “big hit” Since the origin detection process (SS5) is executed again at the time of the “game start” or “at the start of the customer waiting demonstration”, the abnormality of the rotary motor MT may be naturally resolved. In the worst case, only the notice operation by the effect movable body AMU is not executed, and there is no particular adverse effect.

  When the error processing (ST59) as described above is completed, next, input processing for the chance button 11 is executed as necessary (ST60). Further, an effect scenario for the lamp effect (ST67), the effect motor process (ST68) and the sound effect (ST62) is created or updated (ST61). Next, an audio effect based on the created or updated effect scenario is executed (ST62). The audio effects include a motor error audio notification operation based on the abnormality notification timer and a RAM clear audio notification operation based on the clear notification timer. However, as shown in steps ST72 to ST73 of FIG. 9 (e), the RAM clear voice notification has priority, and therefore, when two voice notification operations overlap, a motor error abnormality notification sound is not output. However, since the initial value of the abnormality notification timer is set to be sufficiently larger than the initial value of the clear notification timer (twice in the embodiment), virtually no problem occurs.

  When the sound effect (ST62) including the abnormality notification process is completed, the process proceeds to the process of step ST54 after the backup process (ST63) is executed. Examples of the backup processing include not only checksum calculation but also processing for storing specific data discretely, processing for storing all data in the work area, and the like.

  Following the backup process, a clear process of the watchdog timer WDT is also executed. In this way, in the effect control unit 22, the watchdog timer WDT is cleared at 10 mS intervals, so the elapsed time τ2 from when the watchdog timer WDT last receives a clear pulse until the reset signal is output to the CPU is It is sufficiently longer than 10 mS.

  Subsequently, the effect motor process (ST68 in FIG. 9D) executed every 2 mS will be described with reference to FIGS.

  As shown in FIG. 11, in the production motor process, the value of the abnormality flag ER is first determined (SS1). If the abnormality flag ER = 1, the non-driving data is output to the driver circuit 45B and the process ends ( SS9). In this embodiment, the non-driving data is 0000 having a 4-bit length, and the rotary motor MT maintains a stopped state in an unconstrained state where free rotation is possible.

  On the other hand, if the abnormality flag ER = 0, the value of the retry flag RT is determined (SS2). The retry flag RT is set to RT = 1 in an origin detection process (SS5), an initial operation process (SS6), or the like when, for example, the effect movable body AMU cannot return to the origin area due to idling of the rotation motor MT. If the abnormality is not improved even by the retry process (SS4) executed in the state of the retry flag RT = 1, the abnormality flag ER is set to 1 and the process ends abnormally. On the other hand, when the abnormality is improved and the process ends normally, the retry flag RT = 0.

  Therefore, if it is determined in step SS2 that the retry flag RT = 0, then the value of the motor operation flag FG is determined (SS3). As described above, the motor operation flag FG is roughly classified into FG = 1 where the origin detection process is executed, FG = 2 where the initial operation process is executed, and FG = 3 where the motor effect process is executed.

  Here, the origin detection process (SS5) is (1) when the CPU of the effect control unit is reset, (2) when the variable effect starts, (3) when the variable effect ends, (4) when the big hit game starts, (5) the customer It is executed at the start of a waiting demonstration. Prior to the origin detection process (SS5), the motor operation flag FG = 1 and the abnormality flag ER = 0 are initialized (for example, ST52 in FIG. 9).

  Then, in the origin detection process (SS5), as shown in detail in FIG. 12, if the effect movable body AMU was originally located in the origin area or moved from the outside of the origin area to the origin position, it ended normally. The motor operation flag FG = 0. On the other hand, if the normal operation cannot be continued in the origin detection process (SS5), the retry flag RT = 1 is set and the process ends abnormally. In the subsequent effect motor process, a retry process (SS4) is executed.

  On the other hand, in the initial operation process (SS6) in which the motor operation flag FG = 2 is set by the process in step ST90 in FIG. 10, the execution is started on the condition that the abnormality flag is ER = 0 at the start timing. (See SS40 in FIG. 14). In this initial operation process, when the effect movable body AMU moves to the origin position, the normal operation ends and the motor operation flag FG = 0 is set. Conversely, if normal operation cannot be continued, the motor operation flag FG = 2 is maintained, the retry flag RT = 1 is set, and the process proceeds to the retry process (SS4).

  If the abnormality flag ER = 1 at the timing when the motor operation flag FG = 2 is set, a motor error abnormality notification process is started as shown in steps ST71 to ST77 in FIG.

  As described with respect to the process of step ST98 in FIG. 10, the motor effect process (SS7) is started on the condition that the retry flag RT = 0, the motor operation flag FG = 0, and the abnormality flag ER = 0. A movable effect of the movable body AMU is executed. When the movable effect ends normally, the motor operation flag FG = 0 is set.

  On the other hand, if the movable effect cannot be continued normally, the process is terminated with the abnormality flag ER = 1. Then, since the abnormality flag ER = 1, the subsequent motor performance is prohibited unless the abnormality is recovered.

  However, as described above, (1) not only when the CPU of the effect control unit is reset, but (2) at the start of the variable effect, (3) at the end of the variable effect, (4) at the start of the big hit game, (5) The origin detection process is executed at the start of the customer waiting demonstration effect, and if the normal operation cannot be continued in the origin detection process, the process proceeds to the retry process, so that the possibility that the abnormality of the rotary motor is automatically recovered is not low.

  The outline of the rendering motor process has been described above, and the specific processing content will be described below. The variables used in the program are summarized as shown in the lower column of FIG. That is, the count counter CNT defines the rotation angle of the rotation motor MT, the direction flag DR defines the forward and reverse rotation directions of the rotation motor MT, and the operation mode flag MD manages the progress of the control operation.

  As is clear from FIG. 9D and FIG. 11, in the state of the abnormality flag ER = 0 and the retry flag RT = 0, the process after step SS3 is repeatedly executed every 2 mS. The origin detection process (SS5), the initial operation process (SS6), and the motor effect process (SS7) are started corresponding to the value of the motor operation flag FG (= 1 to 3). In this case, the operation mode MD = 0.

  First, the origin detection process (SS5) will be described with reference to FIG. First, the detection signal SN from the photo interrupter PH is acquired and stored (SS10). Next, the operation mode MD is determined (SS11). If MD = 0 in the initial state, the level of the detection signal SN is determined (SS12).

  As described with reference to FIG. 5, the detection signal SN indicates whether or not the rotating member ROT is located in the origin region. Therefore, when the detection signal SN = H and the rotating member ROT is located in the origin region, the motor operation flag FG is returned to the initial state FG = 0 and the process is normally terminated (SS13). In this case, the rotating member ROT may not be located at the correct origin position, but the effect movable body AMU is accommodated at least at a position where the player does not touch the eyes.

  As described above, in the embodiment of FIG. 12, the rotating member ROT is not driven as long as the effect movable body AMU is located in the origin region at the time of CPU reset. However, in order to reliably detect an abnormality in the rotating member ROT, an inspection process for confirming the operation of the rotating member ROT may be provided prior to the normal end process in step SS13.

  The inspection process is executed by, for example, temporarily moving the rotating member ROT from the origin area ORG to the outside of the origin area and then collecting it in the origin area ORG. Specifically, for example, in steps SS56 to SS67 in FIG. Realized by processing. In this case, the process of step SS66 is replaced with the process of step SS13. In addition, the abnormality detection state (ER = 1) may be set by the processing in steps SS61 and SS67, but instead, the retry flag RT = 1 and the operation mode MD = 0 are set, and the retry processing (SS4) in FIG. ).

  The modified example of the process in step SS13 has been described above, but the description will be continued below by returning to the example. When the detection signal SN = L at the time of determination of step SS12 executed at the time of CPU reset and the rotating member ROT is located outside the origin region, the value of the count counter CNT is set with a sufficient margin and the lap time Initially set to a value corresponding to twice M (SS14). As described above, the lap time M is the elapsed time from when the rotating member ROT rotates at the constant speed V until it reaches the origin again, and in this embodiment, the timer interruption time interval. 245 * τ corresponding to τ. Therefore, the count counter CNT is initialized to 490 corresponding to the time for which the rotating member ROT rotates twice.

  In addition, the direction flag DR is set to 0 to specify that the direction is rotated in the reverse direction (counterclockwise in FIG. 5) and the operation mode MD is set to 1 (SS14). The above process is a process for returning the rotating member ROT to the origin region by the next timer interruption. Note that the initial value of the count counter CNT does not necessarily need to be 490, and may be a value that is appropriately larger than one round (= 245).

  Since the operation mode MD = 1, in the next timer interruption, it is determined whether or not the detection signal SN has become the H level through the path of step SS11 → SS15 → SS16 (SS16). If the rotating member ROT has not yet returned to the origin region and the detection signal SN = L, the drive data is advanced by one step in the DR direction every predetermined time, and the count counter CNT is decremented correspondingly. (SS18). Note that the updated drive data is supplied to the rotary motor MT in the process of step SS8 in FIG. 11, whereby the rotary member ROT is driven to rotate.

  By the way, the drive data of the present embodiment is 4-bit length 0101, 1001, 1010, 0110, and the update timing is determined based on the rotation speed V of the rotating member ROT. If the drive data is updated every two timer interruption processes (= 4 mS), in the configuration of this embodiment, the rotating member ROT rotates once in 4 mS * 245 = 0.98 seconds. .

  Thus, if the process of step SS18 is repeated and the rotary member ROT is stepped forward, the rotary member ROT will eventually return to the origin region and the detection signal SN = H. Therefore, in that case, the count counter CNT is newly initialized to a value (N2 / τ) corresponding to the backward reference time N2 (SS19). As described above, the reverse reference time N2 is an elapsed time from when the rotating member ROT rotating at the constant speed V returns to the origin area to the origin position.

  Further, the direction flag DR is maintained at 0, and the operation mode MD is set to 2 (SS19). The above process is a process for accurately returning the rotating member ROT that has entered the origin area to the origin position by the next timer interruption.

  On the other hand, when the detection signal SN = L, the processes in steps SS17 to SS18 are further repeated. When the detection signal SN = L is maintained and the count counter CNT initialized in step SS14 reaches 0, the retry flag RT = 1 is set and the processing is ended with the operation mode MD = 0. (SS20).

  This means that an abnormality has been detected in which the rotating member ROT cannot return to the origin region even though the driving operation for two rotations has been executed for the rotating motor MT. Therefore, in the next timer interrupt, the retry process (SS4) is executed with the motor operation flag FG = 1 maintained (see FIG. 11).

  On the other hand, in the timer interruption after the process of step SS19 is executed, the value of the count counter CNT is determined through the path of step SS11 → SS15 → SS21 (SS21). If the count counter CNT ≠ 0, the drive data is advanced in the DR direction every predetermined time, and the count counter CNT is decremented correspondingly (SS22).

  Then, at the timing when the count counter CNT = 0, the operation mode MD = 0 and the motor operation flag FG = 0 are set, and the origin detection process is normally terminated (SS23). In the configuration of this embodiment, it cannot be determined whether or not the rotating member ROT has reached the origin position accurately, but it is understood that it is sufficient if the rotating member ROT is accommodated in the origin region.

  Next, the retry process will be described with reference to FIG. The retry process (SS4) is started when the retry flag RT = 1 is set in the origin detection process (SS5), the initial operation process (SS6), or the motor process (SS7). At the start, the operation mode MD = 0 is set.

  Therefore, in the retry process (SS4), as shown in FIG. 13, the operation mode MD is first determined (SS24), and if the operation mode MD = 0, the count counter CNT is initialized to an appropriate value XX, and the direction After setting the flag DR = 1, the operation mode is set to MD = 1 (SS25). The direction flag DR = 1 means that the rotation direction is the forward direction, and usually means a direction away from the origin region.

  Since the operation mode MD is set to 1, the value of the count counter CNT is determined in the next timer interruption through the path of step SS24 → SS26 → SS27 (SS27). If the count counter CNT ≠ 0, the drive data is advanced by one step every predetermined time, and the count counter CNT is decremented correspondingly (SS28).

  If such processing is repeated, the count counter CNT will eventually become 0. In this case, the value of the count counter CNT is newly initialized to a value corresponding to twice the circulation time M. (SS29). Further, the direction flag DR = 0 and the operation mode MD = 2 are set (SS29). Therefore, in the next timer interruption process, the rotating member ROT rotates in the reverse direction toward the origin region. This is because after driving a predetermined number of times (= XX) in the forward direction (SS25 to SS28), the reciprocating motion is performed in the reverse direction so far, thereby eliminating the abnormality of the rotary motor MT.

  By setting the operation mode MD = 2, in the next timer interruption, the detection signal SN is acquired through the path of step SS24 → SS26 → SS30 → SS31 (SS31), and its level is determined (SS32). When the detection signal SN = H and the rotating member ROT enters the origin region, the count counter CNT has a value corresponding to the reverse reference time N2 (N2 / τ) to further move to the origin position. ) Is newly initialized (SS35). Further, the direction flag DR is maintained at 0, and the operation mode MD is set to 2 (SS35).

  On the other hand, if the detection signal SN is not H, the value of the count counter CNT is determined (SS33). If the count counter CNT ≠ 0, the drive data is advanced by one step in the DR direction every predetermined time, and this is handled. The count counter CNT is decremented (SS34).

  If the detection signal SN = L is maintained even if the stepping operation is repeated, it is determined that the restoration is no longer possible and the abnormality flag ER = 1 is set while the retry flag RT = 1 is maintained. Then, the process is finished (SS36).

  As a result, thereafter, until the abnormality flag becomes ER = 0, the rotary motor MT is in a non-driven state, and the rotary member ROT is maintained in a stopped state. Note that in the origin detection process (SS5) executed at the start of the fluctuating effect, the abnormality flag ER = 0 and the motor operation flag FG = 1 are set at the start, so the retry process (SS4) is executed again. .

  If the retry process is successful, the origin detection process (SS5) is re-executed after the retry flag RT = 0 (SS39). Since the retry process is successful, the origin detection process is immediately terminated normally (see SS10 to SS13 in FIG. 12).

  On the other hand, if the retry process fails again, the abnormality flag ER = 1 again (SS36), and the rotary motor MT is not driven until the origin detection process is performed again (see SS9 in FIG. 11). In this embodiment, when the abnormality flag ER = 1, the rotary motor MT is in a non-driven state, and the retry process is repeatedly executed at the start of the fluctuation effect or at the start of the customer waiting demonstration effect. The possibility that the abnormality will be automatically recovered is not low. Note that even if the retry process fails, the abnormality notification operation is not executed, so that the player is not distrusted.

  The items related to the process of step SS36 have been described in detail above. However, after the process of step SS35 is executed, the value of the count counter CNT is determined through the path of step SS24 → SS26 → SS30 → SS37 ( SS37) If the count counter CNT ≠ 0, the drive data is advanced by one step in the DR direction every predetermined time, and the count counter CNT is decremented correspondingly (SS38).

  When the count counter CNT = 0, the retry flag RT = 0 and the operation mode MD = 0 are set, and the retry process is normally terminated (SS39).

  Next, the initial operation process (SS6) shown in FIGS. 14 to 15 will be described. The initial operation process is started upon receiving an initial operation command from the main control unit 21 (ST90 in FIG. 10). If the abnormality flag ER = 1 in this state, the process is immediately terminated (SS40). Such a situation occurs when a motor error occurs in the origin detection process, but thereafter, an abnormality notification operation that continues for a predetermined time is executed by the process after step ST71 in FIG. 9E.

  On the other hand, if the abnormality flag ER = 0, the process of obtaining the detection signal SN (SS41), determining the operation mode MD (SS42), and determining the level of the detection signal SN (SS43) is executed. If the detection signal SN = H, the rotating member ROT is positioned in the origin region, so the count counter CNT is initialized to a value corresponding to two rotations of the rotating member ROT (= 2 * M / τ). The direction flag DR = 1 and the operation mode MD = 3 are initially set, and the process is completed.

  On the other hand, if the operation mode MD ≠ 0 or the detection signal SN = H, the process from step SS42 is executed. The process of steps SS42 to SS53 is substantially the same as the process of steps SS11 to SS22 (except for SS13) in the origin detection process. Accordingly, the rotating member ROT located outside the origin area is reversely rotated to enter the origin area, and thereafter, the rotating member ROT is reversely rotated by the reverse reference time N2 to return the rotating member ROT to the origin position.

  FIG. 15 shows the processing content after the processing of FIG. 14 is finished. First, the operation mode MD is determined. If the operation mode MD = 3, the detection signal SN is determined (SS56 to SS57). The operation mode MD = 3 is the same as the origin detection process (SS5) when the rotating member ROT is already located in the origin area (SS43 → SS54) from the start of the initial operation process (SS6). Then, the rotation member ROT is returned to the origin position (SS52 → SS54).

  In either case, the forward rotation operation is defined by the process of step SS54 (DR = 1). Therefore, when the operation mode MD = 3, the detection signal SN is determined, and it is confirmed whether or not the rotating member ROT located in the origin area has escaped outside the origin area (SS57). If it has escaped outside the origin area (detection signal SN = L), the count counter CNT is further set to a value corresponding to two rotations of the rotating member ROT (= 2 * M / τ) in order to continue the forward rotation. To the direction flag DR = 1 and the operation mode MD = 4 (SS60).

  On the other hand, when the rotating member ROT is still located in the origin area (detection signal SN = H), the forward rotation of the rotating member ROT is continued while the count counter is decremented as long as the count counter CNT ≠ 0. (SS59).

  If the detection signal SN does not become L even after this operation continues, the processing is performed with the motor operation flag FG = 2 and the abnormality flag ER = 1 at the timing when the count counter CNT = 0. Finish (SS61). This state means an abnormality in which the rotating member ROT located in the origin area cannot be escaped from the origin area no matter how it is driven. In the case of this abnormality, the process is not shifted to retry processing. However, since the rotating member ROT is located in the origin region, the effect movable body AMU is normally hidden from the player, so that no particular problem occurs.

  In any case, since the abnormality flag ER = 1, the rotation motor MT stops in a non-driven state thereafter. Then, since the motor operation flag FG = 2 is maintained, the abnormality notification operation after step ST71 in FIG. 9E is started.

  On the other hand, after the process of step SS60 is executed, the detection signal SN is determined through the path of step SS41 → SS45 → SS51 → SS56 → SS62 → SS63 (SS63). When the detection signal SN = H, it means that the rotating member ROT has re-entered the origin area from outside the origin area.

  Therefore, the count counter CNT is newly initialized to a value (N1 / τ) corresponding to the forward reference time N1 (SS66). Further, the direction flag DR is maintained at 1, and the operation mode MD is set to 5 (SS66).

  On the other hand, if the detection signal SN is not H, the value of the count counter CNT is determined (SS64). If the count counter CNT ≠ 0, the drive data is advanced one step in the DR direction every predetermined time, and this is dealt with. The count counter CNT is decremented (SS65).

  If the detection signal SN = L is maintained even after repeating the stepping operation, the abnormality flag ER = 1 is set while the motor operation flag FG = 2 is maintained, and the process ends (SS67). ).

  This state means an abnormality in which the rotating member ROT that has escaped out of the origin area cannot be re-entered into the origin area no matter how it is driven. Even in the case of this abnormality, the process is not shifted to the retry process. However, (1) the initial operation process (SS6) is executed only when the CPU of the main control unit is reset (mostly when the game hall is opened), (2) the motor operation flag FG = 2 and the abnormality flag ER Since the abnormality notification operation is started from the condition of = 1 (see FIG. 9E), there is no practical adverse effect. That is, it is considered that an attendant of the game hall takes appropriate measures in response to the abnormality notification operation.

  By the way, after the process of step SS66 is executed, the value of the count counter CNT is determined through the path of step SS41 → SS45 → SS51 → SS56 → SS62 → SS68 (SS68). If the count counter CNT ≠ 0, the forward rotation until then is continued (SS69), and the operation mode MD = 0 and the motor operation flag FG = 0 are returned at the timing when the count counter CNT = 0. The process ends (SS70). In this state, the rotating member ROT is located at the origin position.

  The rotation motor MT that rotates the rotating member ROT in the forward and reverse directions has been described above with reference to FIGS. However, the basic operation is the same even in the case of a lifting motor MO that reciprocates the movable member MV. That is, in the operations of FIGS. 12 to 14, the forward reference time N1 and the reverse reference time N2 in the rotary motor MT are all read as the reference time N.

  However, since the initial operation process is characterized in the operation of the latter half, the following description will be made on the lifting motor MO that drives the rack and pinion mechanism based on FIG.

  In the initial operation process (SS6), the lifting motor MO is controlled in the same manner as in FIG. 14 in order to accommodate the movable member MV in the origin region. Then, after the accommodating operation is successful, the process proceeds to the operation of FIG. 16 and waits for the detection signal SN = L in the state of the operation mode MD = 3 (SP56 to SP59). This process means determination of whether or not the movable member MV accommodated in the origin area has moved in the forward direction and the left end of the movable member MV has escaped from the origin area to the outside of the origin area.

  When the escape is successful, the count counter CNT is initialized to a value (MN) / τ corresponding to time (MN) (SP60). M is a movement time required for moving the movable range L from the time when the left end of the movable member MV leaves the origin-side mechanical lock until the right end of the movable member MV comes into contact with the end-point mechanical lock. Is the reference time required for the left end of the movable member MV to reach the origin position after entering the origin area.

  In step SP60, the direction flag DR = 1 and the operation mode MD = 4. As shown in FIG. 6, the movement time (MN) means an elapsed time until the right end of the movable member MV that has escaped from the origin region reaches the MAX position on the end point side. Therefore, in the state in which the operation mode MD has shifted to 4, while waiting for the right end of the movable member MV to reach the MAX position while determining the value of the count counter CNT (SP63 to SP64).

  When the right end of the movable member MV reaches the MAX position, the counter CNT is initialized to a value corresponding to the time of 2 * M, and the direction flag DR = 0 and the operation mode MD = 5 ( SP65). This is an initial operation for returning the movable member MV that has reached the MAX position to the origin direction.

  Thereafter, it waits for the left end of the movable member MV to re-enter the origin region. If re-entry, the counter CNT is initialized to a value corresponding to the reference time N and the direction flag DR = 0 is maintained. Thus, the operation mode MD is set to 6 (SP71). This is an initial operation for returning the left end of the movable member MV that has re-entered the origin area to the origin position. Thereafter, the initial operation ends at the timing when the count counter CNT = 0 (SP75).

  On the other hand, when the count counter CNT = 0 in the state of the detection signal SN = L, the processing is terminated with the abnormality flag ER = 1. This state is an abnormality in which the movable member MV could not be collected in the origin region, but a repair by an attendant is expected in response to an abnormality notification process started thereafter.

  By the way, even if the processes of steps SP56 to ST59 shown in FIG. 16 are repeated, the left end of the movable member MV may not escape from the origin area to the outside of the origin area. Specifically, there is a possibility that the state of the detection signal SN = H continues and the count counter CNT = 0. Therefore, when such an abnormality occurs, the count counter CNT is initialized to a value corresponding to 2 * M, and the direction flag DR = 0 and the operation mode MD = 7 are set (SP61).

  This is an initial operation for moving the movable member MV that cannot escape from the origin region to the origin side as much as possible, so as to reliably hide the effect movable body from the player. Thereafter, the movable member MV is driven in the reverse direction until the count counter = 0, the abnormal flag ER = 1 is set, and the process ends (SP78). Also in this case, an abnormality repair work by a staff member based on the abnormality notification process started thereafter can be expected.

  Since the production control unit 22 has been described in detail above, the operation of the image control unit 23 will be described next. The image control unit 23 includes a main process (FIG. 17) that is started when the CPU is reset, a reception interrupt process (not shown) that is activated by a strobe signal STB, and a timer interrupt process (not shown) that is activated every 10 mS. ) And.

  As shown in FIG. 17, the main process of the image control unit 23 is similar to the main process of the effect control unit 22 shown in FIG. That is, the processing of steps SE1 to SE6 is substantially the same as the processing of steps ST46 to ST51 in the effect control unit 22. The same is true in that the processing in steps SE7 to SE14 is repeatedly executed at intervals of 10 mS. The clear pulse is also supplied to the watch dog timer WDT of the image control unit 23 at intervals of 10 mS.

  However, since the image control unit 23 receives the control command transmitted or transferred by the effect control unit 22 and executes the image control operation, there is no process corresponding to step ST52 in FIG. Therefore, after hot start or cold start, the CPU is set to interrupt permission (SE7) and waits for 10 mS to elapse while updating the random number value (SE6). Then, every 10 mS, timer update (SE10), command analysis (SE11), error process (SE12), effect scenario update (SE13), and backup process (SE14) are executed.

  FIG. 18 is a flowchart showing a main part of the command analysis process (SE11). When the power interruption command is received in the reception interrupt process (SE20), it is determined whether the power A command has already been received (SE21). This corresponds to the transmission processing in steps ST82 to ST83 in FIG. 10, and when the operation is normal, the power interruption A command should be received in advance. However, if the power interruption command A has not been received, it is determined that there is a communication abnormality or the like, and the process ends (SE24). This process is the same as the command analysis process of FIG.

  On the other hand, if the power interruption A command has already been received, it is determined that the main control unit 21 has executed the power interruption process, and the liquid crystal screen is made black in preparation for the subsequent interruption of the DC power supply (SE22). ). Next, a part of the backup data determined in the backup determination process (SE2) is altered, set to the CPU interrupt disabled state, and the infinite infinite loop process is repeated (SE23). These processes are the same as those in step ST86 in the effect control unit 22.

  Thereafter, the power supply voltage is expected to be cut off. However, if the DC power supply is maintained due to an instantaneous power interruption or the like, a CPU reset is generated by the watchdog timer, and the process of step SE1 in FIG. Be started. However, since a part of the backup data is damaged, as a result of the backup determination (SE2), the image control unit 23 always performs a cold start. Therefore, the past screen is not re-displayed on the display device, and even when the power switch is quickly turned OFF → ON at the time of game machine development or the like, the operation experiment is not hindered. It should be noted that the elapsed time τ3 from when the watchdog timer WDT of the image control unit 23 receives the clear pulse lastly until the reset signal is output to the CPU is sufficiently longer than the main processing repetition period of 10 mS. is there.

  By the way, when the notification start command about the motor error is received in the reception interrupt process, the image control unit 23 also initializes the notification timer to 60 seconds. This is a process corresponding to the fact that the effect control unit 22 does not transmit a notification end command about a motor error.

  Corresponding to the reception of the notification start command, initial setting for displaying a notification screen such as “objects error” is performed (SE27), and then the timer update process (SE10) is repeated while maintaining the notification screen. When the notification timer reaches 0, the notification screen is automatically extinguished. In addition, since the notification screen is a character display and is overwritten on the previous screen, other display screens will not disappear.

  In this embodiment, the production control unit 22 transmits the notification start command only when the CPU of the main control unit 21 is reset, so in fact, the notification is displayed on the screen indicating whether the RAM is cleared or the backup is restored. The screen will be displayed in duplicate.

  When an initial operation command is received from the production control unit 22, an initial setting for displaying the screen as “PLEASE WAIT” is made (SE29). When a RAM clear command or a backup return command is received, “ Initial settings are made to display the effect symbols of “7”, “3”, and “1” and the notification screen “Return from power failure. Please start playing” (SE31, SE33). When an effect command is received, initial setting for starting the corresponding image effect is performed (SE35).

  FIG. 19 illustrates the operations of the main control unit 21, the effect control unit 22, and the image control unit 23 when the gaming machine is turned on. When the power is turned on (T0), the CPU is reset based on the reset signal output from the reset circuit RST of the main controller 21, and the operation of FIG. 7 is started.

  Further, the CPUs of the effect control unit 22 and the image control unit 23 are reset based on the system reset signal SYS (FIGS. 3 and 4) supplied from the power supply board 20, respectively, and FIG. 9A and FIG. The operation shown in 17 is started. As a result, in the image control unit 23, after the RAM clear process is executed through the path of step SE1, SE2, SE3, and SE6, “POWER ON” is displayed on the display device DISP.

  On the other hand, the main control unit 21 transmits an initial operation command at a timing T1 (ST8 in FIG. 7). Upon receiving the initial operation command, the effect control unit 22 transfers this to the image control unit, and the effect movable body An initial operation for driving the AMU is started (ST88 to ST90 in FIG. 10). The image control unit 23 that has received the initial operation command displays “PLEASE WAIT” on the display device DISP.

  Thereafter, the main control unit 21 transmits a RAM clear command (ST19) or a backup return command (ST15) at timing T2. And the presentation control part 22 which received the control command transfers this to an image control part, and starts the operation | movement according to a control command. For example, when a RAM clear command is received, a RAM clear sound is output for 30 seconds based on a clear control timer that is initially set to 30 seconds, and the illumination lamp is maintained in a fully lit state. Note that when the initial operation of the rotary motor MT is continued, the operation is not affected.

  Further, the image control unit 23 starts an operation based on the control command transferred from the effect control unit 22. Specifically, the appropriate screen display described above is started.

  Incidentally, when a trouble (motor error) occurs in the operation of the effect movable body AMU, the operation shown in FIG. 20 is executed. For example, FIG. 20A shows a case where an initial operation command is received during the operation of origin detection processing. In such a case, since the motor operation flag FG = 1 is rewritten from FG = 2 (ST90 in FIG. 10), the origin detection process (SS5) being executed is abandoned and the initial operation process (SS6) is started. (Timing T1).

  Thereafter, when the effect control unit 22 receives the RAM clear command (timing T2), the effect control unit 22 continuously outputs the RAM clear notification sound for 30 seconds in parallel with the initial operation process (SS6). To do. During the RAM clear notification time, all the illumination lamps are turned on.

  Here, it is assumed that the initial operation process (SS6) does not proceed normally, the process shifts to the retry process (SS4), and a motor error state occurs at timing T3. Then, the effect control unit 22 secures a motor error notification time (for example, 60 seconds) (ST76), and transmits a notification start command to the image control unit 23 (ST77 in FIG. 9). Then, although a motor error notification operation is started, since the RAM clear notification is given priority (ST72), after the 30-second RAM clear notification ends, a motor error notification sound is output.

  On the other hand, the image control unit 23 that has received the notification start command displays a character “Error” on the display screen at that time. Therefore, the RAM clear notification using the notification lamp, the notification sound, and the notification screen will not disappear due to a motor error that occurs thereafter.

  Next, FIG. 20B shows a case where a motor error has occurred during the operation of the origin detection process (SS5). In such a case, the origin detection process ends with the abnormality flag ER = 1 (SS36 in FIG. 13). Then, when the production control unit 22 receives the initial operation command (timing T1), the motor operation flag FG = 2 is set, and notification time management is started together with the generation of a motor error notification sound (ST76). Further, a notification start command is transmitted to the image control unit (ST77).

  After that, when the effect control unit 22 receives the RAM clear command at the timing T2, it transfers this to the image control unit 23 and starts outputting the RAM clear sound as the illumination lamp is turned on. The RAM clear sound is output instead of the motor error notification sound. However, in this embodiment, the motor error notification time is set sufficiently longer than the RAM clear sound notification time. The situation where it is not output does not occur.

  In addition, as described above, the image control unit 23 that has received the transfer of the RAM clear command displays an appropriate screen so as to overlap the character display such as “object error”. Then, the image control unit 23 and the effect control unit 22 continue the notification operation while updating each abnormality notification timer, and terminate the motor error notification operation when the notification time expires.

  In this way, in this embodiment, the abnormality notification time is managed in each of the control units 22 and 23, so that there is no trouble as in the case of terminating the notification operation based on the stop command from the upstream side. . For example, during the motor error notification operation, even if the effect control unit 22 is abnormally reset and cold-started, the character display such as “object error” cannot continue to be displayed without disappearing.

  The same applies to the RAM clear sound output from the effect control unit. For example, no trouble occurs even when the AC power supply is cut off immediately after the main control unit 21 transmits a RAM clear command after the power is turned on. In such a case, the direct current power supply of the effect control unit and the image control unit may be maintained normally, but the RAM clear sound and the illumination lamp automatically disappear when the clear notification timer expires. Therefore, there is no trouble that the RAM clear operation is maintained and the motor error notification sound cannot be output.

  Note that the above-described momentary power interruption of the AC power supply occurs not only when the AC power supply is unstable, but also when the power switch is quickly turned on and off for an operation confirmation experiment in the development stage of the gaming machine.

  By the way, the system reset signal SYS of the present embodiment is generated by the DC power supply in the power supply board 20. Therefore, even if the AC power supply is momentarily stopped, the system reset signal SYS is not generated when the AC power supply is restored as long as the DC power supply is maintained on the power supply board. Therefore, the CPUs of the effect control unit 22 and the image control unit 23 are not reset when the AC power supply is instantaneously stopped, and thus various configurations of the present embodiment are particularly effective.

  In this embodiment, the elapsed time τ1 from when the watchdog timer of the main control unit 21 receives the clear pulse lastly until the reset signal is output to the CPU is determined by the effect control unit 22 and the image control unit 23. The elapsed time τ2 and τ3 from when the watchdog timer finally receives the clear pulse until the reset signal is output to the CPU is set. Further, an appropriate time consumption process is provided when the CPU of the main control unit 21 is reset (ST3 to ST4 in FIG. 7).

  In order to explain the significance of this point, when the AC power supply is instantaneously stopped, the main control unit 21 transmits a power interruption command, starts execution of the infinite loop processing of FIG. 8, and receives the power interruption command. It is assumed that the control unit 22 and the image control unit 23 also start executing the infinite loop processing of FIG. 10 and FIG.

  Normally, the DC power supply is cut off after that, but when the AC power supply is quickly restored, the DC power supplies of the control units 21 to 23 are maintained, so that the watchdog timers of the control units 21 to 23 are activated. When activated, the CPU of each control unit is reset. In the following description, the elapsed times τ1 to τ3 until the watchdog timer is activated are referred to as margin times.

  Here, in the case of a conventional gaming machine, the timer interrupt process of the main control unit 21 is executed every 2 mS, and the effect process of the other control unit is executed every 10 mS. Is τ1 >> τ2≈τ3. Therefore, the main control unit 21 is reset by the CPU much faster than the other control units 22 and 23, and the initial operation command (ST8) transmitted by the main control unit 21 is transmitted to the downstream control units 22 to 23. Could be missed.

  However, in this embodiment, the margin times τ1 to τ3 of the respective watchdog timers are set to the same level, and the main control unit 21 is provided with an appropriate time consumption process (ST3 to ST4). There is no possibility that the downstream control units 22 to 23 will miss the initial operation command transmitted by the control unit 21.

  The margin times τ1 to τ3 do not necessarily have to be set to the same level. If the standby time in the time consumption process (ST3 to ST4) is sufficiently long, for example, the condition of τ1 >> τ2≈τ3 is maintained. You can also

  Next, the circuit configuration of the power supply substrate 20 will be described. FIG. 21 is a circuit diagram showing a power supply circuit of the power supply board 20. This power supply circuit includes a second power supply unit SD that generates a DC voltage supplied to the production interface board 27, and a first power supply unit FR that generates a DC voltage supplied to the main control unit 21 and the payout control unit 24. A power monitoring unit MNT that monitors power-on and power-off, and a power-cut-off unit CUT that cuts off the ground line when an excessive AC voltage is received. Note that illustration of other DC voltages (DC 32 V) supplied to the payout control unit 24 and other DC voltages (DC 32 V, DC 15 V) supplied to the production interface board 27 is omitted.

<Second power supply unit SD>
The second power supply unit SD includes a full-wave rectifier circuit including diodes D1 to D4, a smoothing capacitor C1, a DC-DC converter that generates a DC voltage VB (12V), and a DC-DC that generates a DC voltage Vcc (5V). The converter includes smoothing capacitors C2 and C3. Each of the two DC-DC converters is a chopper type, and operates in common with the smoothing capacitor C1. The direct-current voltage generated by the second power supply unit SD is transmitted to the effect interface board 27 and then stepped down as appropriate to be used by the effect interface board 27, the effect control board 22, and the image control board 23. Is done.

<First power supply FR>
The first power supply unit FR generates a full-wave rectifier circuit using diodes D1, D2, D5, and D6, a smoothing capacitor C4, a DC-DC converter that generates a DC voltage VB (12V), and a DC voltage Vcc (5V). The power storage unit BK is configured by a DC-DC converter, smoothing capacitors C5 and C6, a diode D7, and a capacitor Cb. These two DC-DC converters are also of a chopper type and operate in common with the smoothing capacitor C4. The DC voltage generated by the power storage unit BK serves as a backup power supply BAK that holds data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24.

  The DC voltage VB and the DC voltage Vcc generated by the first power supply unit FR are supplied only to the main control unit 21 and the payout control unit 24, and the DC voltage transmitted to the effect interface board 27 is on the wiring. It is distinguished. Therefore, the main control unit 21 and the payout control unit 24 are not connected to the other sub-control units 22 and 23 via the power line, and transmission of high-frequency noise and the like is prevented.

  The total current in the main control unit 21 and the payout control unit 24 does not exceed 600 mA on the power supply voltage VB line and does not exceed 300 mA on the power supply voltage Vcc line. The voltage drop of the VB and Vcc power supply lines is not a problem at all.

<Power cutoff unit CUT>
The power cut-off unit CUT corresponds to the rectifying unit 51 that generates a DC voltage of a predetermined level from the AC voltage AC24V, the AC monitoring unit 52 that is turned on when the AC power supply lines LN1 and LN2 are overvoltage, and the AC monitoring unit 52 that is turned on. And a switch circuit 53 that performs an OFF operation.

  The rectifier 51 includes a diode D12 that receives an AC voltage from the AC power supply line LN2, a current limiting resistor R1, and a parallel circuit of a capacitor C8 and a Zener diode ZD2, which are connected in series. During normal operation, the voltage across the capacitor C8 is constant at the breakdown voltage of the Zener diode ZD2.

  The switch circuit 53 includes a MOS transistor Q2 having a large current capacity and a bias resistor R5 connected in parallel to the capacitor C8. Here, the transistor Q2 is in an ON state as long as the voltage across the capacitor C8 is at a predetermined level, and connects the ground line of all the circuits of the gaming machine and the frame ground FG.

  The AC monitoring unit 52 includes two diodes D8 and D9 connected to the AC power supply lines LN1 and LN2, a Zener diode ZD1 connected to the connection point of the diodes D8 and D9, a bias resistor R2 and R3, and a capacitor C7 in parallel. The circuit includes a transistor Q1 that is turned on when the voltage across the bias resistor R3 increases, and a current limiting resistor R4 of the transistor Q1.

  Zener diode ZD1 is normally in an OFF state, but when an excessive AC voltage (for example, AC 100V) is applied to AC power supply lines LN1 and LN2, it enters a breakdown state. In this breakdown state, the voltage at both ends of the bias resistor R3 increases and the transistor Q1 is turned on, so that the voltage at both ends of the capacitor C8 decreases.

  Then, the transistor Q2 that has been in the ON state until then is turned OFF, whereby the circuit ground and the frame ground FG are disconnected, and all the power supply voltages of all the gaming machines are cut off. The operation content of the power cut-off unit CUT is as described above. When the voltage across the AC power supply lines LN1 and LN2 exceeds the limit value, the power cut-off unit CUT functions to cut off all the power supply voltages of all the gaming machines at once.

<Power supply monitoring unit MNT>
Next, the power supply monitoring unit MNT will be described. The power supply monitoring unit MNT includes a power supply monitoring unit 54 that monitors the voltage levels of the AC power supply lines LN1 and LN2, a comparison voltage unit 55 that receives the power supply voltage Vcc and outputs a comparison reference voltage Vo, and a power supply monitoring unit 54. An abnormality detection unit 56 that detects a power supply abnormality by comparing output voltages of the unit 55 and a power supply reset unit 57 that generates a system reset signal SYS are configured.

[Power supply monitoring unit 54]
The power supply monitoring unit 54 includes two diodes D10 and D11 connected to the AC power supply lines LN1 and LN2, a series circuit of a resistor R6 and a Zener diode ZD3 connected to a connection point of the diodes D10 and D11, and a Zener diode ZD3. A series circuit of a diode D13 and a smoothing capacitor C9 connected in parallel, a series circuit of resistors R7 and R8 connected in parallel to the smoothing capacitor C9, and a comparator A3 that short-circuits the resistor R8 are configured.

  In this embodiment, the breakdown voltage of the Zener diode ZD3 is about 5.1V, and the Zener diode ZD3 receives the AC voltage AC24V through the current limiting resistor R6. For this reason, when the AC input power supply is in a power supply state, the voltage across the smoothing capacitor C9 is a constant value of about 4.5V. Since the resistance values of the two resistors R7 and R8 are set to R8 >> R7, the both-ends voltage Vs of the resistor R8 is about 4.5V corresponding to the normal level AC voltage AC24V. However, if the output of the comparator A3 is at L level, the voltage Vs across the resistor R8 is substantially 0V correspondingly. The resistor R7 functions as a current limiting resistor for the comparator A3 when the L level is output.

  The comparator A3 is composed of a QUAD comparator (NJM2901) together with other comparators A1 to A4. The QUAD comparator includes four comparators A1 to A4, but any of the comparators A1 to A4 is an open collector type (see FIG. 23 (i)).

  The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A3, and the comparison voltage V1 of about 2.8V is supplied to the plus terminal in the steady state. The comparison voltage V1 is generated by dividing the two types of power supply voltages Vcc and VB generated by the first power supply unit FR with resistors.

  As will be described later, when the power is turned on, the output voltage Vo of the comparison voltage unit 55 becomes a level corresponding to the power supply voltage Vcc whose level is rising (Vo = Vcc−Vf−Δ). Vf and Δ are voltage drops in the diodes D14 and D15 and the resistor R9.

  On the other hand, since the comparison voltage V1 is generated by dividing the power supply voltages Vcc and VB, immediately after the power is turned on, it is lower than the output voltage Vo of the comparison voltage unit 55. Therefore, in a transient state immediately after the power is turned on, the output of the comparator A3 becomes L level to short-circuit the resistor R8. As a result, the output voltage Vs of the power supply monitoring unit 54 becomes almost 0V.

  On the other hand, in a steady state in which the power supply voltages Vcc and VB have reached a predetermined level, the comparison voltage V1 is about 2.8V, while the output voltage Vo of the comparison voltage unit 55 is kept constant at about 2.5V. That is, the comparator A3 has a magnitude relationship of [input voltage to plus input]> [input voltage to minus terminal], but the output part of the comparator A3 is an open collector (see FIG. 23 (i)). Since the output terminal is not pulled up as shown in FIG. 21, the output part of the comparator A3 is opened and does not affect other circuits.

  The operation of the power supply monitoring unit 54 described above is organized as follows.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the resistor R8 is short-circuited by the output part of the comparator A3, so that the voltage Vs across the resistor R8 becomes approximately 0V.

  (2) Thereafter, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 is approximately 4.5 V corresponding to the voltage across the Zener diode ZD3. It becomes.

  (3) When the AC voltage AC24V is cut off, the voltage Vs across the resistor R8 quickly drops to 0V. However, even if the AC voltage AC24V is cut off, the power supply voltages Vcc and VB maintain a predetermined level for a while, so that the output unit of the comparator A3 maintains the open state as it is.

[Comparison voltage unit 55]
The comparison voltage unit 55 includes diodes D14 and D15 that receive two power supply voltages Vcc and Vcc generated separately by the first power supply unit FR and the second power supply unit SD at respective anode terminals, and cathodes of the diodes D14 and D15. A current limiting resistor R9 connected to the terminal and the voltage generator GN are connected in series. In this embodiment, a shunt regulator (HA17431: RENESAS) is used as the voltage generator GN.

  This shunt regulator has an anode terminal A, a cathode terminal K, and a comparison terminal REF. In the state shown in the figure, in which the anode terminal A and the cathode terminal K are connected, the shunt regulator functions in the same manner as a Zener diode. A constant reference voltage Vo (2.5 V) is output between the anode and cathode terminals (see FIG. 23 (h)). On the other hand, during the non-breakdown operation, the internal circuit is turned OFF, and the anode and cathode terminals are opened.

  Therefore, when the power is turned on, until the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 (voltage generation unit GN) corresponds to the power supply voltage Vcc whose level is rising, Vo = Vcc−Vf. −Δ. On the other hand, when the power supply voltage Vcc reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 becomes a constant comparison reference voltage (2.5 V).

[Abnormality detection unit 56]
The abnormality detection unit 56 includes a comparator A1 that generates a power supply abnormality signal ABN1 to the main control unit 21, a comparator A2 that generates a power supply abnormality signal ABN2 to the payout control unit 24, and pull-up resistors R10 of the comparators A1 and A2. , R11 and a capacitor Cs connected between the input terminals of the comparators A1, A2. The output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminals of the comparators A1 and A2, and the voltage Vs across the resistor R8 is supplied to the plus terminal. The comparators A1 and A2 are built in the QUAD comparator (NJM2901) described above.

  Although not shown, power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 are supplied to input ports of the main control unit 21 and the payout control unit 24. An appropriate capacitor is connected between the input terminal of each input port and the ground, and each input port receives a power supply abnormality signal via an appropriate resistor to ensure noise resistance. . Further, the influence of spike noise is eliminated by appropriate software processing (ST30 to ST31 in FIG. 8).

  Since the power supply monitoring unit 54 operates as described above in (1) to (3), the abnormality detection unit 56 operates as follows in response to this.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the voltage Vs across the resistor R8 is almost 0V, while the output voltage Vo of the comparison voltage unit 55 corresponds to the power supply voltage Vcc whose level is rising. Vcc−Vf−Δ. Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 stably maintain the L level without changing the level. Timings T0 to T1 in FIG. 23C indicate a stable L level state when the power is turned on.

  (2) Thereafter, after the power supply voltage Vcc whose level is rising exceeds a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltage Vcc increases to near the normal level, the output part of the comparator A3 is opened, so that the voltage Vs across the resistor R8 becomes approximately 4.5V corresponding to the voltage across the Zener diode ZD3.

  Therefore, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 transition to the H level, and thereafter the H level indicating the normal state is constantly maintained. After timing T1 in FIG. 23 (c), power supply abnormality signals ABN1, ABN2 at normal levels are shown.

  (3) Thereafter, when the AC voltage AC24V is cut off for some reason, the voltage Vs across the resistor R8 quickly drops to 0V. However, since the power supply voltages Vcc and VB are maintained at a predetermined level for a while, the comparator A3 and the comparison voltage unit 55 maintain the operation so far.

  Therefore, when the AC voltage AC24V is cut off at the timing T7 in FIG. 23A, the power supply abnormality signals ABN1 and ABN2 output from the comparators A1 and A2 immediately transition from the H level to the L level to cause an abnormal situation. Indicates occurrence. The main control unit 21 and the payout control unit 24 regularly check the power supply abnormality signals ABN1 and ABN2, and immediately confirm that the power supply abnormality signals ABN1 and ABN2 have transitioned to the L level. It is supposed to start.

[Power reset unit 57]
Next, the power reset unit 57 composed of the comparator A4 will be described. As illustrated, a pull-up resistor R12 is connected to the output terminal of the comparator A4, and a series circuit of a resistor Rf and a capacitor Cf is connected between the output terminal and the plus terminal. Further, the output voltage Vo of the comparison voltage unit 55 is supplied to the minus terminal of the comparator A4, and the comparison voltage V2 of about 2.95V is supplied to the plus terminal in the steady state. The comparison voltage V2 is generated by dividing the two types of power supply voltages Vcc and VB generated by the second power supply unit SD with resistors.

  Since the power reset unit 57 is configured as described above, it operates as follows.

  (1) Immediately after the power is turned on when the AC voltage AC24V is turned on, the output voltage Vo of the comparison voltage unit 55 becomes Vcc−Vf−Δ corresponding to the power supply voltage Vcc whose level is rising. On the other hand, since the comparison voltage V2 is generated by dividing the power supply voltages Vcc and VB of the second power supply unit SD, it is lower than the output voltage Vo during the level increase. Therefore, in such a transient state, the system reset signal SYS output from the comparator A4 becomes L level (see FIG. 23A).

  (2) Thereafter, after the power supply voltage Vcc whose level is rising reaches a predetermined level, the output voltage Vo of the comparison voltage unit 55 is maintained at 2.5V. Further, when the power supply voltages Vcc and VB increase to near the normal level, the comparison voltage V2 approaches the steady value 2.95V. Therefore, the system reset signal SYS output from the comparator A4 transitions from the L level to the H level at an appropriate timing.

  The system reset signal SYS generated in this way is transmitted to the effect control unit 22 and the image control unit 23 via the effect interface board 27, and is provided in each control unit 22 and control unit 23. The power of the CPU and other ICs is reset via the delay circuit. Note that the series circuit of the resistor Rf and the capacitor Cf also exhibits a function of delaying the transition operation.

  FIG. 22A is a circuit diagram showing the reset circuit RST arranged in the main control unit 21 and the payout control unit 24. In this embodiment, the reset circuit RST is configured by utilizing the power supply voltage monitoring IC 1 (MB3771 Fujitsu Microelectronics) and the power supply voltage monitoring IC2 with a watchdog timer function (MB3773 Fujitsu Microelectronics).

  As shown in the equivalent circuit of FIG. 22B, the power supply voltage monitoring IC 1 includes two comparators CompA and CompB. The plus terminals of the two comparators CompA and CompB are set to about 1.24V by the built-in circuit.

  In the circuit configuration of the embodiment, since the Vsa terminal is connected to the ground via the capacitor C11, the potential of the negative terminal of the comparator CompA is divided by the built-in resistor and becomes about 1.4V. . On the other hand, since the power supply voltage VB is divided and supplied to the Vsb terminal by external voltage dividing resistors R20 and R21, the potential of the Vsb terminal is VB * R21 / (R20 + R21). A voltage stabilizing capacitor C12 is connected in parallel to the resistor R21. A delay capacitor C10 is connected to the Ct terminal.

  Since the power supply voltage monitoring IC 1 has the internal circuit of FIG. 22B, when the power supply voltage Vcc rises to a predetermined level after the power is turned on (see timing T2 of FIG. 23D), it is built in. Charging of the delay capacitor C10 is started by the constant current source. Until the delay capacitor C10 is charged to a predetermined level (see T3 in FIG. 23E), the basic reset signal RS1 output from the reset terminal is maintained at the L level. The reset hold time Tpo [S] is Tpo [S] = 105 * C10 [F] corresponding to the capacitance of the external capacitor C10.

  In this way, the basic reset signal RS1 that has become H level at the timing T3 maintains that level unless the power supply voltages Vcc and VB drop. However, the potential of the Vsb terminal is VB * R21 / (R20 + R21), and the level of the power supply voltage VB is monitored at this Vsb terminal. Similarly, the potential of the Vsa terminal is Vcc * 40 / (40 + 1001) corresponding to the built-in resistors 40 kΩ and 100 kΩ, and the level of the power supply voltage Vcc is monitored at this Vsa terminal.

  For this reason, when the voltage level of both or one of the power supply voltages Vcc and VB drops due to the interruption of the AC input AC 24V or the failure of the power supply units FR and SD (see timing T8 in FIG. 23 (d)), Any output terminal of CompB transitions to the H level. Then, the built-in flip-flop is set, and the basic reset signal RS1 output from the reset terminal immediately falls to the L level (see timing T8 in FIG. 23E).

  By the way, in this embodiment, a capacitor C11 is connected between the Vsa terminal and the ground, and a capacitor C12 is connected between the Vsb terminal and the ground. As is apparent from the equivalent circuit of FIG. 22B, these capacitors C11 and C12 have a function of delaying the operation of the internal circuit, and the power supply voltages Vcc and VB are reduced to, for example, 4 V or less for a short time. The basic reset signal RS1 is not output in the instantaneous power failure state or the instantaneous power interruption state.

  In this embodiment, Cll = C12 = 1000 pF is set, and in response to this, in the instantaneous interruption state or instantaneous interruption state where the level drop of the DC voltage (5V, 12V) recovers within 40 μS, The voltage monitoring IC 1 is configured not to react. Therefore, even if spike noise within a pulse width of 40 μS is superimposed on any of the power supply lines of the power supply voltages Vcc and VB supplied from the power supply substrate 20, the basic reset signal RS1 is not abnormally output.

  Corresponding to the power supply voltage monitoring IC 1 operating as described above, the basic reset signal RS1 is sent to the main control unit 21 and the payout control unit 24 as an I / O reset signal via the two NOT gates G1 and G2. It is supplied to the reset terminal of the mounted data input / output IC. Preferably, a basic reset signal (I / O reset signal) RS1 is supplied to a data input / output IC having a latch function. Therefore, the data of the data input / output ICs (for example, SN74273, SN74LV8155, etc.) latched at random when the power is turned on is surely cleared by the basic reset signal RS1.

  The basic reset signal RS1 bar via the NOT gate G1 is supplied to the power supply voltage monitoring IC 2 with a watchdog timer function. As shown in the figure, the power supply voltage monitoring IC 2 outputs a CPU reset signal RS2, but a delay capacitor C15 is connected to the Ct terminal of the power supply voltage monitoring IC 2, and a clear pulse is sent from the one-chip microcomputer to the CK terminal. Configured to be supplied.

  The Vs terminal of the power supply voltage monitoring IC 2 is connected to the ground via the capacitor C14, and the collector terminal and the emitter terminal of the transistor Q3 are connected in parallel to the capacitor C14. The base reset signal RS1 bar divided by the bias resistors R23 and R24 is supplied to the base terminal of the transistor Q3.

  The contentor C14 is a delay element that delays the operation of the internal circuit. As in the case of the power supply voltage monitoring IC1, by appropriately setting the capacitance of the capacitor C14, the power supply voltage monitoring IC2 may be configured not to react in the power supply voltage Vcc instantaneously interrupted state or instantaneously stopped state. it can.

  The power supply voltage monitoring IC 2 has the internal circuit of FIG. 22C, and when the Vs terminal is in an open state, the potential of the Vs terminal is set to about 1.4 V by a built-in resistor. The Vs terminal is connected to the minus terminal of the built-in comparator CompS, and a voltage of about 1.24 V is supplied to the plus terminal of the comparator CompS by the built-in circuit.

  Hereinafter, the operation of the power supply voltage monitoring IC 2 will be described. Since the basic reset signal RS1 bar is at the H level during the period after the power is turned on until the timing T3 (see FIG. 23F), the transistor Q3 is turned on. State. Therefore, the potential of the Vs terminal of the power supply voltage monitoring IC 2 is 0 V, and the output of the comparator CompS becomes H level.

  However, when the basic reset signal RS1 bar transits to L level and the transistor Q3 enters the OFF state at timing T3, the output of the comparator CompS transits to L level, so that the built-in flip-flop enters the reset state and delays. The charging operation to the capacitor C15 is started. Then, after the delay capacitor C15 is charged to a predetermined level (see timing T4 in FIG. 23 (g)), the CPU reset signal RS2 changes from the L level to the H level.

  While the CPU reset signal RS2 is at the L level, the reset terminal of the one-chip microcomputer is maintained at the L level, so that the CPU core and others are surely reset. The reset hold time Tpr [mS] is Tpr [mS] = 1000 * C15 [μF] corresponding to the capacitance of the external capacitor C15.

  In this power supply voltage monitoring IC 2, the watchdog timer circuit built in the power supply voltage monitoring IC 2 starts to operate at the timing when the CPU reset signal RS 2 transitions to the H level and the one-chip microcomputer starts operating. It is configured.

  Therefore, after that, the watchdog timer function is exhibited. Specifically, when the operation of the one-chip microcomputer is started, the power supply voltage monitoring IC 2 starts the discharge operation of the delay capacitor C15. Every time the one-chip microcomputer supplies a clear pulse, the discharge of the delay capacitor C15 is started. The operation switches to the charging operation.

  However, when trouble such as program runaway occurs (see timing T5 in FIG. 23 (g)), the discharging operation of the delay capacitor C15 is continued, and when the potential of the Ct terminal drops to about 0.4V, the CPU The reset signal RS2 is forcibly transitioned to the L level. Thereafter, the CPU reset signal RS2 is maintained at the L level. However, when the CPU reset signal RS2 returns to the H level after the elapse of the predetermined maintenance time Twr, the CPU executes an initial processing program similar to that in the power-on state. To start. The duration Twr [mS] is Twr [mS] = 20 * C15 [μF] corresponding to the capacity of the delay capacitor C15.

  Next, the operation of the power supply voltage monitoring IC 2 when the power is shut off will be described. When the power supply voltage Vcc drops to a predetermined level (4.2 V), the CPU reset signal RS2 changes to the L level (timing T8 in FIG. 23 (g)). Thereafter, the operation of the watchdog timer circuit is prohibited.

  By the way, in this embodiment, the watchdog timer circuit built in the one-chip microcomputer is not utilized, and an external dedicated IC 2 is used. This is because when the CPU runs out of control, it is impossible to deny the possibility that some kind of abnormality has occurred in the built-in circuit of the one-chip microcomputer.

  Further, in this embodiment, the power supply voltage monitoring IC 1 and the power supply voltage monitoring IC 2 are arranged in an overlapping manner, and the power supply reset signal (CPU reset signal) RS2 output from the power supply voltage monitoring IC 2 is used only for the one-chip microcomputer. The power supply reset signal (basic reset signal) RS1 output from the power supply voltage monitoring IC 1 is supplied only to the data input / output IC other than the one-chip microcomputer. The CPU reset signal RS2 generated by the watchdog timer function of the power supply voltage monitoring IC 2 is supplied only to the one-chip microcomputer. The reason for adopting such a configuration is as follows.

  First, since the ball game machine of the present embodiment has a power backup function, the game before the power interruption (before the previous day or before a power failure) may be resumed when the power is turned on. Therefore, when the power is turned on, in particular, it is necessary to reliably reset the data input / output IC having a latch function. However, since the reset hold time is short enough, the power supply reset signal (basic reset signal) RS1 is generated using the power supply voltage monitoring IC1.

  On the other hand, for the one-chip microcomputer, a sufficient reset hold time is required after the power supply voltages Vcc and VB are stabilized. For the reason described above, it is preferable to provide a watchdog timer circuit externally, and a desired reset hold time is required for the CPU reset signal RS2 by the watchdog timer. Therefore, in this embodiment, the power supply voltage monitoring IC 1 and the power supply voltage monitoring IC 2 are connected in series to generate a power reset signal (CPU reset signal) RS2 having an optimal reset hold time (= Tpo + Tpr). At the same time, the CPU reset signal RS2 when an abnormality occurs is generated using the power supply voltage monitoring IC2. The reset hold time is set to an optimum value in each of the main control unit 21 and the payout control unit 24 in consideration of the initial processing time after the CPU reset. Therefore, for example, the control command is not transmitted during the initial processing operation of the payout control unit 24. However, if the main control unit 21 is clearly longer than the payout control unit in the initial processing time, the reset hold time is set to be the same.

  When an abnormality occurs due to program runaway or the like, the basic reset signal RS1 is not generated, so the data input / output IC is not reset. However, unlike when the power is turned on, random data is not latched in the data input / output IC at the time of abnormal reset, and at the time of abnormal reset, the RAM clear process is executed and the game operation is resumed. There is no problem in not resetting the data input / output IC.

  On the other hand, if the power supply voltage (VB, Vcc) is momentarily interrupted for a short time, but continues to such an extent that it cannot be absorbed by the capacitors Cll, C12, the basic reset signal RSl is output from the power supply voltage monitoring 1Cl. Is done. The basic reset signal RS1 turns on the transistor Q3 for a short time. However, by setting the ON resistance of the transistor Q3 to an appropriate value and setting the capacitor C14 connected in parallel to the transistor Q3 to an appropriate capacitance, it is possible to avoid the output of the CPU reset signal RS2.

  In such a case, only the data input / output IC is reset. In particular, this reset operation is performed when the power supply voltage VB (12 V) used for generating a switch signal such as a symbol start port is This is effective in that only the data input / output IC is cleared when the instantaneous power failure state occurs.

  As mentioned above, although the Example of this invention was described concretely, the concrete description content does not specifically limit this invention.

  For example, in the embodiment, the effect movable body AMU is rotationally driven in the effect control unit 22, but it is needless to say that the effect movable board A and the main control board may be rotationally driven instead of this configuration. Of course, the gaming machine that executes the movable effect is not limited to the ball game machine, and the present invention can also be suitably applied to a slot machine (rotating game machine) and the like.

GM gaming machine 21 main control unit 22 sub control unit 20 power supply unit AMU production movable body ST54-ST63 steady process ST48-ST50 maintenance process ST52 production reset process

Claims (10)

The lottery process resulting from the predetermined switch signal is executed, and the game operation is controlled centrally based on the lottery result, and the storage content of the volatile memory updated in accordance with the progress of the game operation is The player is configured to have a main control unit that can be maintained even after the DC power supply is cut off, and a sub control unit that executes an effect operation based on an instruction from the main control unit. A gaming machine capable of shifting to an advantageous gaming state,
The main control unit is configured to transmit an initial operation command when the CPU is reset,
The sub-control unit is an initial process that is executed when the CPU of the sub-control unit is reset, and a steady process that is repeatedly executed after the initial process is finished and advances the presentation operation while updating the storage content of the volatile memory, Configured with
In the initial processing of the sub-control unit, the storage content of the volatile memory is determined based on the predetermined data of the volatile memory, and if the storage content is valid, the storage of the volatile memory is performed under a predetermined condition. While a maintenance process is provided to maintain the content,
The steady process of the sub-control unit is provided with a backup process for writing predetermined data in a volatile memory, and an effect reset process for returning the effect operation to the initial state when an initial operation command is received. Machine. The main control unit is configured to stop the progress of the game operation in response to the interruption of the AC power supplied to the gaming machine, and to transmit a power interruption command indicating that to the sub-control unit,
When the sub-control unit receives the power-off command, the sub-control unit stops the progress of the rendering operation, and after writing the data whose validity is denied in the determination process to the volatile memory, the sub-control unit is disconnected from the DC power The gaming machine according to claim 1, wherein the gaming machine is configured to wait.   The game according to claim 1 or 2, wherein when the number of maintenance processes exceeds a predetermined value, the stored contents of the volatile memory are erased even if the stored contents are valid. Machine.   A first reset circuit for forcibly resetting the CPU of the main control unit when the gaming operation is not proceeding normally, and a CPU of the sub control unit when the rendering operation is not proceeding normally A game machine according to any one of claims 1 to 3, further comprising a second reset circuit that forcibly abnormally resets.   The sub-control unit controls a movable effect by the effect movable body, and in the effect reset process, the effect movable body is driven to accommodate the effect movable body in the origin region. Game machines.   The sub-control unit operates based on an instruction received from the main control unit via the upstream sub-control unit and an upstream sub-control unit that operates based on an instruction from the main control unit. The gaming machine according to any one of claims 1 to 5, wherein the gaming machine is divided into a downstream sub-control unit that operates based on the system.   The gaming machine according to claim 6, wherein the upstream sub-control unit includes the maintenance process and the effect reset process.   The gaming machine according to claim 7, wherein the downstream sub-control unit has a process equivalent to a maintenance process of the upstream sub-control unit.   The gaming machine according to any one of claims 6 to 8, wherein the downstream sub-control unit executes a presentation operation using a display device, and the upstream sub-control unit outputs a sound signal and executes the presentation operation. .   The gaming machine according to any one of claims 1 to 9, further comprising a power supply reset circuit that detects an AC power supply and outputs a system set signal to the sub-control unit.