CN109889209A - A kind of rate adaptation type ldpc decoder suitable for aerospace communication - Google Patents
A kind of rate adaptation type ldpc decoder suitable for aerospace communication Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a kind of rate adaptation type ldpc decoders suitable for aerospace communication, it include: input data processing module, iteration decoding module and output data processing module, input data processing module includes Frame Synchronization Test unit, FIFO memory and null frame fills unit, data flow input frame synchronous detection unit, Frame Synchronization Test unit does Frame Synchronization Test to data, and synchronous data frame is sent into FIFO memory, according to the full status indication and empty status flags of FIFO memory, null frame fills unit is sent into iteration decoding module from FIFO memory read data frame or filling null frame；After iteration decoding module decodes, output data processing module does hard decision to the data after iterative decoding and framing exports.The present invention realizes the decoding operation of single master clock self-adaptive processing data with different rate by filling null frame to input data.
Description
Technical field
This application involves the Error Correction of Coding of digital communication technology field more particularly to a kind of rates suitable for aerospace communication
Self-adaptation type ldpc decoder.
Background technique
Digital signal will appear mistake due to being influenced by noise and interference in transmission process, and channel coding technology is made
To guarantee that the effective means of information reliable transmission is widely used in various communication systems, low density parity check code (Low-
Density Parity Check Code, LDPC) proposed earliest by Gallager, Mackay et al. further study showed that,
The performance of LDPC code can be close to shannon limit (Shannon under belief propagation (Belief Propagation) decoding algorithm
Limit), and there is lower error floor, is one of the aerospace communication error correction pattern that CCSDS recommends.
LDPC code is a kind of linear block codes, its check matrix is a very sparse matrix, the non-zero in matrix
The quantity of element is seldom with respect to for ranks length.If every a line (or column) of check matrix has identical nonzero element,
Claiming this LDPC code is regular, otherwise referred to as abnormal LDPC code.Due to element 1 in the check matrix of irregular LDPC codes
Position not have rule substantially can be followed, and cause encoding and decoding complexity high, realize that difficulty is big.And regular LDPC code, especially quasi- circulation rule
Then LDPC (QC-LDPC) code can complete coding and decoding using simple shift register, and hardware complexity substantially reduces.
(8160,7136) LDPC code as defined in CCSDS belongs to one kind of QC-LDPC code, the decoder architecture of QC-LDPC code
There are mainly three types of:
Serial decoding: all row (column) operations are completed by reusing 1 CFU and VFU arithmetic element, occupy resource
At least, but needs many clock cycle could complete primary complete row (column) update.
Full parellel structure: by configuring an arithmetic element for each row (column), and make the parallel work of all arithmetic elements
Make to improve arithmetic speed, it is minimum only to need 2 clock cycle that complete 1 interative computation, but need to consume very much
Hardware resource, chip are difficult to support.
Semi-parallel architecture: the quasi-cyclic feature of QC-LDPC check matrix is utilized, semi-parallel architecture can be used, will verify
Matrix is divided into several sub-blocks, and the node of each sub-block is mapped to a hardware processing element, passes through in each iterative process
A sub- block check node and variable node arithmetic element are repeated to calculate the outer letter of a sub- block check node and variable node
Breath, the information update of all nodes are successively completed by this sub-block endpoint processing unit, and this structure can obtain serially
With parallel compromise.
During decoder for decoding, due to successive ignition operation need to handle master clock be slightly above input data with when
Clock needs to provide high-frequency clock by hardware phase-locked-loop if master clock is obtained by 2 frequency multiplication of input data accompanying clock,
For the decoding operation of different input data rates, then mutually in requisition for different hardware phase-locked-loops, therefore, it is necessary to complicated clocks
Switch logic is just able to satisfy the decoding operation demand of different input data rates.
For this reason, it may be desirable to a kind of ldpc decoder of rate adaptation type is provided, on the basis of realizing LDPC decoding function,
The decoding operation that arbitrary velocity data are supported by single master clock does not need clock and switches, the control logic of simplified decoding device,
Improve the reliability of decoder.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of rate adaptation type LDPC suitable for aerospace communication
Decoder, comprising: input data processing module, iteration decoding module and output data processing module, wherein
The input data processing module includes Frame Synchronization Test unit, FIFO memory and null frame fills unit, data
Stream inputs the Frame Synchronization Test unit, and the Frame Synchronization Test unit does Frame Synchronization Test to data:, will if frame synchronization
Synchronous data frame is sent into the FIFO memory and otherwise resets the FIFO memory, null frame fills unit, iterative decoding
Module and output data processing module；According to the full status indication and empty status flags of the FIFO memory, the null frame is filled out
It fills unit and is sent into the iteration decoding module from the FIFO memory read data frame or filling null frame；The FIFO memory
Reading label sent after being delayed to the output data processing module；
The iteration decoding module is iterated decoding to the data frame of input, and the data frame after iterative decoding is sent into
The output data processing module；
The output data processing module is done hard decision and framing to the data after iterative decoding and is exported, while by the reading
Take label as data validity flag position with output.
Preferably, the null frame fills unit includes original state, reads data fifo state and filling null frame state,
In,
Original state: the full status indication for detecting FIFO memory is " 1 ", and empty status flags are " 0 ", is denoted as sta=
10, FIFO, which is in, at this time can be read state, start to read data fifo, and start a 13 bit wide counters；Wherein, sta
First is full status indication, and second is empty status flags；
It reads data fifo state: starting to read FIFO memory data, if detection sta=00 or sta=10, after resuming studies
Take FIFO memory data；If there is illegal state sta=11, original state is jumped to；If detecting sta=01 and counter
Num=8192 then jumps to filling null frame state；
Fill null frame state: data are read empty in FIFO memory, fill whole frame format sky data to guarantee that coding module is defeated
Enter continuous.If detecting sta=01 or sta=00, null frame is continued to fill up；If there is illegal state sta=11, leap to just
Beginning state；If detecting sta=10 and counter num=8192, jumps to and read data fifo state.
Preferably, the iteration decoding module is using amendment Min-Sum decoding algorithm.
Preferably, taking normaliztion constant is 0.75 in the operation of variable node to check-node.
Preferably, the iteration decoding module includes control unit, described control unit carries out at every frame data frame head
Mistake caused by single-particle inversion is limited in present frame by forced resetting.
Compared with prior art, there are following technical effects by the present invention:
1, the present invention is by filling null frame to input data, and is data validity flag in output data, realizes single
The decoding operation of master clock self-adaptive processing data with different rate eliminates clock switching system complicated under different rates；
2, the present invention has decoder and receives error number by combining to input data format judgement and reset processing
According to rear self-recovering function；
3, the present invention terminates to improve the anti-list of decoder to all register reset processing modes by every frame data operation
Particle overturns performance.
Certainly, it implements any of the products of the present invention and does not necessarily require achieving all the advantages described above at the same time.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it is therefore apparent that drawings in the following description are only some embodiments of the invention, for ability
For field technique personnel, without creative efforts, it is also possible to obtain other drawings based on these drawings.It is attached
In figure:
Fig. 1 is the structural block diagram for the rate adaptation type ldpc decoder that the embodiment of the present invention is suitable for aerospace communication；
Fig. 2 is Frame Synchronization Test state flow chart of the embodiment of the present invention；
Fig. 3 is the state transition diagram of null frame fills unit of the embodiment of the present invention；
Fig. 4 is iteration decoding module work flow diagram of the embodiment of the present invention；
Fig. 5 is variable node functional unit working principle diagram of the embodiment of the present invention；
Fig. 6 is the working principle diagram of check-node functional unit of the embodiment of the present invention.
Specific embodiment
Below with reference to attached drawing to a kind of rate adaptation type LDPC decoding suitable for aerospace communication provided by the invention
Device is described in detail, and the present embodiment is implemented under the premise of the technical scheme of the present invention, gives detailed implementation
Mode and specific operating process, but protection scope of the present invention is not limited to following embodiments, and those skilled in the art are not
In the range of changing spirit of that invention and content, can it be modified and be polished.
Rate adaptation type ldpc decoder provided in an embodiment of the present invention suitable for aerospace communication uses part parallel
Decoding architecture is the universal coding mode of current aerospace communication, is made this using the rule of LDPC coding and decoding as defined in CCSDS standard
Decoder has versatility in satellite communication.According to LDPC code H-matrix feature, 2 check-node functional units and 32 are chosen
A variable node functional unit forms a sub-block, using 100MHz clock, realizes and is no more than the adaptive of 50Mbps data rate
Answer iterative decoding.It should be noted that based on the actual application requirements, can configure appropriate number of check-node when concrete application
Functional unit and variable node functional unit.
Fig. 1 is the structural block diagram of rate adaptation type ldpc decoder of the embodiment of the present invention.Referring to FIG. 1, LDPC is decoded
Device includes: input data processing module, iteration decoding module and output data processing module.Firstly, input data, accompanying clock
Input data processing module is inputted with local clock；Then, input data input and output after iteration decoding module decoding processing
Data processing module；Finally, output data processing module output output data, accompanying clock and data validity marker bit.
With continued reference to FIG. 1, input data processing module includes Frame Synchronization Test unit, FIFO memory and null frame filling
Unit.After data flow inputs input data processing module, firstly, to prevent input data frame construction error from causing decoder subsequent
Processing is chaotic, does Frame Synchronization Test to input data by Frame Synchronization Test unit: if frame synchronization, synchronous data frame being sent
Enter the FIFO memory；Otherwise, the FIFO memory, null frame fills unit, iteration decoding module and output data are resetted
Processing module；Then, null frame fills unit from FIFO memory read data frame and is sent into iteration decoding module, when FIFO is stored
When data read empty in device, null frame fills unit filling null frame continues to be fed into iteration decoding module, to guarantee the iterative decoding mould
The continuity of block input data；Meanwhile FIFO memory send label is read into output data processing module after being delayed.
Fig. 2 is Frame Synchronization Test state flow chart of the embodiment of the present invention, referring to FIG. 2, frame synchronizing process includes 4 shapes
State: search condition (S), trapped state (C1, C2), lock state (L) and review state (F1, F2), wherein
Search condition: Frame Synchronization Test unit real-time monitoring input data content, once the content in discovery register is
Frame head data (is illustrated so that frame head is " 1ACFFC1D ", fault-tolerant 2bits as an example) below, then enters capture shape from search condition
Otherwise state continues to keep search condition, while starting one 13 counters, and counting the period is 8192；
Trapped state: when counter is 8191, Frame Synchronization Test unit checks data, if content is still
" 1ACFFC1D ", then correctly count is incremented for frame head, otherwise retracts search condition；When frame head, which correctly counts, is more than or equal to 3, enter
Lock state；
Lock state: Frame Synchronization Test unit counter it is each 8191 when frame by frame check receive data content, if number
It is still " 1ACFFC1D " according to content, then keeps lock state；
Review state: in lock state, if frame head is not detected, count is incremented for frame head error；If frame head error counts
Frame head is detected when less than 3, then retracts lock state；If frame head error, which counts, is more than or equal to 3, search condition is reentered.
When Frame Synchronization Test unit is in search condition or trapped state, FIFO memory, null frame fills unit, iteration are translated
Code module and output data processing module are in reset state；When Frame Synchronization Test unit is in the lock state or checks state,
FIFO memory, null frame fills unit, iteration decoding module and output data processing module work normally.Frame Synchronization Test unit
By being judged input data format correctness, input data format entanglement can be effectively prevented to the shadow of local program
It rings, after front end input data format is of short duration to malfunction and restore normal, local program can restore normal encoding automatically.Frame synchronization is just
In true data content deposit FIFO memory, by FIFO memory realize data buffer storage and accompanying clock/local clock every
From.
As one embodiment, according to the full status indication and empty status flags of the FIFO memory, null frame filling is single
Member is sent into the iteration decoding module from the FIFO memory read data frame or filling null frame, when data in FIFO memory
When reading empty, null frame is continued to fill up by null frame fills unit to guarantee to input the continuity of the data of iteration decoding module, Jin Erbao
Card iteration decoding module operation is continuous, does not need complicated clock switch logic, simplifies control logic, realizes decoding rate certainly
It adapts to.Meanwhile the reading label of FIFO memory is sent after being delayed to output data processing module.
Specifically, by taking FIFO memory reads clock as 50MHz as an example, null frame fills unit expires according to FIFO memory
Status indication and empty status flags instruction read data frame or filling null frame.Fig. 3 is null frame fills unit of the embodiment of the present invention
State transition diagram.Referring to FIG. 3, null frame fills unit totally 3 states: original state reads data fifo state and filling null frame
State, wherein
Original state: the full status indication for detecting FIFO memory is " 1 ", and empty status flags are " 0 ", is denoted as sta=
10, FIFO, which is in, at this time can be read state, start to read data fifo, and start a 13 bit wide counters；Wherein, sta
First is full status indication, and second is empty status flags；
It reads data fifo state: starting to read FIFO memory data, if detection sta=00 or sta=10, after resuming studies
Take FIFO memory data；If there is illegal state sta=11, original state is jumped to；If detecting sta=01 and counter
Num=8192 then jumps to filling null frame state.
Fill null frame state: data are read empty in FIFO memory, fill whole frame format sky data to guarantee that coding module is defeated
Enter continuous.If detecting sta=01 or sta=00, null frame is continued to fill up；If there is illegal state sta=11, leap to just
Beginning state；If detecting sta=10 and counter num=8192, jumps to and read data fifo state.
After data frame inputs iteration decoding module, decoding process is the message process of continuous iteration, includes following 4
Step:
Step 1: initialization
Maximum number of iterations is set, and assigns the LLR obtained by channel, the interior information as variable point to each variable point
(Intrinsic Value)。
Wherein, PnFor the channel prior information of n-th of variable node.
Step 2: the t times iteration, the transmitting information of variable node to check-node
Step 3, the t times iteration, the information transmitting of check-node to variable node
Iteration several times after, if meeting maximum number of iterations, calculate posterior probability simultaneously adjudicate, otherwise repeatedly step 2 and step
Rapid 3.
Step 4: calculating the posterior probability of variable node and adjudicate output.
The posterior probability of each variable node output are as follows:
Each bit is made decisions according to following rule:
Wherein, maximum a posteriori probability L(post)(un) it is the external information of variable node n and the initial likelihood ratio information of node n
The sum of.
Specifically, with continued reference to FIG. 1, iteration decoding module is modified Min-Sum decoding algorithm to the data frame of input
(Modified Min-sum Algorithm, MMSA) decoding, and the data frame after decoding is sent into output data processing module.
In the present embodiment, iteration decoding module includes initial information storage unit, check-node functional unit (CFU), variable node function
It can unit (VFU), iterative information storage unit and control unit.Wherein, initial information storage unit major function is to cache simultaneously
Initial Channel Assignment information, to δ value in formula (1)Then initialization information is channel input information, initial information storage
Unit is made of two groups of Block RAM ping-pong operations, every group of Block RAM 16 two-port RAMs, each RAM storage depth
It is 511, every frame coding channel likelihood ratio information is divided into 16 sections that length is 511.First group of RAM receives channel initialization data
When, second group of RAM is waited, and after first group of RAM receives complete frame channel initialization data, starting variable node handles mould
Block starts iterative decoding operation, and second group of RAM receives channel initialization data at this time, alternately.It is carried out to certain frame data
When decoded operation, the numerical value in channel initial information storage unit is remained unchanged；RAM group also simultaneously realize across clock frequency every
From the clock of writing of RAM group is 50MHz, and reading clock is 100MHz, and successive iterations work decoding master clock is 100MHz；Variable section
The interative computation unit that point functional unit (VFU), check-node functional unit (CFU), iterative information storage unit form, mainly
Function is the interative computation for carrying out variable node and check-node information update；Control unit mainly completes each unit working condition
Coordinated control carries out forced resetting at every frame data frame head, mistake caused by single-particle inversion is limited in present frame, under
One frame data restore normal after arriving, and error diffusion can be effectively prevented.
Fig. 4 is iteration decoding module work flow diagram of the embodiment of the present invention.Referring to FIG. 4, the work of iteration decoding module
Process is as follows:
A. one group of Block RAM of control unit control initial information storage unit, this group of Block RAM write is enabled to be had
Effect receives the information for carrying out self-channel, after a frame data all store, is switched to another group of Block RAM and stores next frame number
According to, while returning to one signal of control unit；
B. control unit enables variable node functional unit (VFU) after a frame data store, and enabled initialization
Storage unit read functions carry out variable node and update operation, and iterative information storage unit is written in operation result；
C. after the completion of variable node functional unit (VFU) operation, end signal, control unit shielding are sent to control unit
Variable node functional unit (VFU) and initial information storage unit start the operation of check-node functional unit (CFU), verification
Nodal function unit (CFU) reads information from iterative information storage unit, and operation result is written and is read address identical bits
In setting；
D. after check-node functional unit (CFU) operation, check-node functional unit (CFU) is sent to control unit
End signal, control unit shield check-node functional unit (CFU), start variable node functional unit (VFU) and initial letter
Cease storage unit, such variable node functional unit (VFU) and check-node functional unit (CFU) alternately operation.
E. after the interative computation of maximum number of iterations, iterative decoding is completed, and the data after decoding are sent into output
Data processing module.Then, start the iterative decoding of next frame data.
Wherein, variable node renewal process is also known as vertical operation, mainly realizes the content of formula (2).At variable node
The effect of reason module includes two parts: a part is to update variable node message, send to iterative information storage unit and is used for school
It tests node and carries out next iteration；Another part (vout) is to update posterior probability message, which is mainly used for hard decision.
Fig. 5 is variable node functional unit working principle diagram of the embodiment of the present invention.Referring to FIG. 5, variable node function list
The workflow of member are as follows: 1 channel likelihood ratio (LLR) information is read from each channel initial information storage unit；Meanwhile root
4 check-node information are read from 4 iterative information storage units according to address；Variable node functional unit is to by iterative information
The check-node information and LLR information read in storage unit carries out vertical operation, obtains new variable node information；Finally,
New variable node information is write back in each iterative information storage unit by read address, confidence information is completed and updates.It needs
Repeat the vertical calculating process of maximum number of iterations.
Vertical calculating process completes in algorithm variable node to the calculating of check-node using 5 level production line modes, wherein
It is 0.75 by the normaliztion constant factor value in formula (2), multiplying can be reduced to displacement add operation, as long as
Carrying out shifter-adder can be achieved with, and enormously simplify arithmetic logic.
With continued reference to FIG. 5, in0~in3 is four check-nodes being connected in Tanner figure with a variable node
Updated information；Intrinsic Value is the initialization information of variable node；Out0~out3 be four variable nodes into
Information after row update；Vout is the adduction of interior information and 4 input information, is sentenced by checking the highest order of the information
Certainly.
Check-node functional unit mainly realizes formula (3), for completing the update of check-node message, renewal process
Referred to as operation of horizontal, is a part of iterative process, and the operation of progress mainly makes decoder go the i-th row of each row block
Confidence information updates operation.
Fig. 6 is the working principle diagram of check-node functional unit of the embodiment of the present invention.Referring to FIG. 6, each check-node
32 variable node messages are read from 32 iterative information storage units；Due to the read address of 32 iterative information storage units
It is i, therefore this single stepping only needs counter to can be achieved with the reading of information；Then, 32 variable node information are read
After be directly fed to the check node unit carry out information update operation, obtain new check-node information；Finally, by new verification
Nodal information is write back in each iterative information storage unit by read address, completes check-node information update.Complete an iteration
Operation of horizontal, i.e. check-node information update operation, need repeat maximum number of iterations operation of horizontal process.
In amendment Min-Sum decoding algorithm, the work that check-node functional unit needs are completed is: finding out and a school
The minimum value of each variable node data (in addition to itself) absolute value that node is connected is tested, if the value of current point is minimum value,
Then output is the minimum value in other all values, i.e., secondary minimum value.The product for seeking each data symbol value, by gained minimum value and symbol
Number value is merged into new data, i.e.,
Wherein, the product of each symbol can obtain by searching for the mode of table.
With continued reference to FIG. 1, the output data processing module includes hard decision unit, Framing unit and data validity
Marking unit, hard decision unit carry out hard decision to the data after iterative decoding, carry out framing output through Framing unit, simultaneously also
Data validity flag and accompanying clock of the output data validity unit to judgement data markers.By adjoint to output data
Validity marker bit keeps data after decoding continuous under each rate conditions, does not influence data validity.
The embodiment of the present invention realizes the ldpc decoder based on CCSDS standard recommendation, transmits need to meet different rates
It asks, it is right by way of filling null frame and output data with validity marker bit to input data outside basic decoding function
Different rates decoding data self-adaptive processing eliminates clock switching system complicated under different rates；By to input data
Format judgement and reset processing combine, and decoder is made to have self-recovering function after reception wrong data；It is transported by every frame data
Calculating terminates to improve decoder anti-single particle overturning performance to all register reset processing modes.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (5)
1. a kind of rate adaptation type ldpc decoder suitable for aerospace communication characterized by comprising input data processing
Module, iteration decoding module and output data processing module, wherein
The input data processing module includes that Frame Synchronization Test unit, FIFO memory and null frame fills unit, data flow are defeated
Enter the Frame Synchronization Test unit, the Frame Synchronization Test unit does Frame Synchronization Test to data: if frame synchronization, will synchronize
Data frame be sent into the FIFO memory and otherwise reset the FIFO memory, null frame fills unit, iteration decoding module
With output data processing module；According to the full status indication and empty status flags of the FIFO memory, the null frame filling is single
Member is sent into the iteration decoding module from the FIFO memory read data frame or filling null frame；The reading of the FIFO memory
Label is taken to be sent after being delayed to the output data processing module；
The iteration decoding module is iterated decoding to the data frame of input, and will be described in the data frame feeding after iterative decoding
Output data processing module；
The output data processing module does hard decision to the data after iterative decoding and framing exports, while the reading being marked
It is denoted as data validity flag position with output.
2. the rate adaptation type ldpc decoder according to claim 1 suitable for aerospace communication, which is characterized in that institute
Null frame fills unit is stated to include original state, read data fifo state and filling null frame state, wherein
Original state: the full status indication for detecting FIFO memory is " 1 ", and empty status flags are " 0 ", is denoted as sta=10, this
When FIFO be in state can be read, start read data fifo, and start a 13 bit wide counters；Wherein, first of sta
For full status indication, second is empty status flags；
It reads data fifo state: starting to read FIFO memory data, if detection sta=00 or sta=10, continues to read
FIFO memory data；If there is illegal state sta=11, original state is jumped to；If detecting sta=01 and counter
Num=8192 then jumps to filling null frame state；
Fill null frame state: data are read empty in FIFO memory, fill whole frame format sky data to guarantee that coding module input connects
It is continuous.If detecting sta=01 or sta=00, null frame is continued to fill up；If there is illegal state sta=11, initial shape is leapt to
State；If detecting sta=10 and counter num=8192, jumps to and read data fifo state.
3. the rate adaptation type ldpc decoder according to claim 1 suitable for aerospace communication, which is characterized in that institute
Iteration decoding module is stated using amendment Min-Sum decoding algorithm.
4. the rate adaptation type ldpc decoder according to claim 4 suitable for aerospace communication, which is characterized in that
For variable node into the operation of check-node, taking normaliztion constant is 0.75.
5. the rate adaptation type ldpc decoder according to claim 1 suitable for aerospace communication, which is characterized in that institute
Stating iteration decoding module includes control unit, and described control unit carries out forced resetting at every frame data frame head, by single-particle
Mistake caused by overturning is limited in present frame.
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| CN113934133A (en) * | 2021-09-28 | 2022-01-14 | 国网电力科学研究院有限公司 | Control command confirmation method and system suitable for security control system |
| CN113934133B (en) * | 2021-09-28 | 2024-05-31 | 国网电力科学研究院有限公司 | Control command confirmation method and system suitable for security control system |
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