CN109889209B - Rate self-adaptive LDPC decoder suitable for aerospace communication - Google Patents
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Abstract
The invention discloses a rate self-adaptive LDPC decoder suitable for aerospace communication, which comprises: the data stream is input into the frame synchronization detection unit, the frame synchronization detection unit carries out frame synchronization detection on the data, the synchronous data frames are sent into the FIFO memory, and the empty frame filling unit reads the data frames from the FIFO memory or fills the empty frames into the iterative decoding module according to the full state mark and the empty state mark of the FIFO memory; after the iterative decoding module decodes, the output data processing module makes hard decision on the data after iterative decoding and outputs the data in a framing way. According to the invention, the space frame is filled into the input data, so that the decoding operation of self-adaptively processing the data with different rates by a single master clock is realized.
Description
Technical Field
The present application relates to error correction coding in the field of digital communication technologies, and in particular, to a rate adaptive LDPC decoder suitable for aerospace communications.
Background
The digital signal is subject to noise and interference in the transmission process and errors occur, the channel coding technology is widely applied to various communication systems as an effective means for ensuring reliable information transmission, low-density parity check codes (Low-Density Parity Check Code, LDPC) are first proposed by Gallager, mackay et al further research shows that the performance of the LDPC codes can approach Shannon Limit under a belief propagation (Belief Propagation) decoding algorithm, and the LDPC codes have a lower error code platform and are one of space navigation communication error correction codes recommended by CCSDS.
An LDPC code is a linear block code whose check matrix is a very sparse matrix in which the number of non-zero elements is small relative to the row-column length. Such an LDPC code is said to be regular if each row (or column) of the check matrix has the same non-zero element, otherwise it is said to be an irregular LDPC code. The positions of the elements 1 in the check matrix of the irregular LDPC code are basically irregular and circulated, so that the complexity of coding and decoding is high, and the implementation difficulty is high. And the regular LDPC code, especially the quasi-cyclic regular LDPC (QC-LDPC) code can adopt a simple shift register to finish encoding and decoding, so that the hardware complexity is greatly reduced.
The (8160, 7136) LDPC code specified by CCSDS belongs to one of QC-LDPC codes, and the decoder structure of QC-LDPC codes mainly has three kinds:
serial decoding: by reusing 1 CFU and VFU arithmetic units to complete all row (column) operations, the resources are minimal, but many clock cycles are required to complete a complete row (column) update.
Full parallel structure: by configuring one operation unit for each row (column) and enabling all operation units to work in parallel, the operation speed is improved, and 1 iteration operation can be completed only by 2 clock cycles at least, but a lot of hardware resources are consumed, and the chip is difficult to support.
Semi-parallel structure: by utilizing the quasi-cyclic characteristic of the QC-LDPC check matrix, a semi-parallel structure can be used for dividing the check matrix into a plurality of sub-blocks, the node of each sub-block is mapped into a hardware processing unit, the external information of one sub-block check node and variable node is calculated by repeating one sub-block check node and variable node operation unit in each iteration process, and the information updating of all nodes is sequentially completed by the sub-block node processing unit.
In the decoding process of the decoder, since the main clock needs to be processed slightly higher than the input data accompanying clock in multiple iterative operation, if the main clock is obtained by multiplying the frequency of the input data accompanying clock 2, a high-speed clock needs to be provided by a hardware phase-locked loop, and for decoding operation of different input data rates, different hardware phase-locked loops are correspondingly required, so that complex clock switching logic is required to meet the decoding operation requirements of different input data rates.
Therefore, it is desirable to provide a rate adaptive type LDPC decoder, which supports decoding operation of arbitrary rate data through a single master clock on the basis of implementing the LDPC decoding function, does not need clock switching, simplifies control logic of the decoder, and improves reliability of the decoder.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a rate adaptive LDPC decoder suitable for aerospace communications, including: an input data processing module, an iterative decoding module and an output data processing module, wherein,
the input data processing module comprises a frame synchronization detection unit, a FIFO memory and a null frame filling unit, wherein the frame synchronization detection unit is input by a data stream, and the frame synchronization detection unit performs frame synchronization detection on data: if the frames are synchronous, the synchronous data frames are sent to the FIFO memory, otherwise, the FIFO memory, the empty frame filling unit, the iterative decoding module and the output data processing module are reset; the empty frame filling unit reads data frames from the FIFO memory or fills empty frames to be sent to the iterative decoding module according to the full state mark and the empty state mark of the FIFO memory; the reading mark of the FIFO memory is delayed and then sent to the output data processing module;
the iterative decoding module performs iterative decoding on the input data frame and sends the data frame after iterative decoding to the output data processing module;
and the output data processing module makes hard decision on the iteratively decoded data, frames the data and outputs the data, and simultaneously takes the read mark as a data validity mark bit to be output concomitantly.
Preferably, the null frame filling unit includes an initial state, a read FIFO data state, and a fill null frame state, wherein,
initial state: detecting that the full state of the FIFO memory is marked as "1", the empty state is marked as "0", and is marked as sta=10, when the FIFO is in a readable state, starting to read FIFO data, and starting a 13-bit wide counter; wherein the first bit of a sta is a full state flag and the second bit is an empty state flag;
read FIFO data state: starting to read the FIFO memory data, and if sta=00 or sta=10 is detected, continuing to read the FIFO memory data; if illegal state sta=11 appears, jumping to the initial state; if sta=01 is detected and num=8192 is a counter, then jump to the fill empty frame state;
filling in a null frame state: the data in the FIFO memory is read empty, and the empty data in the whole frame format is filled so as to ensure continuous input of the coding module. If sta=01 or sta=00 is detected, continuing to fill the null frame; if illegal state sta=11 appears, directly jumping to the initial state; if sta=10 is detected and the counter num=8192, then the read FIFO data state is skipped.
Preferably, the iterative decoding module adopts a modified minimum sum decoding algorithm.
Preferably, in the operation from the variable node to the check node, the normalization constant is taken to be 0.75.
Preferably, the iterative decoding module comprises a control unit, wherein the control unit performs forced reset at the head of each frame of data frame, and limits errors caused by single event upset to the current frame.
Compared with the prior art, the invention has the following technical effects:
1. according to the invention, by filling the blank frames into the input data and marking the data validity of the output data, the decoding operation of self-adaptively processing the data with different rates by a single master clock is realized, and a complex clock switching system under different rates is omitted;
2. the invention combines the input data format judgment and the reset processing, so that the decoder has the function of self-recovery after receiving error data;
3. according to the invention, the reset processing mode of all registers is finished through each frame of data operation, so that the single event upset resistance of the decoder is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the accompanying drawings:
FIG. 1 is a block diagram of a rate adaptive LDPC decoder according to an embodiment of the present invention adapted for use in aerospace communications;
FIG. 2 is a flow chart of a frame sync detection state according to an embodiment of the present invention;
FIG. 3 is a state transition diagram of a null frame fill element according to an embodiment of the present invention;
FIG. 4 is a flowchart of the iterative decoding module operation of an embodiment of the present invention;
FIG. 5 is a schematic diagram of the functional unit of a variable node according to an embodiment of the present invention;
fig. 6 is a schematic diagram of the operation of the check node function unit according to an embodiment of the present invention.
Detailed Description
The rate adaptive LDPC decoder suitable for aerospace communication provided by the invention will be described in detail below with reference to the accompanying drawings, the embodiment is implemented on the premise of the technical scheme of the invention, and a detailed implementation mode and a specific operation process are provided, but the protection scope of the invention is not limited to the embodiment described below, and the modification and color rendering can be performed by those skilled in the art without changing the spirit and content of the invention.
The rate self-adaptive LDPC decoder suitable for space navigation communication provided by the embodiment of the invention adopts a partial parallel decoding structure, adopts the LDPC coding rule specified by the CCSDS standard, is a general coding mode of the current space navigation communication, and has universality in satellite communication. According to the characteristic of the LDPC code H matrix, 2 check node functional units and 32 variable node functional units are selected to form a sub-block, and a 100MHz clock is adopted to realize self-adaptive iterative decoding with the data rate not exceeding 50 Mbps. It should be noted that, during specific application, according to practical application requirement, a proper number of check node functional units and variable node functional units can be configured.
Fig. 1 is a block diagram of a rate adaptive LDPC decoder according to an embodiment of the present invention. Referring to fig. 1, the ldpc decoder includes: the device comprises an input data processing module, an iterative decoding module and an output data processing module. Firstly, inputting data, an accompanying clock and a local clock into an input data processing module; then, the input data is decoded by the iterative decoding module and then is input into the output data processing module; finally, the output data processing module outputs output data, an accompanying clock and a data validity flag bit.
With continued reference to fig. 1, the input data processing module includes a frame synchronization detecting unit, a FIFO memory, and a null frame filling unit. After the data stream is input into the input data processing module, firstly, in order to prevent the subsequent processing confusion of the decoder caused by the frame structure error of the input data, the frame synchronization detection unit performs frame synchronization detection on the input data: if the frames are synchronous, sending the synchronous data frames into the FIFO memory; otherwise, resetting the FIFO memory, the empty frame filling unit, the iterative decoding module and the output data processing module; then, the empty frame filling unit reads the data frame from the FIFO memory and sends the data frame into the iterative decoding module, and when the data in the FIFO memory is read empty, the empty frame filling unit fills the empty frame and continues to send the empty frame into the iterative decoding module so as to ensure the continuity of the data input by the iterative decoding module; meanwhile, the FIFO memory delays the reading mark and sends the delayed reading mark to the output data processing module.
Fig. 2 is a flow chart of a frame synchronization detection state according to an embodiment of the present invention, please refer to fig. 2, wherein the frame synchronization process includes 4 states: a search state (S), a capture state (C1, C2), a lock state (L) and a review state (F1, F2), wherein,
search state: the frame synchronization detection unit monitors the content of input data in real time, and once the content in the register is found to be frame header data (hereinafter, the description is given by taking the frame header as 1ACFFC1D and fault tolerance 2bits as examples), the frame synchronization detection unit enters a capturing state from a searching state, otherwise, the searching state is kept continuously, and a 13-bit counter is started at the same time, wherein the counting period is 8192;
capturing state: when the counter is 8191, the frame synchronization detecting unit checks the data, if the content is still 1ACFFC1D, the frame header is correctly counted and added with 1, otherwise, the searching state is returned; when the correct count of the frame header is more than or equal to 3, entering a locking state;
locking state: the frame synchronization detecting unit checks the received data content frame by frame at each 8191 of the counters, and maintains a lock state if the data content is still "1ACFFC 1D";
rechecking state: in the locked state, if no frame header is detected, the frame header error count is incremented by 1; if the frame header error count is less than 3, the frame header is detected, and the locking state is returned; if the error count of the frame header is more than or equal to 3, the searching state is re-entered.
When the frame synchronization detection unit is in a searching state or a capturing state, the FIFO memory, the empty frame filling unit, the iterative decoding module and the output data processing module are in a reset state; when the frame synchronization detection unit is in a locking state or a rechecking state, the FIFO memory, the empty frame filling unit, the iterative decoding module and the output data processing module work normally. The frame synchronization detection unit can effectively prevent the influence of the input data format disorder on the local program by judging the correctness of the input data format, and the local program can automatically restore normal coding after the short-term error and the normal restoration of the input data format at the front end. The data content with correct frame synchronization is stored in the FIFO memory, and the data buffering and the accompanying clock/local clock isolation are realized through the FIFO memory.
As an embodiment, according to the full state flag and the empty state flag of the FIFO memory, the empty frame filling unit reads the data frame from the FIFO memory or fills the empty frame and sends it into the iterative decoding module, and when the data in the FIFO memory is empty, the empty frame filling unit continues to fill the empty frame to ensure the continuity of the data input into the iterative decoding module, thereby ensuring the continuity of the operation of the iterative decoding module, simplifying the control logic and realizing the self-adaption of the decoding rate without complex clock switching logic. Meanwhile, the reading mark of the FIFO memory is delayed and then sent to the output data processing module.
Specifically, taking the FIFO memory read clock as an example of 50MHz, the empty frame filling unit indicates to read a data frame or fill an empty frame according to the full state flag and the empty state flag of the FIFO memory. Fig. 3 is a state transition diagram of a null frame filling unit according to an embodiment of the present invention. Referring to fig. 3, the empty frame filling unit has 3 states: an initial state, a read FIFO data state, and a fill empty frame state, wherein,
initial state: detecting that the full state of the FIFO memory is marked as "1", the empty state is marked as "0", and is marked as sta=10, when the FIFO is in a readable state, starting to read FIFO data, and starting a 13-bit wide counter; wherein the first bit of a sta is a full state flag and the second bit is an empty state flag;
read FIFO data state: starting to read the FIFO memory data, and if sta=00 or sta=10 is detected, continuing to read the FIFO memory data; if illegal state sta=11 appears, jumping to the initial state; if sta=01 is detected and the counter num=8192, the transition to the fill empty frame state is made.
Filling in a null frame state: the data in the FIFO memory is read empty, and the empty data in the whole frame format is filled so as to ensure continuous input of the coding module. If sta=01 or sta=00 is detected, continuing to fill the null frame; if illegal state sta=11 appears, directly jumping to the initial state; if sta=10 is detected and the counter num=8192, then the read FIFO data state is skipped.
After the data frame is input into the iterative decoding module, the decoding process is a message transmission process of continuous iteration, and the method comprises the following 4 steps:
step 1: initialization of
The maximum number of iterations is set, and LLRs obtained from the channel are assigned to each variable point as the intra information (intra Value) of the variable point.
Wherein P is n Channel a priori information for the nth variable node.
Step 2: the t time iteration, the variable node transmits information to the check node
Step 3, the t-th iteration, the information transfer from the check node to the variable node
After iterating for several times, if the maximum iteration times are met, calculating the posterior probability and judging, otherwise, repeating the step 2 and the step 3.
Step 4: and calculating the posterior probability of the variable node and judging and outputting.
The posterior probability output by each variable node is:
each bit is decided according to the following rule:
wherein the maximum posterior probability L (post) (u n ) Is the sum of the external information of the variable node n and the initial likelihood ratio information of the node n.
Specifically, please continue to refer to fig. 1, the iterative decoding module performs Modified Min-sum algorism (MMSA) decoding on the input data frame, and sends the decoded data frame to the output data processing module. In this embodiment, the iterative decoding module includes an initial information storage unit, a check node function unit (CFU), a variable node function unit (VFU), an iterative information storage unit, and a control unit. Wherein the primary function of the initial information storage unit is to buffer and initialize channel information, and to take delta value in formula (1)
The initialization information is channel input information,the initial information storage unit is operated by two groups of Block RAMs in ping-pong mode, each group of Block RAMs is composed of 16 dual-port RAMs, each RAM has a storage depth of 511, and each frame of decoding channel likelihood ratio information is divided into 16 sections with a length of 511. When the first group of RAMs receives channel initialization data, the second group of RAMs waits, and after the first group of RAMs receives complete one frame of channel initialization data, the variable node processing module is started to start iterative decoding operation, and at the moment, the second group of RAMs receives the channel initialization data and performs the iterative decoding operation alternately. When decoding operation is carried out on certain frame data, the numerical value in the channel initial information storage unit is kept unchanged; the RAM group also realizes cross-clock frequency isolation at the same time, the write clock of the RAM group is 50MHz, the read clock is 100MHz, and the subsequent iteration decoding work master clock is 100MHz; the variable node functional unit (VFU), the check node functional unit (CFU) and the iteration information storage unit are used for performing iteration operation of updating the variable node and check node information; the control unit mainly completes coordination control of the working states of the units, performs forced reset at the frame head of each frame of data, limits errors caused by single event upset to the current frame, and can effectively prevent error diffusion by recovering the next frame of data after arriving.
Fig. 4 is a flowchart illustrating the operation of the iterative decoding module according to an embodiment of the present invention. Referring to fig. 4, the workflow of the iterative decoding module is as follows:
a. the control unit controls a group of Block RAMs of the initial information storage unit, the group of Block RAMs are enabled to be effective in writing, information from a channel is received, after one frame of data is stored completely, the control unit is switched to the other group of Block RAMs to store the next frame of data, and meanwhile, a signal is returned to the control unit;
b. after the end of the storage of the frame data, the control unit enables a variable node function unit (VFU), enables the reading function of the initialization storage unit, performs variable node updating operation, and writes the operation result into the iteration information storage unit;
c. after the variable node functional unit (VFU) operation is finished, an end signal is sent to the control unit, the control unit shields the variable node functional unit (VFU) and the initial information storage unit, the operation of the check node functional unit (CFU) is started, the check node functional unit (CFU) reads information from the iteration information storage unit, and the operation result is written into the same position as the read address;
d. after the operation of the check node functional unit (CFU) is finished, the check node functional unit (CFU) sends an end signal to the control unit, the control unit shields the check node functional unit (CFU), and the variable node functional unit (VFU) and the initial information storage unit are started, so that the variable node functional unit (VFU) and the check node functional unit (CFU) alternately operate.
e. After the iterative operation of the maximum iterative times, the iterative decoding is completed, and the decoded data is sent to an output data processing module. Then, iterative decoding of the next frame data starts.
The variable node update process is also called vertical operation, and mainly realizes the content of the formula (2). The function of the variable node processing module comprises two parts: part of the information is updated variable node information, and the updated variable node information is sent to an iteration information storage unit for carrying out the next iteration on the check node; the other part (vout) is an update posterior probability message, which is mainly used for hard decisions.
Fig. 5 is a schematic diagram of the operation of the variable node functional unit according to an embodiment of the present invention. Referring to fig. 5, the workflow of the variable node functional unit is: reading out 1 channel likelihood ratio (LLR) information from each channel initial information storage unit; meanwhile, reading 4 pieces of check node information from 4 iterative information storage units according to the address; the variable node functional unit performs vertical operation on the check node information and the LLR information read out from the iteration information storage unit to obtain new variable node information; and finally, writing the new variable node information back to each iteration information storage unit according to the read address to finish the updating of the confidence information. The vertical operation process of the maximum number of iterations needs to be repeated.
The vertical operation process adopts a 5-stage pipeline mode to finish the calculation from a variable node to a check node in the algorithm, wherein the normalized constant factor in the formula (2) is valued to be 0.75, the multiplication operation can be simplified to be a shift addition operation, and the calculation logic is greatly simplified as long as the shift addition operation is carried out.
With continued reference to fig. 5, in0 to in3 are updated information of four check nodes connected to one variable node in the Tanner graph; the Intrinsic Value is the initialization information of the variable node; out0 to out3 are information after the four variable nodes are updated; vout is the sum of the inner information and the 4 input information, and is decided by examining the most significant bits of this information.
The check node functional unit mainly realizes a formula (3) for completing the update of the check node message, wherein the update process is called horizontal operation, is part of an iterative process, and mainly makes the decoder perform row confidence information update operation on the ith row of each row block.
Fig. 6 is a schematic diagram of the operation of the check node function unit according to an embodiment of the present invention. Referring to fig. 6, each check node reads out 32 variable node messages from 32 iteration information storage units; because the read addresses of the 32 iteration information storage units are i, the information can be read only by a counter in the one-step operation; then, the 32 variable node information is directly sent to the check node unit for information updating operation after being read out, so as to obtain new check node information; and finally, writing the new check node information back to each iteration information storage unit according to the read address to finish the update of the check node information. And (3) finishing the horizontal operation of one iteration, namely updating the check node information, and repeating the horizontal operation process of the maximum iteration times.
In the correction minimum sum decoding algorithm, the work to be done by the check node functional unit is: the minimum value of the absolute value of each variable node data (except itself) connected with one check node is obtained, and if the value of the current point is the minimum value, the minimum value among all other values, namely the next minimum value, is output. Multiplying the sign values of each data, combining the minimum value with the sign value to form new data, i.e
Wherein the product of each symbol can be obtained by means of a look-up table.
With continued reference to fig. 1, the output data processing module includes a hard decision unit, a framing unit, and a data validity marking unit, where the hard decision unit makes a hard decision on the iteratively decoded data, and the framing unit outputs the data, and also outputs a data validity marking and an accompanying clock of the data validity marking unit for determining the data marking. The output data is accompanied with validity marking bits, so that decoded data is continuous under various speed conditions, and the data validity is not influenced.
The embodiment of the invention realizes the LDPC decoder recommended based on the CCSDS standard, and in order to meet the transmission requirements of different rates, in addition to the basic decoding function, the method fills the space frame and the output data with the validity marking bit to the input data, so as to adaptively process the decoded data of different rates, thereby omitting a complex clock switching system under different rates; the decoder has a self-recovery function after receiving error data by combining input data format judgment and reset processing; and the reset processing mode of all registers is finished through the data operation of each frame, so that the single event upset resistance of the decoder is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A rate adaptive LDPC decoder adapted for use in aerospace communications, comprising: an input data processing module, an iterative decoding module and an output data processing module, wherein,
the input data processing module comprises a frame synchronization detection unit, a FIFO memory and a null frame filling unit, wherein the frame synchronization detection unit is input by a data stream, and the frame synchronization detection unit performs frame synchronization detection on data: if the frames are synchronous, the synchronous data frames are sent to the FIFO memory, otherwise, the FIFO memory, the empty frame filling unit, the iterative decoding module and the output data processing module are reset; the empty frame filling unit reads data frames from the FIFO memory or fills empty frames to be sent to the iterative decoding module according to the full state mark and the empty state mark of the FIFO memory; the reading mark of the FIFO memory is delayed and then sent to the output data processing module;
the iterative decoding module performs iterative decoding on the input data frame and sends the data frame after iterative decoding to the output data processing module; the iterative decoding module comprises an initial information storage unit, a variable node functional unit, a check node functional unit, an iterative information storage unit and a control unit, wherein the initial information storage unit consists of two groups of Block RAMs, and the iterative decoding comprises the following specific steps:
s1: the control unit controls one group of the Block RAMs of the initial information storage unit, the write enable of the Block RAMs is effective, information from a channel is received, when one group of frame data is stored completely, the control unit switches to the other group of the Block RAMs to store the next frame data, and meanwhile, a signal is returned to the control unit;
s2: after the end of the storage of the frame data, the control unit enables the variable node functional unit and enables the initial information storage unit to read the function, performs variable node updating operation, and writes the operation result into the iteration information storage unit;
s3: after the variable node functional unit is operated, an end signal is sent to the control unit, the control unit shields the variable node functional unit and the initial information storage unit, operation of the check node functional unit is started, the check node functional unit reads information from the iteration information storage unit, and an operation result is written into the same position as a read address;
s4: after the operation of the check node functional unit is finished, the check node functional unit sends an end signal to the control unit, the control unit shields the check node functional unit and starts the variable node functional unit and the initial information storage unit, so that the variable node functional unit and the check node functional unit alternately operate;
s5: after the iterative operation of the maximum iterative times, finishing iterative decoding, and sending the decoded data to the output data processing module;
the output data processing module makes hard decision on the iteratively decoded data and outputs the data in a framing mode, and meanwhile takes the reading mark as a data validity mark bit to be output concomitantly; the output data processing module comprises a hard decision unit, a framing unit and a data validity marking unit, wherein the hard decision unit makes hard decision on the iteratively decoded data, the framing unit performs framing output, and meanwhile, the data validity marking unit also outputs the data validity marking of the decision data marking and an accompanying clock.
2. The rate adaptive LDPC decoder according to claim 1 wherein the null frame padding element comprises an initial state, a read FIFO data state and a padded null frame state, wherein,
initial state: detecting that the full state of the FIFO memory is marked as "1", the empty state is marked as "0", and is marked as sta=10, when the FIFO is in a readable state, starting to read FIFO data, and starting a 13-bit wide counter; wherein the first bit of a sta is a full state flag and the second bit is an empty state flag;
read FIFO data state: starting to read the FIFO memory data, and if sta=00 or sta=10 is detected, continuing to read the FIFO memory data; if illegal state sta=11 appears, jumping to the initial state; if sta=01 is detected and num=8192 is a counter, then jump to the fill empty frame state;
filling in a null frame state: the data in the FIFO memory is read empty, the empty data in the whole frame format is filled to ensure continuous input of the coding module, and if sta=01 or sta=00 is detected, the empty frame is continuously filled; if illegal state sta=11 appears, directly jumping to the initial state; if sta=10 is detected and the counter num=8192, then the read FIFO data state is skipped.
3. The rate adaptive LDPC decoder for aerospace communications according to claim 1, wherein the iterative decoding module employs a modified minimum sum decoding algorithm.
4. The rate adaptive LDPC decoder for aerospace communications according to claim 1, wherein the normalization constant is taken to be 0.75 in the variable node to check node operation.
5. The rate adaptive LDPC decoder for aerospace communications according to claim 1, wherein the iterative decoding module comprises a control unit that performs a forced reset at a header of each frame of data, limiting errors caused by single event upset to be within a current frame.
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