CN109861685A - A kind of full subtracter realized using three-phase double track preliminary filling logic - Google Patents

Abstract

The invention discloses a kind of full subtracters realized using three-phase double track preliminary filling logic, including two XOR gates, three NAND gates, two preset number/reset circuits and nine buffers, the work-based logic of each XOR gate and each NAND gate is respectively three-phase double track preliminary filling logic；Advantage is that an evaluation operation is realized in full subtracter a cycle, it is divided into three phases in a cycle, when discharge control signal and preliminary filling control signal enter low level, full subtracter enters charging stage, when evaluation signal becomes high level from low level, full subtracter realizes evaluation operation, when discharge control signal becomes high level from low level, full subtracter enters discharge condition, it is ready for evaluation operation next time, it is exported within each duty cycle and is discharged to low level since being pre-charged high level, consume energy constant, with energy consumption and the mutually independent feature of handled data, defend the characteristic attacked while reverse-engineering attack with anti-DPA, power consumption is lower.

Description

A kind of full subtracter realized using three-phase double track preliminary filling logic

Technical field

The present invention relates to a kind of full subtracters, more particularly, to a kind of full subtracter realized using three-phase double track preliminary filling logic.

Background technique

With the fast development of IC (Integratedcircuit) chip industry and integrated circuit, intellectual property The safety of (Intellectual Property, IP) is to be improved, and more perfect method is needed to protect.Nowadays, there are many The mode of kind attack IP kernel, the core technology of designer can be quickly grasped using reverse-engineering.Attacker utilizes Gradation processing Technology extracts each layer of chip interior of circuit structure, extracts circuit meshwork list, extracts source code by software, damage is set The legitimate interests of meter person, the behaviors such as imitated chip are even more the intellectual property of designer of having constituted a serious infringement.In face of encrypting or complicating IP kernel afterwards, attacker bypass password program, by physical messages such as the electric current, the voltages that are leaked on acquisition system pin, To extrapolate the cipher mode of IP kernel, this attack is referred to as bypass attack SCA (Side Channel Attacks), In, differential power consumption analysis (Differential Power Analysis, DPA) is exactly a kind of strong operability in bypass attack Attack pattern, defence DPA attack technology attracted wide attention as a hot research direction.Therefore, while tool is realized There are anti-reverse-engineering and the basic circuit structure of DPA attack characteristic to have broad application prospects.

Subtraction is that a kind of common arithmetic operation, theoretically subtraction and add operation are of equal value, and can be with Multiplying can mutually convert with division operation.Subtracter is one of the most basic component for forming arithmetic unit, is widely used in various The data of different word lengths are handled in digital enciphering system.It is real based on insulation dynamic difference logic in terms of full subtracter circuit realization There are certain shortcomings in terms of safety for existing full subtracter, and vulnerable to the attack of DPA, and timing control is complicated, and with Complicated interface circuit need to be designed when cmos circuit interaction；Although the full subtracter that differential logic based on look-up table is realized has good Good anti-DPA attack performance, but reverse-engineering can not defend, and required transistor is more, and area, power dissipation overhead are larger；Base It is not quite identical in the full subtracter output load capacitance that sensitive scale-up version logic is realized, it is possible to the breakthrough as DPA attack Point.

Summary of the invention

Technical problem to be solved by the invention is to provide the connection that one kind can defend reverse-engineering and differential power consumption analysis Close attack, and area and the lesser full subtracter realized using three-phase double track preliminary filling logic of power dissipation overhead.

The technical scheme of the invention to solve the technical problem is: a kind of realized using three-phase double track preliminary filling logic Full subtracter, including two XOR gates, three NAND gates, two preset number/reset circuits and nine buffers are each described XOR gate and the work-based logic of the NAND gate are respectively three-phase double track preliminary filling logic, each XOR gate and every A NAND gate is respectively provided with first input end, the first inverting input terminal, the second input terminal, the second inverting input terminal, pre- Control terminal, discharge control terminal, evaluation control terminal, output end and reversed-phase output are filled, each preset number/reset circuit point It Ju You not first input end, the second input terminal, third input terminal, the 4th input terminal and output end；By XOR gate described in two Be referred to as the first XOR gate and the second XOR gate, by NAND gate described in three be referred to as the first NAND gate, second with it is non- Preset number/reset circuit described in two is referred to as the first preset number/reset circuit and second in advance by door and third NAND gate Number/reset circuit is set, buffer described in nine is referred to as the first buffer, the second buffer, third buffer, the 4th Buffer, the 5th buffer, hex buffer, the 7th buffer, the 8th buffer and the 9th buffer；First exclusive or The first input end of door is connected with the first inverting input terminal of second NAND gate and its connecting pin is the full subtracter First input end, for accessing minuend, the first inverting input terminal of first XOR gate and described second with it is non- The first input end of door connects and its connecting pin is the first inverting input terminal of the full subtracter, for accessing the anti-of minuend Phase signals, the second input terminal of first XOR gate is connected with the second input terminal of second NAND gate and it is connected End is the second input terminal of the full subtracter, for accessing subtrahend, the second inverting input terminal of first XOR gate and Second inverting input terminal of second NAND gate connects and its connecting pin is the second inverting input terminal of the full subtracter, For accessing the inversion signal of subtrahend, the preliminary filling control of the preliminary filling control terminal of first XOR gate, second NAND gate End processed, first buffer input terminal connected with the input terminal of the 4th buffer and its connecting pin is described The preliminary filling control terminal of full subtracter, for accessing preliminary filling control signal, the discharge control terminal of first XOR gate, described the The discharge control terminal of two NAND gates, second buffer input terminal connected with the input terminal of the 5th buffer and Its connecting pin is the discharge control terminal of the full subtracter, and for accessing discharge control signal, first XOR gate is asked It is slow to be worth control terminal, the evaluation control terminal of second NAND gate, the input terminal of the third buffer and the described the 6th It rushes the input terminal connection of device and its connecting pin is the evaluation control terminal of the full subtracter, for accessing evaluation control signal, institute The output end for the first XOR gate stated, the first input end of second XOR gate and first NAND gate it is first anti- Phase input terminal connection, the reversed-phase output of first XOR gate, second XOR gate the first inverting input terminal and The first input end of first NAND gate connects, the second input terminal of second XOR gate and described first with it is non- Door the second input terminal connection and its connecting pin be the full subtracter low level borrow signal input part, for access low level to One's own department or unit borrows signal, the second anti-phase input of the second inverting input terminal of second XOR gate and first NAND gate End connection and its connecting pin are that the reverse phase low level of the full subtracter borrows signal input part, are borrowed for accessing low level to one's own department or unit The inversion signal of signal, the output end of first buffer, the preliminary filling control terminal of second XOR gate and described The preliminary filling control terminal of first NAND gate connects, the electric discharge control of the output end of second buffer, second XOR gate End processed is connected with the discharge control terminal of first NAND gate, the output end of the third buffer, described second different Or the evaluation control terminal of door is connected with the evaluation control terminal of first NAND gate, the output end of the 4th buffer and The input terminal of 7th buffer connects, the output end of the 7th buffer and the preliminary filling of the third NAND gate Control terminal connection, the output end of the 5th buffer are connected with the input terminal of the 8th buffer, and the described the 8th The output end of buffer is connected with the discharge control terminal of the third NAND gate, the output end of the hex buffer and institute The input terminal for the 9th buffer stated connects, the output end of the 9th buffer and the evaluation control of the third NAND gate End processed connection, the output end of first NAND gate are connected with the first input end of the third NAND gate, and described the The reversed-phase output of one NAND gate is connected with the first inverting input terminal of the third NAND gate, second NAND gate Output end is connected with the second input terminal of the third NAND gate, the reversed-phase output of second NAND gate and described The second inverting input terminal connection of third NAND gate, the output end of second XOR gate and first preset number/multiple The second input terminal connection of position circuit, the reversed-phase output of second XOR gate and first preset number/reset electricity The third input terminal on road connects, the output end and second preset number/reset circuit second of the third NAND gate Input terminal connection, reversed-phase output and second preset number/reset circuit third input of the third NAND gate End connection, first preset number/reset circuit first input end and second preset number/reset circuit first Input terminal connection and its connecting pin are first preset/reset terminal of the full subtracter, for accessing first preset/reset letter Number, the 4th input terminal of the first preset number/reset circuit and second preset number/reset circuit the 4th input End connection and its connecting pin are second preset/reset terminal of the full subtracter, for accessing second preset/reset signal, institute The first preset number stated/reset circuit output end is the poor output end of the full subtracter, described for exporting this potential difference Second preset number/reset circuit output end borrows signal output end for the full subtracter, for exporting one's own department or unit to a high position Borrow signal.

Each preset number/reset circuit respectively includes the one or two input and door, the two or two input are defeated with door and two Enter or door, the one or two input and door, the two or two input and door and two inputs or door are respectively provided with the The first input end of one input terminal, the second input terminal and output end, described one or two input and door is the preset number/multiple Second input terminal of the first input end of position circuit, the one or two input and door is the preset number/reset circuit The first input end of second input terminal, the two or two input and door is that preset number/reset circuit third inputs Second input terminal of end, the two or two input and door is the 4th input terminal of preset number/reset circuit, described One or two input is connect with the first input end of the output end of door and two inputs or door, the two or two input and door Output end connect with the second input terminal of described two input or door, the output end of two inputs or door is described pre- Set the output end of number/reset circuit.

Each buffer respectively includes the first phase inverter and the second phase inverter, the input of first phase inverter End is the input terminal of the buffer, the input terminal company of the output end of first phase inverter and second phase inverter It connects, the output end of second phase inverter is the output end of the buffer.

The XOR gate respectively include the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, 5th PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the tenth Nine NMOS tubes, the 20th NMOS tube and the 21st NMOS tube；The source electrode of first PMOS tube accesses power supply, and described the The grid of one PMOS tube, first NMOS tube grid connected with the grid of the 4th NMOS tube and its connecting pin is The discharge control terminal of the XOR gate, the drain electrode of first PMOS tube, second PMOS tube source electrode, described The source electrode of third PMOS tube, the 4th PMOS tube source electrode connected with the source electrode of the 5th PMOS tube, described The grid of two PMOS tube is connected with the grid of the 5th PMOS tube and its connecting pin is the preliminary filling control of the XOR gate End, it is the drain electrode of second PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of first NMOS tube, described The drain electrode of the second NMOS tube, the grid of the 4th PMOS tube connected with the grid of the third NMOS tube and its connect End is the output end of the XOR gate, the grid, described of the grid of the third PMOS tube, second NMOS tube The drain electrode of 4th PMOS tube, the drain electrode of the third NMOS tube, the drain electrode and the described the 4th of the 5th PMOS tube The drain electrode of NMOS tube connects and its connecting pin is the reversed-phase output of the XOR gate；The source electrode of first NMOS tube connects Ground, it is the source electrode of second NMOS tube, the drain electrode of the 5th NMOS tube, the drain electrode of the 6th NMOS tube, described The drain electrode of the 7th NMOS tube connected with the drain electrode of the 8th NMOS tube, it is the source electrode of the third NMOS tube, described The drain electrode of 9th NMOS tube, the drain electrode of the tenth NMOS tube, the drain electrode and the described the tenth of the 11st NMOS tube The drain electrodes of two NMOS tubes connects, the source electrode ground connection of the 4th NMOS tube, the grid of the 5th NMOS tube, described the The grid of seven NMOS tubes, the tenth NMOS tube grid connected with the grid of the 12nd NMOS tube and its connecting pin For the first input end of the XOR gate, the source electrode of the 5th NMOS tube and the drain electrode of the 13rd NMOS tube connect It connects, the grid of the 6th NMOS tube, the grid of the 8th NMOS tube, the grid of the 9th NMOS tube and described The 11st NMOS tube grid connection and its connecting pin be the XOR gate the first inverting input terminal, the described the 6th The source electrode of NMOS tube is connected with the drain electrode of the 14th NMOS tube, the source electrode and the described the tenth of the 7th NMOS tube The drain electrode of five NMOS tubes connects, and the source electrode of the 8th NMOS tube is connected with the drain electrode of the 16th NMOS tube, described The source electrode of the 9th NMOS tube connected with the drain electrode of the 17th NMOS tube, the source electrode of the tenth NMOS tube and described The 18th NMOS tube drain electrode connection, the drain electrode of the source electrode of the 11st NMOS tube and the 19th NMOS tube connects It connects, the source electrode of the 12nd NMOS tube is connected with the drain electrode of the 20th NMOS tube, the 13rd NMOS tube Grid, the grid of the 14th NMOS tube, the grid of the 19th NMOS tube and the 20th NMOS tube Grid connection and its connecting pin be the XOR gate the second input terminal, it is the source electrode of the 13rd NMOS tube, described The source electrode of the 14th NMOS tube, the source electrode of the 15th NMOS tube, the 16th NMOS tube source electrode, described The source electrode of 17th NMOS tube, the source electrode of the 18th NMOS tube, the source electrode of the 19th NMOS tube, described The source electrode of 20 NMOS tubes is connected with the drain electrode of the 21st NMOS tube, the grid of the 15th NMOS tube, institute The grid for the 16th NMOS tube stated, the 17th NMOS tube grid connected with the grid of the 18th NMOS tube And its connecting pin is the second inverting input terminal of the XOR gate, the grid of the 21st NMOS tube is described different Or the evaluation control terminal of door, the source electrode ground connection of the 21st NMOS tube, first PMOS tube, described second PMOS tube, the third PMOS tube, the 4th PMOS tube and the 5th PMOS tube are common threshold voltage PMOS tube, first NMOS tube, second NMOS tube, the third NMOS tube, the 4th NMOS tube and 21st NMOS tube is common threshold voltage NMOS tube, the 5th NMOS tube, the 8th NMOS tube, Tenth NMOS tube, the 11st NMOS tube, the 13rd NMOS tube, the 16th NMOS tube, institute The 18th NMOS tube and the 19th NMOS tube stated are low threshold voltage NMOS tube, the 6th NMOS tube, institute It is the 7th NMOS tube stated, the 9th NMOS tube, the 12nd NMOS tube, the 14th NMOS tube, described 15th NMOS tube, the 17th NMOS tube, the 20th NMOS tube are high threshold voltage NMOS tube.The exclusive or Door is realized based on three-phase double track preliminary filling logic, introduces additional charging stage and discharge regime, within each duty cycle, base It is all discharged to low level VSS since supply voltage VDD in the output terminal potential of the XOR gate of three-phase double track preliminary filling logic, consumes Energy constant has energy consumption and the mutually independent feature of handled data, therefore the energy with good anti-power consumption attack Power, and in XOR gate, in the pulldown network that the 5th NMOS tube is constituted to the 20th NMOS tube, the right and left NMOS tube quantity is consistent And connection type is the same, has only both been able to achieve XOR logic function by configuring the threshold voltage of NMOS tube, when reverse by carrying out When engineering attack, correct logic function, therefore the ability with good anti-reverse-engineering can not be obtained from domain.

The NAND gate respectively include the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, Tenth PMOS tube, the 22nd NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube, the 20th Six NMOS tubes, the 27th NMOS tube, the 28th NMOS tube, the 29th NMOS tube, the 30th NMOS tube, the 31st NMOS tube, the 32nd NMOS tube, the 33rd NMOS tube, the 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, the 38th NMOS tube, the 39th NMOS tube, the 40th NMOS tube, the 41st NMOS Pipe and the 42nd NMOS tube；The source electrode of 6th PMOS tube accesses power supply, the grid of the 6th PMOS tube, described The 22nd NMOS tube grid and the 25th NMOS tube grid connection and its connecting pin be it is described with it is non- The discharge control terminal of door, the drain electrode of the 6th PMOS tube, the source electrode of the 7th PMOS tube, the 8th PMOS tube Source electrode, the 9th PMOS tube source electrode connected with the source electrode of the tenth PMOS tube, the 7th PMOS tube Grid is connected with the grid of the tenth PMOS tube and its connecting pin is the preliminary filling control terminal of the NAND gate, and described the The drain electrode of seven PMOS tube, the drain electrode of the 8th PMOS tube, the drain electrode of the 22nd NMOS tube, the described the 20th The drain electrode of three NMOS tubes, the 9th PMOS tube grid connected with the grid of the 24th NMOS tube and its connect End is the output end of the NAND gate, the grid of the 8th PMOS tube, the grid of the 23rd NMOS tube, institute The drain electrode for the 9th PMOS tube stated, the drain electrode of the 24th NMOS tube, the drain electrode of the tenth PMOS tube and described The 25th NMOS tube drain electrode connection and its connecting pin be the NAND gate reversed-phase output；Described the 22nd The source electrode of NMOS tube is grounded, the drain electrode, described of the source electrode of the 23rd NMOS tube, the 26th NMOS tube The drain electrode of 27th NMOS tube, the drain electrode of the 28th NMOS tube and the drain electrode of the 29th NMOS tube connect It connects, the source electrode of the 24th NMOS tube, the drain electrode of the 30th NMOS tube, the 31st NMOS tube Drain electrode, the drain electrode of the 32nd NMOS tube are connected with the drain electrode of the 33rd NMOS tube, and the described the 20th The source electrodes of five NMOS tubes is grounded, the grid, described of the grid of the 26th NMOS tube, the 28th NMOS tube The 31st NMOS tube grid and the 33rd NMOS tube grid connection and its connecting pin be it is described with it is non- The first input end of door, the source electrode of the 26th NMOS tube are connected with the drain electrode of the 34th NMOS tube, institute The grid for the 27th NMOS tube stated, the grid of the 29th NMOS tube, the 30th NMOS tube grid It is connected with the grid of the 32nd NMOS tube and its connecting pin is the first inverting input terminal of the NAND gate, it is described The source electrode of the 27th NMOS tube connected with the drain electrode of the 35th NMOS tube, the 28th NMOS tube Source electrode is connected with the drain electrode of the 36th NMOS tube, the source electrode and the described the 30th of the 29th NMOS tube The drain electrode of seven NMOS tubes connects, and the source electrode of the 30th NMOS tube is connected with the drain electrode of the 38th NMOS tube, The source electrode of 31st NMOS tube is connected with the drain electrode of the 39th NMOS tube, the 32nd NMOS The source electrode of pipe is connected with the drain electrode of the 40th NMOS tube, the source electrode and the described the 4th of the 33rd NMOS tube The drain electrode of 11 NMOS tubes connects, the grid of the 34th NMOS tube, the grid of the 35th NMOS tube, institute The grid of the 40th NMOS tube stated and the connection of the grid of the 41st NMOS tube and its connecting pin be it is described with it is non- Second input terminal of door, the source electrode of the 34th NMOS tube, the source electrode of the 35th NMOS tube, described the The source electrode of 36 NMOS tubes, the source electrode of the 37th NMOS tube, the 38th NMOS tube source electrode, described The source electrode of the 39th NMOS tube, the source electrode of the 40th NMOS tube, the 41st NMOS tube source electrode and The drain electrode of 42nd NMOS tube connects, grid, the 37th NMOS of the 36th NMOS tube The grid of pipe, the 38th NMOS tube grid connected with the grid of the 39th NMOS tube and its connecting pin For the second inverting input terminal of the NAND gate, the grid of the 42nd NMOS tube is the evaluation of the NAND gate Control terminal, the source electrode ground connection of the 42nd NMOS tube；It is 6th PMOS tube, the 7th PMOS tube, described The 8th PMOS tube, the 9th PMOS tube and the tenth PMOS tube be common threshold voltage PMOS tube, it is described 22nd NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube It is common threshold voltage NMOS tube with the 42nd NMOS tube, the 26th NMOS tube, the third It is ten NMOS tubes, the 31st NMOS tube, the 32nd NMOS tube, the 34th NMOS tube, described The 38th NMOS tube, the 39th NMOS tube and the 40th NMOS tube be low threshold voltage NMOS Pipe, the 27th NMOS tube, the 28th NMOS tube, the 29th NMOS tube, the third 13 NMOS tubes, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, institute The 41st NMOS tube stated is high threshold voltage NMOS tube.The NAND gate is realized using three-phase double track preliminary filling logic, is introduced The additional charging stage and discharge regime, the output end level of NAND gate is from supply voltage VDD within each duty cycle Start to be discharged to low level VSS, consume energy constant, there is energy consumption and the mutually independent feature of handled data, therefore Ability with good anti-power consumption attack, the lower seine that the 26th NMOS tube is constituted to the 41st NMOS tube in NAND gate The right and left NMOS tube is the same in network, and itself and the XOR gate circuit knot having the same based on three-phase double track preliminary filling logic Structure only realizes that NAND Logic function can not be from domain when being attacked by reverse-engineering by configuring the threshold voltage of NMOS tube Obtain correct logic function, therefore the ability with good anti-reverse-engineering.

The threshold voltage of the common threshold voltage PMOS tube is -0.404V, the common threshold voltage NMOS tube Threshold voltage be 0.397V, the threshold voltage of the low threshold voltage NMOS tube is 0.243V, the high threshold voltage The threshold voltage of NMOS tube is 0.489V.

Compared with the prior art, the advantages of the present invention are as follows by two XOR gates, three NAND gates, two preset numbers/ The work-based logic of reset circuit and nine buffers composition full subtracters, each XOR gate and each NAND gate is respectively three-phase double track Preliminary filling logic, two of them XOR gate, three NAND gates and nine buffers constitute a subtracters, the subtracter with two in advance It sets number/reset circuit and is combined together the full subtracter reconstructed, full subtracter is next in two preset number/reset circuit controls An evaluation operation is realized in period, and is divided into three phases in a cycle, when discharge control signal and preliminary filling control signal When into low level, full subtracter enters charging stage, and when evaluation signal becomes high level from low level, full subtracter realizes evaluation The function of circuit is realized in operation, and when discharge control signal becomes high level from low level, full subtracter enters discharge condition, is Evaluation operation next time is ready, and thus full subtracter of the invention passes through the XOR gate and three-phase of three-phase double track preliminary filling logic Basic unit of the NAND gate of double track preliminary filling logic as full subtracter, by configuring threshold voltage realization XOR logic and being patrolled with non- Function is collected, and is exported within each duty cycle and is discharged to low level since being pre-charged high level, consumes energy constant, With energy consumption and the mutually independent feature of handled data, defend reverse-engineering while attack with anti-DPA attack Characteristic, power consumption are lower.

Detailed description of the invention

Fig. 1 is the structural block diagram of full subtracter of the invention；

Fig. 2 is preset number/reset circuit circuit diagram of full subtracter of the invention；

Fig. 3 is the circuit diagram of the buffer of full subtracter of the invention；

Fig. 4 is the circuit diagram of the XOR gate of full subtracter of the invention；

Fig. 5 is the circuit diagram of the NAND gate of full subtracter of the invention；

Fig. 6 is the NOR gate circuit working timing figure of full subtracter of the invention；

Fig. 7 is the simulation curve figure of the NOR gate circuit function of full subtracter of the invention；

Fig. 8 is the simulation curve figure of the NAND gate circuit function of full subtracter of the invention；

Fig. 9 is the simulation curve figure of full subtracter of the invention.

Specific embodiment

The present invention will be described in further detail below with reference to the embodiments of the drawings.

Embodiment one: as shown in Figure 1, a kind of full subtracter realized using three-phase double track preliminary filling logic, including two exclusive or Door, three NAND gates, two preset number/reset circuits and nine buffers, the work of each XOR gate and each NAND gate are patrolled Collecting is respectively three-phase double track preliminary filling logic, and it is defeated that each XOR gate and each NAND gate are respectively provided with first input end, the first reverse phase Enter end, the second input terminal, the second inverting input terminal, preliminary filling control terminal, discharge control terminal, evaluation control terminal, output end and reverse phase Output end, each preset number/reset circuit are respectively provided with first input end, the second input terminal, third input terminal, the 4th input terminal And output end；Two XOR gates are referred to as the first XOR gate XOR1 and the second XOR gate XOR2, three NAND gates are distinguished Referred to as the first NAND gate NAND1, the second NAND gate NAND2 and third NAND gate NAND3, by two preset number/reset circuits point Also known as it is the first preset number/reset circuit PRESET1 and the second preset number/reset circuit PRESET2, nine buffers is distinguished Referred to as the first buffer buff1, the second buffer buff2, third buffer buff3, the 4th buffer buff4, the 5th buffering Device buff5, hex buffer buff6, the 7th buffer buff7, the 8th buffer buff8 and the 9th buffer buff9；First The connection of the first inverting input terminal of the first input end of XOR gate XOR1 and the second NAND gate NAND2 and its connecting pin are full subtracter First input end, for accessing minuend A, the first inverting input terminal of the first XOR gate XOR1 and the second NAND gate NAND2 First input end connection and its connecting pin be full subtracter the first inverting input terminal, for accessing the inversion signal of minuend AThe second input terminal of the second input terminal of first XOR gate XOR1 and the second NAND gate NAND2 connect and its connecting pin is complete The second input terminal for subtracting device, for accessing subtrahend B, the second inverting input terminal and the second NAND gate of the first XOR gate XOR1 The second inverting input terminal of NAND2 connects and its connecting pin is the second inverting input terminal of full subtracter, for accessing the anti-of subtrahend B Phase signalsThe preliminary filling control terminal of first XOR gate XOR1, the preliminary filling control terminal of the second NAND gate NAND2, the first buffer The connection of the input terminal of the input terminal of buff1 and the 4th buffer buff4 and its connecting pin are the preliminary filling control terminal of full subtracter, are used for It accesses preliminary filling and controls signal CHARGEB, the control of discharge of the discharge control terminal of the first XOR gate XOR1, the second NAND gate NAND2 Input terminal connection and its connecting pin the putting for full subtracter at end, the input terminal of the second buffer buff2 and the 5th buffer buff5 Electric control end, for accessing discharge control signal DISCHARGE, evaluation control terminal, the second NAND gate of the first XOR gate XOR1 The input terminal of the evaluation control terminal of NAND2, the input terminal of third buffer buff3 and hex buffer buff6 connects and it connects The evaluation control terminal that end is full subtracter is connect, for accessing evaluation control signal EVAL, the output end of the first XOR gate XOR1, second The connection of the first inverting input terminal of the first input end of XOR gate XOR2 and the first NAND gate NAND1, the first XOR gate XOR1's Reversed-phase output, the second XOR gate XOR2 the first inverting input terminal connected with the first input end of the first NAND gate NAND1, The connection of the second input terminal of the second input terminal of two XOR gate XOR2 and the first NAND gate NAND1 and its connecting pin are full subtracter Low level borrows signal input part, borrows signal Cn, the second anti-phase input of the second XOR gate XOR2 to one's own department or unit for accessing low level End connected with the second inverting input terminal of the first NAND gate NAND1 and its connecting pin for the reverse phase low level of full subtracter to borrow signal defeated Enter end, borrows the inversion signal Cnb of signal Cn for accessing low level to one's own department or unit, it is the output end of the first buffer buff1, second different Or the preliminary filling control terminal of door XOR2 is connected with the preliminary filling control terminal of the first NAND gate NAND1, the output of the second buffer buff2 It holds, the discharge control terminal of the second XOR gate XOR2 is connected with the discharge control terminal of the first NAND gate NAND1, third buffer The output end of buff3, the second XOR gate XOR2 evaluation control terminal connected with the evaluation control terminal of the first NAND gate NAND1, The connection of the input terminal of the output end of four buffer buff4 and the 7th buffer buff7, the output end of the 7th buffer buff7 and The preliminary filling control terminal of third NAND gate NAND3 connects, and the output end of the 5th buffer buff5 and the 8th buffer buff8's is defeated Enter end connection, the output end of the 8th buffer buff8 is connected with the discharge control terminal of third NAND gate NAND3, hex buffer The connection of the input terminal of the output end of buff6 and the 9th buffer buff9, the output end of the 9th buffer buff9 and third with it is non- The evaluation control terminal connection of door NAND3, the output end of the first NAND gate NAND1 and the first input end of third NAND gate NAND3 Connection, the reversed-phase output of the first NAND gate NAND1 connect with the first inverting input terminal of third NAND gate NAND3, second and The output end of NOT gate NAND2 is connected with the second input terminal of third NAND gate NAND3, the anti-phase output of the second NAND gate NAND2 End is connected with the second inverting input terminal of third NAND gate NAND3, and the output end of the second XOR gate XOR2 and the first preset number/answer The second input terminal connection of position circuit PRESET1, the reversed-phase output and the first preset number/reset circuit of the second XOR gate XOR2 The third input terminal of PRESET1 connects, the output end of third NAND gate NAND3 and the second preset number/reset circuit PRESET2 The connection of second input terminal, the reversed-phase output of third NAND gate NAND3 and the second preset number/reset circuit PRESET2 third Input terminal connection, the first preset number/reset circuit PRESET1 first input end and the second preset number/reset circuit PRESET2 First input end connection and its connecting pin be the full subtracter first preset/reset terminal, it is first preset/multiple for accessing Position signal M, the 4th input terminal of the first preset number/reset circuit PRESET1 and the second preset number/reset circuit PRESET2 The connection of 4th input terminal and its connecting pin are second preset/reset terminal of the full subtracter, for accessing second preset/reset Signal N, the first preset number/reset circuit PRESET1 output end is the poor output end of full subtracter, for exporting this potential difference CO, Second preset number/reset circuit PRESET2 output end borrows signal output end for full subtracter, for exporting one's own department or unit to a high position Borrow signal R.

Embodiment two: the present embodiment is substantially the same with embodiment one, and difference is as described below:

As shown in Fig. 2, in the present embodiment, each preset number/reset circuit respectively includes the one or two input and door AND1, the Two or two inputs and the input of door AND2 and two or door OR, the one or two input and door AND1, the two or two input and the input of door AND2 and two Or door OR is respectively provided with first input end, the second input terminal and output end, the one or two input and the first input end of door AND1 are The second input terminal of preset number/reset circuit first input end, the one or two input and door AND1 are preset number/reset circuit Second input terminal, the two or two input and the first input end of door AND2 are preset number/reset circuit third input terminal, the two or two The second input terminal of input and door AND2 are the 4th input terminal of preset number/reset circuit, and the one or two input is defeated with door AND1's Outlet connect with two inputs or the first input end of door OR, and the two or two input is inputted with the output end of door AND2 and two or door OR The output end of the connection of second input terminal, two inputs or door OR are preset number/reset circuit output end.

As shown in figure 3, each buffer respectively includes the first phase inverter INV1 and the second phase inverter in the present embodiment The input terminal of INV2, the first phase inverter INV1 are the input terminal of buffer, the output end and the second reverse phase of the first phase inverter INV1 The input terminal of device INV2 connects, and the output end of the second phase inverter INV2 is the output end of buffer.

As shown in figure 4, XOR gate includes the first PMOS tube P1, the second PMOS tube P2, third PMOS tube in the present embodiment P3, the 4th PMOS tube P4, the 5th PMOS tube P5, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS Pipe N4, the 5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS tube N9, the tenth NMOS tube N10, the 11st NMOS tube N11, the 12nd NMOS tube N12, the 13rd NMOS tube N13, the 14th NMOS tube N14, 15 NMOS tube N15, the 16th NMOS tube N16, the 17th NMOS tube N17, the 18th NMOS tube N18, the 19th NMOS tube N19, the 20th NMOS tube N20 and the 21st NMOS tube N21；The source electrode of first PMOS tube P1 accesses power vd D, the first PMOS The grid of the grid of pipe P1, the grid of the first NMOS tube N1 and the 4th NMOS tube N4 connects and its connecting pin is the electric discharge of XOR gate Control terminal, the drain electrode of the first PMOS tube P1, the source electrode of the second PMOS tube P2, the source electrode of third PMOS tube P3, the 4th PMOS tube P4 Source electrode and the 5th PMOS tube P5 source electrode connection, the grid connection of the grid of the second PMOS tube P2 and the 5th PMOS tube P5 and its Connecting pin is the preliminary filling control terminal of XOR gate, the drain electrode of the second PMOS tube P2, the drain electrode of third PMOS tube P3, the first NMOS tube N1 Drain electrode, the drain electrode of the second NMOS tube N2, the grid of the 4th PMOS tube P4 are connected with the grid of third NMOS tube N3 and it is connected End be XOR gate output end, the grid of third PMOS tube P3, the grid of the second NMOS tube N2, the 4th PMOS tube P4 drain electrode, The drain electrode of third NMOS tube N3, the drain electrode of the 5th PMOS tube P5 are connected with the drain electrode of the 4th NMOS tube N4 and its connecting pin is exclusive or The reversed-phase output of door；The source electrode of first NMOS tube N1 is grounded VSS, the leakage of the source electrode, the 5th NMOS tube N5 of the second NMOS tube N2 Pole, the drain electrode of the 6th NMOS tube N6, the drain electrode of the 7th NMOS tube N7 are connected with the drain electrode of the 8th NMOS tube N8, third NMOS tube N3 Source electrode, the drain electrode of the 9th NMOS tube N9, the drain electrode of the tenth NMOS tube N10, the drain electrode and the 12nd of the 11st NMOS tube N11 The drain electrode of NMOS tube N12 connects, and the source electrode of the 4th NMOS tube N4 is grounded VSS, grid, the 7th NMOS tube N7 of the 5th NMOS tube N5 Grid, the tenth NMOS tube N10 grid and the 12nd NMOS tube N12 grid connection and its connecting pin be XOR gate first Input terminal, the drain electrode connection of the source electrode and the 13rd NMOS tube N13 of the 5th NMOS tube N5, the grid of the 6th NMOS tube N6, the 8th The grid of the grid of NMOS tube N8, the grid of the 9th NMOS tube N9 and the 11st NMOS tube N11 connects and its connecting pin is exclusive or First inverting input terminal of door, the drain electrode connection of the source electrode and the 14th NMOS tube N14 of the 6th NMOS tube N6, the 7th NMOS tube N7 Source electrode and the 15th NMOS tube N15 drain electrode connection, the drain electrode of the source electrode of the 8th NMOS tube N8 and the 16th NMOS tube N16 connects It connects, the drain electrode connection of the source electrode and the 17th NMOS tube N17 of the 9th NMOS tube N9, the source electrode and the 18th of the tenth NMOS tube N10 The drain electrode of NMOS tube N18 connects, the drain electrode connection of the source electrode and the 19th NMOS tube N19 of the 11st NMOS tube N11, and the 12nd The drain electrode of the source electrode of NMOS tube N12 and the 20th NMOS tube N20 connect, the grid of the 13rd NMOS tube N13, the 14th NMOS tube The grid of the grid of N14, the grid of the 19th NMOS tube N19 and the 20th NMOS tube N20 connects and its connecting pin is XOR gate The second input terminal, the source of the source electrode of the 13rd NMOS tube N13, the source electrode of the 14th NMOS tube N14, the 15th NMOS tube N15 Pole, the source electrode of the 16th NMOS tube N16, the source electrode of the 17th NMOS tube N17, the source electrode of the 18th NMOS tube N18, the 19th The drain electrode of the source electrode of NMOS tube N19, the source electrode of the 20th NMOS tube N20 and the 21st NMOS tube N21 connects, the 15th NMOS The grid of pipe N15, the grid of the 16th NMOS tube N16, the grid of the 17th NMOS tube N17 and the grid of the 18th NMOS tube N18 Pole connection and its connecting pin are the second inverting input terminal of XOR gate, and the grid of the 21st NMOS tube N21 is asking for XOR gate It is worth control terminal, the source electrode of the 21st NMOS tube N21 is grounded VSS, the first PMOS tube P1, the second PMOS tube P2, third PMOS tube P3, the 4th PMOS tube P4 and the 5th PMOS tube P5 are common threshold voltage PMOS tube, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4 and the 21st NMOS tube N21 are common threshold voltage NMOS tube, and the 5th NMOS tube N5, the 8th NMOS tube N8, the tenth NMOS tube N10, the 11st NMOS tube N11, the 13rd NMOS tube N13, the 16th NMOS tube N16, the 18th NMOS tube N18 and the 19th NMOS tube N19 are low threshold voltage NMOS tube, the 6th NMOS tube N6, 7th NMOS tube N7, the 9th NMOS tube N9, the 12nd NMOS tube N12, the 14th NMOS tube N14, the 15th NMOS tube N15, 17 NMOS tube N17, the 20th NMOS tube N20 are high threshold voltage NMOS tube.

As shown in figure 3, each NAND gate respectively includes the 6th PMOS tube P6, the 7th PMOS tube P7, the 8th in the present embodiment PMOS tube P8, the 9th PMOS tube P9, the tenth PMOS tube P10, the 22nd NMOS tube N22, the 23rd NMOS tube N23, second 14 NMOS tube N24, the 25th NMOS tube N25, the 26th NMOS tube N26, the 27th NMOS tube N27, the 28th NMOS tube N28, the 29th NMOS tube N29, the 30th NMOS tube N30, the 31st NMOS tube N31, the 32nd NMOS tube N32, the 33rd NMOS tube N33, the 34th NMOS tube N34, the 35th NMOS tube N35, the 36th NMOS tube N36, 37th NMOS tube N37, the 38th NMOS tube N38, the 39th NMOS tube N39, the 40th NMOS tube N40, the 40th One NMOS tube N41 and the 42nd NMOS tube N42；The source electrode of 6th PMOS tube P6 accesses power vd D, the grid of the 6th PMOS tube P6 The grid of pole, the grid of the 22nd NMOS tube N22 and the 25th NMOS tube N25 connects and its connecting pin is putting for NAND gate Electric control end, the drain electrode of the 6th PMOS tube P6, the 7th PMOS tube P7 source electrode, the source electrode of the 8th PMOS tube P8, the 9th PMOS tube The connection of the source electrode of the source electrode of P9 and the tenth PMOS tube P10, the grid connection of the grid and the tenth PMOS tube P10 of the 7th PMOS tube P7 And its connecting pin is the preliminary filling control terminal of NAND gate, the drain electrode of the 7th PMOS tube P7, the drain electrode of the 8th PMOS tube P8, the 22nd The drain electrode of NMOS tube N22, the drain electrode of the 23rd NMOS tube N23, the 9th PMOS tube P9 grid and the 24th NMOS tube N24 Grid connection and its connecting pin be NAND gate output end, the grid of the grid of the 8th PMOS tube P8, the 23rd NMOS tube N23 Pole, the drain electrode of the 9th PMOS tube P9, the drain electrode of the 24th NMOS tube N24, the drain electrode and the 25th of the tenth PMOS tube P10 The drain electrode of NMOS tube N25 connects and its connecting pin is the reversed-phase output of NAND gate；The source electrode of 22nd NMOS tube N22 is grounded The drain electrode of the source electrode, the 26th NMOS tube N26 of VSS, the 23rd NMOS tube N23, the drain electrode of the 27th NMOS tube N27, The drain electrode of 28th NMOS tube N28 is connected with the drain electrode of the 29th NMOS tube N29, the source electrode of the 24th NMOS tube N24, The drain electrode of 30th NMOS tube N30, the drain electrode of the 31st NMOS tube N31, the drain electrode and the 30th of the 32nd NMOS tube N32 The drain electrode of three NMOS tube N33 connects, the source electrode ground connection VSS of the 25th NMOS tube N25, the grid of the 26th NMOS tube N26, The grid of the grid of 28th NMOS tube N28, the grid of the 31st NMOS tube N31 and the 33rd NMOS tube N33 connects And its connecting pin is the first input end of NAND gate, the leakage of the source electrode and the 34th NMOS tube N34 of the 26th NMOS tube N26 Pole connection, the grid of the 27th NMOS tube N27, the grid of the 29th NMOS tube N29, the 30th NMOS tube N30 grid It is connected with the grid of the 32nd NMOS tube N32 and its connecting pin is the first inverting input terminal of NAND gate, the 27th NMOS The drain electrode of the source electrode of pipe N27 and the 35th NMOS tube N35 connect, the source electrode and the 36th of the 28th NMOS tube N28 The drain electrode of NMOS tube N36 connects, the drain electrode connection of the source electrode and the 37th NMOS tube N37 of the 29th NMOS tube N29, third The drain electrode connection of the source electrode and the 38th NMOS tube N38 of ten NMOS tube N30, the source electrode and third of the 31st NMOS tube N31 The drain electrode of 19 NMOS tube N39 connects, the drain electrode connection of the source electrode and the 40th NMOS tube N40 of the 32nd NMOS tube N32, the The drain electrode connection of the source electrode of 33 NMOS tube N33 and the 41st NMOS tube N41, the grid of the 34th NMOS tube N34, the The grid of the grid of 35 NMOS tube N35, the grid of the 40th NMOS tube N40 and the 41st NMOS tube N41 connects and it Connecting pin is the second input terminal of NAND gate, the source electrode of the 34th NMOS tube N34, the source electrode of the 35th NMOS tube N35, the The source electrode of 36 NMOS tube N36, the source electrode of the 37th NMOS tube N37, the source electrode of the 38th NMOS tube N38, the 30th The source electrode of nine NMOS tube N39, the source electrode of the 40th NMOS tube N40, the 41st NMOS tube N41 source electrode and the 42nd NMOS The drain electrode of pipe N42 connects, grid, the 38th NMOS of the grid of the 36th NMOS tube N36, the 37th NMOS tube N37 The connection of the grid of the grid of pipe N38 and the 39th NMOS tube N39 and its connecting pin are the second inverting input terminal of NAND gate, the The grid of 42 NMOS tube N42 is the evaluation control terminal of NAND gate, and the source electrode of the 42nd NMOS tube N42 is grounded VSS；6th PMOS tube P6, the 7th PMOS tube P7, the 8th PMOS tube P8, the 9th PMOS tube P9 and the tenth PMOS tube P10 are common threshold value electricity Press PMOS tube, the 22nd NMOS tube N22, the 23rd NMOS tube N23, the 24th NMOS tube N24, the 25th NMOS tube N25 and the 42nd NMOS tube N42 is common threshold voltage NMOS tube, the 26th NMOS tube N26, the 30th NMOS tube N30, the 31st NMOS tube N31, the 32nd NMOS tube N32, the 34th NMOS tube N34, the 38th NMOS tube N38, 39th NMOS tube N39 and the 40th NMOS tube N40 is low threshold voltage NMOS tube, the 27th NMOS tube N27, second 18 NMOS tube N28, the 29th NMOS tube N29, the 33rd NMOS tube N33, the 35th NMOS tube N35, the 36th NMOS tube N36, the 37th NMOS tube N37 and the 41st NMOS tube N41 are high threshold voltage NMOS tube.

In the present embodiment, the threshold voltage of common threshold voltage PMOS tube is -0.404V, common threshold voltage NMOS tube Threshold voltage is 0.397V, and the threshold voltage of low threshold voltage NMOS tube is 0.243V, the threshold value electricity of high threshold voltage NMOS tube Pressure is 0.489V.

The truth table of full subtracter of the invention is as shown in table 1, full subtracter export R when Kano chart it is as shown in table 2, subtract entirely For Kano chart when device output Co as shown in figure 3, preset number/reset circuit truth table is as shown in table 4, preset number/reset is electric The Kano chart on road is as shown in table 5.According to the output end expression formula of 3 full subtracter of table 1, table 2 and table are as follows: WithAccording to table 4 and table 5 it is found that by taking full subtracter output is R as an example, preset number/reset circuit output end Expression formula:

Table 1

Table 2

Table 3

Table 4

Table 5

The NOR gate circuit working sequence of full subtracter of the invention is as shown in Figure 6.Known to analysis chart 6: of the invention subtracts entirely The XOR gate course of work of device is divided into precharge, evaluation and electric discharge three phases.When CHARGEB, DISCHARGE and EVAL are When low level, XOR gate enters pre-charging stage, the first PMOS tube P1, the second PMOS tube P2 and the conducting of the 5th PMOS tube P5 pipe, The output end OUT and reversed-phase output of XOR gateIt is precharged to high level；As EVAL and CHARGEB become high level, Second PMOS tube P2 and the 5th PMOS tube P5 cut-off, circuit precharge terminates, while the 21st NMOS tube as evaluation pipe N21 conducting, circuit enters the evaluation stage, at this time A=1, B=1, the 5th NMOS tube N5 in pulldown network, the 6th NMOS tube N6, the Before the grid voltage of 19 NMOS tube N19 and the 20th NMOS tube N20 conducting, the second NMOS tube N2 and third NMOS tube N3 Preliminary filling is to high level, thus the second NMOS tube N2 has electric current I1 to flow through, and third NMOS tube N3 has electric current I2 to flow through, due to the 5th NMOS tube N5 and the 6th NMOS tube N6 is Low threshold pipe, at this time by the 3rd PNOS pipe P3, the 4th PMOS tube P4, the second NMOS tube The sense amplifier that N2, third NMOS tube N3 are constituted amplifies the current difference between electric current I1 and electric current I2, the output of XOR gate End OUT takes the lead in being discharged to low level, the 4th PMOS tube P4 conducting, the reversed-phase output of XOR gateStill maintain high level； When EVAL is low level, when DISCHARGE becomes high level, the 21st NMOS tube N21 cut-off, evaluation terminates, while first NMOS tube N1 and the 4th NMOS tube N4 conducting, circuit enter discharge regime, the output end OUT and reversed-phase output of XOR gate It is discharged to low level, a duty cycle terminates, and realizes XOR logic function.

The simulation curve of the NOR gate circuit function of full subtracter of the invention is as shown in Figure 7；Full subtracter of the invention with The simulation curve of not circuit function is as shown in Figure 8；The simulation curve of full subtracter of the invention is as shown in Figure 9；Analysis chart 7 can Know, XOR gate of the invention, NAND gate and full subtracter are respectively provided with correct logic function.

Claims (6)

1. it is a kind of using three-phase double track preliminary filling logic realize full subtracter, it is characterised in that including two XOR gates, three with it is non- The work of door, two preset number/reset circuits and nine buffers, each XOR gate and each NAND gate is patrolled Collecting is respectively three-phase double track preliminary filling logic, and each XOR gate and each described NAND gate are respectively provided with the first input End, the first inverting input terminal, the second input terminal, the second inverting input terminal, preliminary filling control terminal, discharge control terminal, evaluation control terminal, Output end and reversed-phase output, the preset number/reset circuit are respectively provided with first input end, the second input terminal, the Three input terminals, the 4th input terminal and output end；XOR gate described in two is referred to as the first XOR gate and the second XOR gate, NAND gate described in three is referred to as the first NAND gate, the second NAND gate and third NAND gate, it will be preset described in two Number/reset circuit is referred to as the first preset number/reset circuit and the second preset number/reset circuit, by buffering described in nine Device be referred to as the first buffer, the second buffer, third buffer, the 4th buffer, the 5th buffer, hex buffer, 7th buffer, the 8th buffer and the 9th buffer；The first input end of first XOR gate and described second with First inverting input terminal of NOT gate connects and its connecting pin is the first input end of the full subtracter, for accessing minuend, First inverting input terminal of first XOR gate is connected with the first input end of second NAND gate and its connecting pin For the first inverting input terminal of the full subtracter, for accessing the inversion signal of minuend, the of first XOR gate Two input terminals are connected with the second input terminal of second NAND gate and its connecting pin is the second input of the full subtracter End, for accessing subtrahend, the second reverse phase of the second inverting input terminal of first XOR gate and second NAND gate Input terminal connection and its connecting pin are the second inverting input terminal of the full subtracter, for accessing the inversion signal of subtrahend, institute The preliminary filling control terminal for the first XOR gate stated, the preliminary filling control terminal of second NAND gate, first buffer it is defeated Enter end connected with the input terminal of the 4th buffer and its connecting pin for the full subtracter preliminary filling control terminal, for connecing Enter preliminary filling control signal, it is the discharge control terminal of first XOR gate, the discharge control terminal of second NAND gate, described The input terminal of the second buffer connect with the input terminal of the 5th buffer and its connecting pin is the full subtracter Discharge control terminal, for accessing discharge control signal, the evaluation control terminal of first XOR gate, second NAND gate Evaluation control terminal, the third buffer input terminal connected with the input terminal of the hex buffer and its connecting pin It is the output end of first XOR gate, described for accessing evaluation control signal for the evaluation control terminal of the full subtracter The first input end of the second XOR gate connected with the first inverting input terminal of first NAND gate, first exclusive or Reversed-phase output, the first inverting input terminal of second XOR gate and the first input end of first NAND gate of door Connection, the second input terminal of second XOR gate is connected with the second input terminal of first NAND gate and its connecting pin Low level for the full subtracter borrows signal input part, borrows signal, second exclusive or to one's own department or unit for accessing low level Second inverting input terminal of door connect with the second inverting input terminal of first NAND gate and its connecting pin is described complete The reverse phase low level for subtracting device borrows signal input part, borrows the inversion signal of signal for accessing low level to one's own department or unit, and described first The preliminary filling control terminal of the output end of buffer, the preliminary filling control terminal of second XOR gate and first NAND gate connects It connects, the output end of second buffer, the discharge control terminal of second XOR gate and first NAND gate Discharge control terminal connection, the output end of the third buffer, the evaluation control terminal of second XOR gate and described The evaluation control terminal of first NAND gate connects, the output end of the 4th buffer and the input terminal of the 7th buffer Connection, the output end of the 7th buffer are connected with the preliminary filling control terminal of the third NAND gate, and the described the 5th is slow The output end for rushing device is connected with the input terminal of the 8th buffer, the output end of the 8th buffer and described The discharge control terminal of three NAND gates connects, and the input terminal of the output end of the hex buffer and the 9th buffer connects Connect, the output end of the 9th buffer is connected with the evaluation control terminal of the third NAND gate, described first with it is non- The output end of door is connected with the first input end of the third NAND gate, the reversed-phase output of first NAND gate and institute First inverting input terminal of the third NAND gate stated connects, the output end of second NAND gate and the third NAND gate The second input terminal connection, the second anti-phase input of the reversed-phase output of second NAND gate and the third NAND gate End connection, the output end of second XOR gate are connected with the second input terminal of first preset number/reset circuit, institute The reversed-phase output for the second XOR gate stated is connected with first preset number/reset circuit third input terminal, described The output end of third NAND gate is connected with the second input terminal of second preset number/reset circuit, the third with it is non- The reversed-phase output of door is connected with second preset number/reset circuit third input terminal, first preset number/multiple The first input end of position circuit is connected with second preset number/reset circuit first input end and its connecting pin is described Full subtracter first preset/reset terminal, for access first preset/reset signal, first preset number/reset circuit The 4th input terminal connected with the 4th input terminal of second preset number/reset circuit and its connecting pin is described to subtract entirely The second of device be preset/reset terminal, for accessing second preset/reset signal, the output of first preset number/reset circuit End is the poor output end of the full subtracter, and for exporting this potential difference, second preset number/reset circuit output end is The full subtracter borrows signal output end, borrows signal to a high position for exporting one's own department or unit.

2. a kind of full subtracter realized using three-phase double track preliminary filling logic according to claim 1, it is characterised in that each Preset number/the reset circuit respectively includes the one or two input and door, the two or two input and door and two inputs or door, described One or two input is respectively provided with first input end, second with door, the two or two input and door and two inputs or door The first input end of input terminal and output end, the one or two input and door is the preset number/reset circuit first Second input terminal of input terminal, the one or two input and door is second input terminal of preset number/reset circuit, institute The two or two input and the first input end of door stated are preset number/reset circuit third input terminal, described second Two inputs are the 4th input terminal of preset number/reset circuit with the second input terminal of door, the one or two input with The output end of door is connected with the first input end of two inputs or door, output end and institute of the two or two input with door The output end of the second input terminal connection of two inputs or door stated, two inputs or door is the preset number/reset electricity The output end on road.

3. a kind of full subtracter realized using three-phase double track preliminary filling logic according to claim 1, it is characterised in that each The buffer respectively includes the first phase inverter and the second phase inverter, and the input terminal of first phase inverter is described delays The input terminal of device is rushed, the output end of first phase inverter is connected with the input terminal of second phase inverter, and described The output end of two phase inverters is the output end of the buffer.

4. a kind of full subtracter realized using three-phase double track preliminary filling logic according to claim 1, it is characterised in that each The XOR gate respectively includes the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, One NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, Eight NMOS tubes, the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, second Ten NMOS tubes and the 21st NMOS tube；The source electrode of first PMOS tube accesses power supply, the grid of first PMOS tube Pole, first NMOS tube grid connected with the grid of the 4th NMOS tube and its connecting pin be the XOR gate Discharge control terminal, the drain electrode of first PMOS tube, the source electrode of second PMOS tube, the third PMOS tube Source electrode, the 4th PMOS tube source electrode connected with the source electrode of the 5th PMOS tube, the grid of second PMOS tube Pole connected with the grid of the 5th PMOS tube and its connecting pin be the XOR gate preliminary filling control terminal, described second The drain electrode of PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of first NMOS tube, second NMOS tube It drains, the grid of the 4th PMOS tube is connected with the grid of the third NMOS tube and its connecting pin is the exclusive or Door output end, the grid of the third PMOS tube, second NMOS tube grid, the 4th PMOS tube leakage Pole, the drain electrode of the third NMOS tube, the drain electrode of the 5th PMOS tube are connected with the drain electrode of the 4th NMOS tube And its connecting pin is the reversed-phase output of the XOR gate；The source electrode of first NMOS tube is grounded, and described second The source electrode of NMOS tube, the drain electrode of the 5th NMOS tube, the drain electrode of the 6th NMOS tube, the 7th NMOS tube Drain electrode is connected with the drain electrode of the 8th NMOS tube, the leakage of the source electrode of the third NMOS tube, the 9th NMOS tube Pole, the drain electrode of the tenth NMOS tube, the drain electrode of the 11st NMOS tube and the drain electrode of the 12nd NMOS tube Connection, the source electrode ground connection of the 4th NMOS tube, the grid of the grid of the 5th NMOS tube, the 7th NMOS tube Pole, the tenth NMOS tube grid connected with the grid of the 12nd NMOS tube and its connecting pin be the exclusive or The first input end of door, the source electrode of the 5th NMOS tube connects with the drain electrode of the 13rd NMOS tube, and described the The grid of six NMOS tubes, the grid of the 8th NMOS tube, the 9th NMOS tube grid and the described the 11st The grid of NMOS tube connects and its connecting pin is the first inverting input terminal of the XOR gate, the source of the 6th NMOS tube Pole is connected with the drain electrode of the 14th NMOS tube, the source electrode of the 7th NMOS tube and the 15th NMOS tube Drain electrode connection, the source electrode of the 8th NMOS tube are connected with the drain electrode of the 16th NMOS tube, the 9th NMOS The source electrode of pipe is connected with the drain electrode of the 17th NMOS tube, the source electrode and the described the 18th of the tenth NMOS tube The drain electrode of NMOS tube connects, and the source electrode of the 11st NMOS tube is connected with the drain electrode of the 19th NMOS tube, described The source electrode of the 12nd NMOS tube connected with the drain electrode of the 20th NMOS tube, the grid of the 13rd NMOS tube, The grid of the grid of 14th NMOS tube, the grid of the 19th NMOS tube and the 20th NMOS tube connects It connects and its connecting pin is the second input terminal of the XOR gate, the source electrode of the 13rd NMOS tube, the described the 14th The source electrode of NMOS tube, the source electrode of the 15th NMOS tube, the source electrode of the 16th NMOS tube, the described the 17th The source electrode of NMOS tube, the source electrode of the 18th NMOS tube, the source electrode of the 19th NMOS tube, the described the 20th The source electrode of NMOS tube is connected with the drain electrode of the 21st NMOS tube, the grid of the 15th NMOS tube, described The grid of 16th NMOS tube, the 17th NMOS tube grid connected with the grid of the 18th NMOS tube and its Connecting pin is the second inverting input terminal of the XOR gate, and the grid of the 21st NMOS tube is the XOR gate Evaluation control terminal, the 21st NMOS tube source electrode ground connection, first PMOS tube, the 2nd PMOS Pipe, the third PMOS tube, the 4th PMOS tube and the 5th PMOS tube are common threshold voltage PMOS tube, First NMOS tube, second NMOS tube, the third NMOS tube, the 4th NMOS tube and described 21 NMOS tubes are common threshold voltage NMOS tube, the 5th NMOS tube, the 8th NMOS tube, described Ten NMOS tubes, the 11st NMOS tube, the 13rd NMOS tube, the 16th NMOS tube, the described the tenth Eight NMOS tubes and the 19th NMOS tube are low threshold voltage NMOS tube, the 6th NMOS tube, the described the 7th NMOS tube, the 9th NMOS tube, the 12nd NMOS tube, the 14th NMOS tube, the described the 15th NMOS tube, the 17th NMOS tube, the 20th NMOS tube are high threshold voltage NMOS tube.

5. a kind of full subtracter realized using three-phase double track preliminary filling logic according to claim 1, it is characterised in that each The NAND gate respectively includes the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube, 22 NMOS tubes, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube, the 26th NMOS tube, second 17 NMOS tubes, the 28th NMOS tube, the 29th NMOS tube, the 30th NMOS tube, the 31st NMOS tube, the 32nd NMOS tube, the 33rd NMOS tube, the 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, the 38th NMOS tube, the 39th NMOS tube, the 40th NMOS tube, the 41st NMOS tube and the 42nd NMOS tube；The source electrode of 6th PMOS tube accesses power supply, the grid of the 6th PMOS tube, the described the 22nd The grid of NMOS tube is connected with the grid of the 25th NMOS tube and its connecting pin is the electric discharge control of the NAND gate End processed, the drain electrode of the 6th PMOS tube, the source electrode of the 7th PMOS tube, the source electrode of the 8th PMOS tube, institute The source electrode for the 9th PMOS tube stated is connected with the source electrode of the tenth PMOS tube, the grid of the 7th PMOS tube and described The tenth PMOS tube grid connection and its connecting pin be the NAND gate preliminary filling control terminal, the 7th PMOS tube Drain electrode, the drain electrode of the 8th PMOS tube, the drain electrode of the 22nd NMOS tube, the 23rd NMOS tube It drains, the grid of the 9th PMOS tube is connected with the grid of the 24th NMOS tube and its connecting pin is described The output end of NAND gate, the grid of the 8th PMOS tube, the grid of the 23rd NMOS tube, the described the 9th The drain electrode of PMOS tube, the drain electrode of the 24th NMOS tube, the drain electrode and the described the 20th of the tenth PMOS tube The drain electrode of five NMOS tubes connects and its connecting pin is the reversed-phase output of the NAND gate；22nd NMOS tube Source electrode ground connection, the source electrode of the 23rd NMOS tube, the drain electrode of the 26th NMOS tube, the described the 27th The drain electrode of NMOS tube, the drain electrode of the 28th NMOS tube are connected with the drain electrode of the 29th NMOS tube, described The source electrode of the 24th NMOS tube, the drain electrode of the 30th NMOS tube, the drain electrode of the 31st NMOS tube, institute The drain electrode for the 32nd NMOS tube stated is connected with the drain electrode of the 33rd NMOS tube, the 25th NMOS tube Source electrode ground connection, the grid of the 26th NMOS tube, the grid of the 28th NMOS tube, the described the 30th The grid of one NMOS tube is connected with the grid of the 33rd NMOS tube and its connecting pin is the first of the NAND gate The source electrode of input terminal, the 26th NMOS tube is connected with the drain electrode of the 34th NMOS tube, and described second The grid of 17 NMOS tubes, the grid of the 29th NMOS tube, the grid of the 30th NMOS tube and described The grid of 32nd NMOS tube connects and its connecting pin is the first inverting input terminal of the NAND gate, and the described the 20th The source electrode of seven NMOS tubes is connected with the drain electrode of the 35th NMOS tube, the source electrode of the 28th NMOS tube and institute The drain electrode for the 36th NMOS tube stated connects, the source electrode of the 29th NMOS tube and the 37th NMOS tube Drain electrode connection, the source electrode of the 30th NMOS tube connects with the drain electrode of the 38th NMOS tube, described the The source electrode of 31 NMOS tubes is connected with the drain electrode of the 39th NMOS tube, the source electrode of the 32nd NMOS tube It is connected with the drain electrode of the 40th NMOS tube, the source electrode and the 41st NMOS of the 33rd NMOS tube The drain electrode of pipe connects, the grid of the 34th NMOS tube, the grid of the 35th NMOS tube, the described the 4th The grid of ten NMOS tubes is connected with the grid of the 41st NMOS tube and its connecting pin is the second of the NAND gate Input terminal, the source electrode of the 34th NMOS tube, the source electrode of the 35th NMOS tube, the described the 36th The source electrode of NMOS tube, the source electrode of the 37th NMOS tube, the source electrode of the 38th NMOS tube, the third The source electrode of 19 NMOS tubes, the source electrode of the 40th NMOS tube, the source electrode of the 41st NMOS tube and described The drain electrode of 42nd NMOS tube connects, the grid of the grid of the 36th NMOS tube, the 37th NMOS tube Pole, the 38th NMOS tube grid connected with the grid of the 39th NMOS tube and its connecting pin is described NAND gate the second inverting input terminal, the grid of the 42nd NMOS tube is that the evaluation of the NAND gate controls End, the source electrode ground connection of the 42nd NMOS tube；6th PMOS tube, the 7th PMOS tube, described Eight PMOS tube, the 9th PMOS tube and the tenth PMOS tube are common threshold voltage PMOS tube, and described second 12 NMOS tubes, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube and institute The 42nd NMOS tube stated is common threshold voltage NMOS tube, the 26th NMOS tube, the described the 30th It is NMOS tube, the 31st NMOS tube, the 32nd NMOS tube, the 34th NMOS tube, described 38th NMOS tube, the 39th NMOS tube and the 40th NMOS tube are low threshold voltage NMOS tube, 27th NMOS tube, the 28th NMOS tube, the 29th NMOS tube, the described the 33rd It is NMOS tube, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, described 41st NMOS tube is high threshold voltage NMOS tube.

6. a kind of full subtracter realized using three-phase double track preliminary filling logic according to claim 4 or 5, it is characterised in that institute The threshold voltage for the common threshold voltage PMOS tube stated is -0.404V, the threshold voltage of the common threshold voltage NMOS tube For 0.397V, the threshold voltage of the low threshold voltage NMOS tube is 0.243V, the threshold of the high threshold voltage NMOS tube Threshold voltage is 0.489V.