CN113470715A - Full-subtracting device applying MTJ (magnetic tunnel junction) - Google Patents

Full-subtracting device applying MTJ (magnetic tunnel junction) Download PDF

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CN113470715A
CN113470715A CN202110821028.1A CN202110821028A CN113470715A CN 113470715 A CN113470715 A CN 113470715A CN 202110821028 A CN202110821028 A CN 202110821028A CN 113470715 A CN113470715 A CN 113470715A
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nmos tube
tube
electrode
nmos
drain electrode
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CN113470715B (en
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王晨旭
宫月红
罗敏
王新胜
常亮
蔡济济
石薇
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Shandong Jiaotong University
Innovation Academy for Microsatellites of CAS
Harbin Institute of Technology Weihai
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Shandong Jiaotong University
Innovation Academy for Microsatellites of CAS
Harbin Institute of Technology Weihai
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

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Abstract

A full-reduction device applying MTJ solves the problem that write-in power consumption is increased due to the fact that an MOS tube is added in the direction of power supply voltage when the MTJ of the full-reduction device is written at any time, and belongs to the technical field of electronic circuits. The invention relates to a full-subtracting device applying MTJ, which comprises a 1-bit full-subtracting device, two write-in circuits and two clock logic control circuits; the clock signals output by the two clock logic control circuits simultaneously send two write-in circuits; the clock logic control circuits are all realized by NOR gate circuits; the three inputs of the clock logic control circuit comprise a full-subtracter working clock, a positive/negative writing enabling control signal and a positive/negative writing input clock signal. The invention controls the clock of the write-in circuit by adding the control gate, reduces the quantity of MOS tubes in the clock power supply voltage direction of the write-in circuit, and achieves the purpose of reducing the write-in power consumption.

Description

Full-subtracting device applying MTJ (magnetic tunnel junction)
Technical Field
The invention relates to a full-reduction device, in particular to a full-reduction device applying MTJ (magnetic tunnel junction), belonging to the technical field of electronic circuits.
Background
Further development of mobile communication technology puts higher requirements on the performance and power consumption of the analog-to-digital conversion circuit of the signal receiving end. In order to improve the performance of Analog to Digital converters (ADCs), the application of new memory devices in Digital correction circuits is a promising design direction. Memory development also encounters bottlenecks as integrated circuit fabrication technology evolves further. Currently, the conventional memory has the problems of high power consumption, limited access speed, low storage density, easy loss in storage and the like. Spin transfer torque Magnetic random access memory (STT-MRAM) based on Magnetic Tunnel Junction (MTJ) has the advantages of low power consumption, high speed, high storage density, nonvolatility, easy 3d integration and the like, and has wide application prospect, thereby becoming a new memory research direction. The STT-MRAM is applied to the analog-to-digital conversion circuit, so that the energy efficiency of the analog-to-digital converter can be further improved, and the STT-MRAM has very important significance for the development of mobile communication technology and the development of the whole information industry.
Currently, there have been some corresponding research results on the performance of MTJ devices and applications of MTJs, such as studying the magnetic sensitivity and spin injection characteristics of MgO-based magnetic tunnel junctions, applying MTJs as memory devices in Look-Up tables (LUTs), and applying full reducers of MTJ memory devices.
Some of the existing functional circuits applying the MTJ can only write the MTJ once, and some of the functional circuits can write the MTJ periodically by setting regular clocks (clk1 and clk2), so that the functional circuits cannot ensure that the functional circuits have two functions of writing at any time and periodically writing. If writing is needed at any time, a control MOS tube is generally added in the direction of the power supply voltage of the writing circuit, and the grid electrode of the MOS tube is connected with a writing enable signal EN, as shown in fig. 1, the number of the MOS tubes in the direction of the writing power supply is increased, so that the power supply voltage required for maintaining conduction is increased, and the MTJ writing power consumption is increased.
Disclosure of Invention
Aiming at the problem that the write-in power consumption is increased due to the mode of adding an MOS tube in the direction of power voltage when the MTJ of the full reducer is written at any time, the invention provides the full reducer applying the MTJ, which saves the power consumption.
The invention relates to a full-subtracting device applying MTJ, which comprises a 1-bit full-subtracting device, two write-in circuits and two clock logic control circuits;
the 1-bit full subtracter comprises a difference circuit and a borrow bit circuit, wherein the difference circuit and the borrow bit circuit respectively comprise two MTJs, and the MTJ1 and the MTJ2 of the difference circuit are respectively used for storing a borrow variable C during difference calculationiBorrow inverse volume
Figure BDA0003171945700000021
The MTJ3 and MTJ4 of the borrow circuit are used to store the borrow variable C during borrow respectivelyiBorrow inverse volume
Figure BDA0003171945700000022
MTJ1 has the same resistance state as MTJ3, MTJ2 has the same resistance state as MTJ4, and MTJ1 has the opposite resistance state as MTJ 2;
each write circuit has two input clock signals clk1 and clk2, when clk1 is 0, a forward current is input to MTJ1 and MTJ3, a reverse current is input to MTJ2 and MTJ4, when clk2 is 0, a forward current is input to MTJ2 and MTJ4, and a reverse current is input to MTJ1 and MTJ 3; the clock signals clk1 and clk2 cannot be 0 at the same time;
the clock signal clk1 output by the No. 1 clock logic control circuit simultaneously transmits two write-in circuits, and the clock signal clk2 output by the No. 2 clock logic control circuit simultaneously transmits two write-in circuits;
the clock logic control circuits are all realized by NOR gate circuits;
the three inputs of the clock logic control circuit No. 1 comprise clk, en1 and clkw1, wherein clk represents a full-subtracting device working clock, en1 represents an enabling control signal for the forward writing of the writing circuit, clkw1 represents an input clock signal for the forward writing of the writing circuit, and the output of the clock logic control circuit No. 1 is a clock signal clk 1; the three inputs of the clock logic control circuit 2 comprise clk, en2 and clkw2, en2 represents an enable control signal for the write circuit to write reversely, clkw2 represents an input clock signal for the write circuit to write reversely, and the output of the clock logic control circuit 2 is a clock signal clk 2.
Preferably, the write circuit comprises a PMOS transistor MP11, a PMOS transistor MP12, an NMOS transistor MN11 and an NMOS transistor MN 12;
the source electrode of the PMOS tube MP11 and the source electrode of the PMOS tube MP12 are simultaneously connected with the positive electrode of the power supply;
the grid electrode of the PMOS pipe MP11 is connected with the output end of a clock signal clk1 of the clock logic control circuit No. 1;
the grid electrode of the PMOS pipe MP12 is connected with the output end of a clock signal clk2 of the clock logic control circuit No. 2;
the drain electrode of the PMOS tube MP11 is connected with the drain electrode of the NMOS tube MN11, and the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN 12;
the source electrode of the NMOS tube MN11 and the source electrode of the NMOS tube MN12 are simultaneously connected with the negative electrode of the power supply of the write-in circuit;
the gate of the NMOS transistor MN11 inputs the clock signal clk1 _; clk1_ and clk1 are complementary clocks;
the gate of the NMOS transistor MN12 inputs the clock signal clk2 _; clk2_ is complementary to clk 2.
Preferably, the difference circuit comprises a precharge sensitive amplifier PCSA No. 1, a CMOS double-rail circuit No. 1, an MTJ1, an MTJ2 and a TN 5;
the No. 1 precharge sensitive amplifier PCSA comprises a PMOS tube MP1, a PMOS tube TP1, an NMOS tube TN1, a PMOS tube MP2, a PMOS tube TP2, an NMOS tube TN2 and a charging capacitor C L1 and a charging capacitor CL2；
The grid of the PMOS tube MP1 and the grid of the PMOS tube MP2 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP1, the source electrode of the PMOS tube TP1, the source electrode of the PMOS tube TP2 and the source electrode of the PMOS tube MP2 are connected with the positive electrode of the full-subtracting device power supply;
drain electrode of PMOS transistor MP1 and charging capacitor CLThe positive electrode of 1, the drain electrode of PMOS tube TP1, the drain electrode of NMOS tube TN1, the gate electrode of NMOS tube TN2 and the gate electrode of PMOS tube TP2 are simultaneously connected to a point, and the point outputs a difference variable
Figure BDA0003171945700000031
A grid electrode of the PMOS tube TP1, a grid electrode of the NMOS tube TN1, a drain electrode of the PMOS tube TP2, a drain electrode of the NMOS tube TN2, a drain electrode of the PMOS tube MP2 and a charging capacitor CL2, the positive poles of the two electrodes are simultaneously connected with a point, and the point outputs the inverse difference Sub;
charging capacitor C L1 negative electrode, charging capacitor CL2, the negative electrode of the power supply is simultaneously connected with the negative electrode of the full-reduction device;
the No. 1 CMOS double-track circuit comprises NMOS tubes T1-T8;
the drain electrode of the NMOS tube T1 is connected with the drain electrode of the NMOS tube T2 and is simultaneously connected with the source electrode of the NMOS tube TN 1;
the drain electrode of the NMOS tube T5 is connected with the drain electrode of the NMOS tube T6 and is simultaneously connected with the source electrode of the NMOS tube TN 2;
the drain electrode of the NMOS tube T1 is simultaneously connected with the drain electrode of the NMOS tube T3, the source electrode of the NMOS tube T5 and the drain electrode of the NMOS tube T7;
the drain electrode of the NMOS tube T2 is simultaneously connected with the drain electrode of the NMOS tube T4, the source electrode of the NMOS tube T6 and the drain electrode of the NMOS tube T8;
the drain electrode of the NMOS tube T3 is connected with the source electrode of the NMOS tube T4, and is simultaneously connected with one end of the MTJ 1;
the drain electrode of the NMOS tube T7 is connected with the source electrode of the NMOS tube T8, and is simultaneously connected with one end of the MTJ 2;
the grid input signals A of the NMOS tube T1 and the NMOS tube T6 are A, and A represents a reduced number;
the grid input signals B of the NMOS tube T3 and the NMOS tube T8 represent the number of subtractions;
grid input signals of NMOS tube T2 and NMOS tube T5
Figure BDA0003171945700000032
A and
Figure BDA0003171945700000033
is a pair of complementary signals;
grid input signals of NMOS tube T4 and NMOS tube T7
Figure BDA0003171945700000034
B and
Figure BDA0003171945700000035
is a pair of complementary signals;
the other end of the MTJ1 and the other end of the MTJ2 are connected to the drain of the NMOS transistor TN5, the source of the NMOS transistor TN5 is connected to the negative electrode of the full-subtractor power supply, and the gate of the NMOS transistor TN5 is connected to the clock signal clk.
Preferably, the borrowing circuit comprises a precharge sensitive amplifier PCSA No. 2, a CMOS double-rail circuit No. 2, an MTJ3, an MTJ4 and an NMOS tube TN 6;
the No. 2 precharge sensitive amplifier PCSA comprises a PMOS tube MP3, a PMOS tube TP3, an NMOS tube TN3, a PMOS tube MP4, a PMOS tube TP4, an NMOS tube TN4 and a charging capacitor CL3 and a charging capacitor CL4；
The grid of the PMOS tube MP3 and the grid of the PMOS tube MP4 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP3, the source electrode of the PMOS tube TP3, the source electrode of the PMOS tube TP4 and the source electrode of the PMOS tube TP4 are connected with the anode of the power supply;
drain electrode of PMOS transistor MP3 and charging capacitor CL3 positive electrode, drain electrode of PMOS tube TP3, drain electrode of NMOS tube TN3, and NMOS tube TThe grid of the N4 and the grid of the PMOS tube TP4 are simultaneously connected with one point, and the output borrow inverse quantity of the point
Figure BDA0003171945700000041
A grid electrode of the PMOS tube TP3, a grid electrode of the NMOS tube TN3, a drain electrode of the PMOS tube TP4, a drain electrode of the NMOS tube TN4, a drain electrode of the PMOS tube MP4 and a charging capacitor CL4 is connected with a point at the same time, and the point outputs a borrow variable Ci+1；
CiA borrowing variable, C, from the lower bit to the current biti+1Representing a borrow variable for the current bit to the higher bit.
Charging capacitor CL3 negative electrode, charging capacitor CL4, the negative electrode of the power supply is simultaneously connected with the negative electrode of the power supply of the full-reduction device;
the No. 2 CMOS double-rail circuit comprises NMOS transistors T9-T12;
the drain electrode of the NMOS tube T9 and the drain electrode of the NMOS tube T10 are connected, and are simultaneously connected with the source electrode of the NMOS tube TN 3;
the source electrode of the NMOS tube T9 is connected with the source electrode of the NMOS tube T10 and is also connected with one end of the MTJ 3;
the drain electrode of the NMOS tube T11 and the drain electrode of the NMOS tube T12 are connected, and the drain electrode of the NMOS tube TN4 is connected;
the source electrode of the NMOS tube T11 is connected with the source electrode of the NMOS tube T12 and is connected with one end of the MTJ 4;
grid input signal of NMOS tube T9
Figure BDA0003171945700000042
The gate of the NMOS transistor T10 receives a signal B;
the gate of the NMOS transistor T11 inputs a signal A;
grid input signal of NMOS tube T12
Figure BDA0003171945700000043
The other end of the MTJ4 at the other end of the MTJ3 is connected to the drain of the NMOS transistor TN6, the source of the NMOS transistor TN6 is connected to the negative electrode of the full-subtracting device power supply, and the gate of the NMOS transistor TN6 is connected to the clock signal clk.
Preferably, the voltage of the write circuit power supply is higher than the voltage of the full-subtractor power supply.
Preferably, the forward current has a current of more than 100uA, and the reverse current has a current of less than-100 uA.
The invention has the advantages that the clock of the write-in circuit is controlled by adding the control gate, the number of MOS (metal oxide semiconductor) tubes in the clock power supply voltage direction of the write-in circuit is reduced, and the aim of reducing the write-in power consumption is fulfilled. The circuit of the invention can complete the function of a subtracter and select by setting a write enable signal: 1. the MTJ is periodically written. 2. The MTJ is written aperiodically.
Drawings
FIG. 1 is a diagram of a conventional write control circuit;
FIG. 2 is a structure diagram of an MTJ with CoFeB/mgO/CoFeB as material;
FIG. 3 is a schematic diagram of the differencing or borrowing bit of the full subtracter;
FIG. 4 is a schematic diagram of a write circuit according to the present invention;
FIG. 5 is a schematic diagram of a clock logic control circuit according to the present invention;
FIG. 6 is a schematic diagram of a 1-bit full subtractor of the present invention;
FIG. 7 is a graph of MTJ transient characteristics;
FIG. 8 is a diagram illustrating the operation timing and operation result of the full subtracter.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The full subtractor working process of the embodiment is divided into a writing mode and a calculating mode, and the two modes are switched under the control of a clock clk. In the calculation mode of this embodiment, the logic function of the full subtracter needs to be implemented:
the expressions (1) to (4) give the logical function expressions of the full subtracter, including the functions of difference and borrow bit. Wherein formula (1) is a difference variable Sub expression, and formula (2) is a difference inverse variable
Figure BDA0003171945700000051
Expression formula (3) is borrow Ci+1The variable expression, formula (4) is borrow inverse quantity
Figure BDA0003171945700000052
And (5) expressing. The corresponding circuit is divided into two parts, and the functions of difference finding and borrowing of the full subtracter are respectively realized.
Figure BDA0003171945700000053
Figure BDA0003171945700000054
Figure BDA0003171945700000055
Figure BDA0003171945700000056
Wherein C isiAnd
Figure BDA0003171945700000057
the MTJ1-MTJ4 needs to be written; to achieve the above function, the present embodiment provides a full subtractor using MTJ, including 1 bitThe circuit comprises a full subtracter, two write-in circuits and two clock logic control circuits;
the 1-bit full subtractor of the present embodiment includes a difference circuit and a borrow circuit, each of which includes two MTJs, wherein the MTJ1 and MTJ2 of the difference circuit are respectively used for storing a borrow variable C during difference calculationiBorrow inverse volume
Figure BDA0003171945700000061
The MTJ3 and MTJ4 of the borrow circuit are used to store the borrow variable C during borrow respectivelyiBorrow inverse volume
Figure BDA0003171945700000062
The schematic diagram of the structure of the MTJ device is shown in fig. 2, and the device consists of three layers, namely, an oxide insulating layer (e.g., MgO) in the middle, and two ferromagnetic layers (e.g., CoFeB). In FIG. 2, when the magnetization directions of the two ferromagnetic layers are opposite to each other, the MTJ exhibits a high resistance state, which is equivalent to a logic "0" in the memory content; when the relative magnetization directions of the electrons of the two ferromagnetic layers are the same, the MTJ assumes a low resistance state, which corresponds to a logic "0" stored therein. To achieve a "write" operation, i.e., to change the stored contents of the MTJ, the relative electronic magnetization directions of the two ferromagnetic layers need to be changed, requiring an externally supplied current. In application, it is generally considered that the magnetization direction of electrons on one side is fixed, and only the magnetization direction of electrons on the other side needs to be changed by applying current, so that the "write" operation can be realized.
The resistance states of MTJ1 and MTJ3 are the same, the resistance states of MTJ2 and MTJ4 are the same, and the resistance states of MTJ1 and MTJ2 are opposite;
when the clock is clk at a low level, the four MTJs are turned on, and writing is realized by inputting current to the MTJs;
each write circuit has two input clock signals clk1 and clk2, when clk1 is 0, a forward current is input to MTJ1 and MTJ3, a reverse current is input to MTJ2 and MTJ4, when clk2 is 0, a forward current is input to MTJ2 and MTJ4, and a reverse current is input to MTJ1 and MTJ 3; the clock signals clk1 and clk2 cannot be 0 at the same time;
the clock signal clk1 output by the No. 1 clock logic control circuit simultaneously transmits two write-in circuits, and the clock signal clk2 output by the No. 2 clock logic control circuit simultaneously transmits two write-in circuits;
the clock logic control circuits are all realized by NOR gate circuits;
as shown in fig. 5, three inputs of the clock logic control circuit No. 1 of the present embodiment include clk, en1, and clkw1, clk denotes a full-decrementer operating clock, en1 denotes an enable control signal for the write circuit to write in the forward direction, clkw1 denotes an input clock signal for the write circuit to write in the forward direction, and the output of the clock logic control circuit No. 1 is a clock signal clk 1; the three inputs of the clock logic control circuit No. 2 comprise clk, en2 and clkw2, en2 represents an enable control signal for the write circuit to write reversely, clkw2 represents an input clock signal for the write circuit to write reversely, and the output of the clock logic control circuit No. 2 is a clock signal clk 2;
in the embodiment, under the clock control of the operation, the operation is divided into two stages by combining a control circuit. In the first stage, when clk is in high level, the write circuit is in a blocking state, and the existence of the write circuit does not influence the normal operation process of the full subtracter; when clk is low, the control circuit is turned on to perform a write operation on the MTJ, and when the write clock clk1 is active, a loop indicated by a thick line is formed to provide a write current in the direction shown in the figure for the MTJ write operation; when the write clock clk2 is active, write current loop 2 is formed, providing reverse current for MTJ "write"; the write clock clk1 is controlled by clk, en1 and clkw1, and the write can be realized only when clk is 0, en1 is 0 and clkw1 is 0, and the control function is realized by a nor gate circuit; similarly, the write clock clk2 is controlled by clk, en2, and clkw 2. In designing the write timing, it is ensured that clk1 and clk2 cannot be active at the same time, i.e., that both write paths cannot be turned on at the same time. The magnitude of the write current is realized by adjusting the width-to-length ratios of MP11, MP12, MN11 and MN 12.
In a preferred embodiment, the write circuit of this embodiment is shown in fig. 4, where a PMOS transistor MP11, a PMOS transistor MP12, an NMOS transistor MN11, and an NMOS transistor MN 12; the source electrode of the PMOS tube MP11 and the source electrode of the PMOS tube MP12 are simultaneously connected with the positive electrode of the power supply; the grid electrode of the PMOS pipe MP11 is connected with the output end of a clock signal clk1 of the clock logic control circuit No. 1; the grid electrode of the PMOS pipe MP12 is connected with the output end of a clock signal clk2 of the clock logic control circuit No. 2; the drain electrode of the PMOS tube MP11 is connected with the drain electrode of the NMOS tube MN11, and the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN 12; the source electrode of the NMOS tube MN11 and the source electrode of the NMOS tube MN12 are simultaneously connected with the negative electrode of the power supply of the write-in circuit; the gate of the NMOS transistor MN11 inputs the clock signal clk1 _; clk1_ and clk1 are complementary clocks; the gate of the NMOS transistor MN12 inputs the clock signal clk2 _; clk2_ is complementary to clk 2.
In fig. 4, complementary control clocks are applied to the gates of MP11 and MN12, so that MP12 and MN11 are turned on to form a write current path 1: MP11 → MTJ1 → MTJ2 → MN 12; when complementary control clocks are applied to the gates of the MP12 and the MN11, another current path 2 is formed: MP12 → MTJ2 → MTJ1 → MN 11. In practical applications, the channel 1 and the channel 2 cannot be opened simultaneously, and the opening and closing time of the two channels needs to be controlled according to the requirement of the MTJ "writing" timing.
In this embodiment, the 1-bit full subtractor includes a difference circuit and a borrow circuit, and as shown in fig. 3, the difference or borrow circuit includes a Pre-Charge Sense Amplifier (PCSA), a CMOS dual-rail circuit, and an MTJ. Wherein the PCSA is operative to read out the memory contents of the MTJ device.
As shown in fig. 6, the difference circuit of the present embodiment includes a precharge sensitive amplifier PCSA No. 1, a CMOS dual-rail circuit No. 1, an MTJ1, an MTJ2, and a TN 5; the No. 1 precharge sensitive amplifier PCSA comprises a PMOS tube MP1, a PMOS tube TP1, an NMOS tube TN1, a PMOS tube MP2, a PMOS tube TP2, an NMOS tube TN2 and a charging capacitor CL1 and a charging capacitor CL2; the grid of the PMOS tube MP1 and the grid of the PMOS tube MP2 are simultaneously connected with a clock signal clk; the source electrode of the PMOS tube MP1, the source electrode of the PMOS tube TP1, the source electrode of the PMOS tube TP2 and the source electrode of the PMOS tube MP2 are connected with the positive electrode of the full-subtracting device power supply; drain electrode of PMOS transistor MP1 and charging capacitor CLThe positive electrode of 1, the drain electrode of PMOS tube TP1, the drain electrode of NMOS tube TN1, the gate electrode of NMOS tube TN2 and the gate electrode of PMOS tube TP2 are simultaneously connected to a point, and the point outputs a difference variable
Figure BDA0003171945700000071
A grid electrode of the PMOS tube TP1, a grid electrode of the NMOS tube TN1, a drain electrode of the PMOS tube TP2, a drain electrode of the NMOS tube TN2, a drain electrode of the PMOS tube MP2 and a charging capacitor CL2, the positive poles of the two electrodes are simultaneously connected with a point, and the point outputs the inverse difference Sub; charging capacitor CL1 negative electrode, charging capacitor CL2, the negative electrode of the power supply is simultaneously connected with the negative electrode of the full-reduction device; the No. 1 CMOS double-track circuit comprises NMOS tubes T1-T8; the drain electrode of the NMOS tube T1 is connected with the drain electrode of the NMOS tube T2 and is simultaneously connected with the source electrode of the NMOS tube TN 1; the drain electrode of the NMOS tube T5 is connected with the drain electrode of the NMOS tube T6 and is simultaneously connected with the source electrode of the NMOS tube TN 2; the drain electrode of the NMOS tube T1 is simultaneously connected with the drain electrode of the NMOS tube T3, the source electrode of the NMOS tube T5 and the drain electrode of the NMOS tube T7; the drain electrode of the NMOS tube T2 is simultaneously connected with the drain electrode of the NMOS tube T4, the source electrode of the NMOS tube T6 and the drain electrode of the NMOS tube T8; the drain electrode of the NMOS tube T3 is connected with the source electrode of the NMOS tube T4, and is simultaneously connected with one end of the MTJ 1; the drain electrode of the NMOS tube T7 is connected with the source electrode of the NMOS tube T8, and is simultaneously connected with one end of the MTJ 2; the grid input signals A of the NMOS tube T1 and the NMOS tube T6 are A, and A represents a reduced number; the grid input signals B of the NMOS tube T3 and the NMOS tube T8 represent the number of subtractions; grid input signals of NMOS tube T2 and NMOS tube T5
Figure BDA0003171945700000081
Grid input signals of NMOS tube T4 and NMOS tube T7
Figure BDA0003171945700000084
The other end of the MTJ1 and the other end of the MTJ2 are connected to the drain of the NMOS transistor TN5, and the source of the NMOS transistor TN5 is connected to the negative electrode of the full-reduction unit power supply.
As shown in fig. 6, the borrowing bit circuit of the present embodiment includes a precharge sensitive amplifier PCSA No. 2, a CMOS dual-rail circuit No. 2, an MTJ3, an MTJ4, and an NMOS transistor TN 6; the No. 2 precharge sensitive amplifier PCSA comprises a PMOS tube MP3, a PMOS tube TP3, an NMOS tube TN3, a PMOS tube MP4, a PMOS tube TP4, an NMOS tube TN4 and a charging capacitor CL3 and a charging capacitor CL4; the grid of the PMOS tube MP3 and the grid of the PMOS tube MP4 are simultaneously connected with a clock signal clk; the source electrode of the PMOS transistor MP3, the source electrode of the PMOS transistor TP3, the source electrode of the PMOS transistor TP4 and the PMOS transistorThe source electrode of the TP4 is connected with the anode of the power supply; drain electrode of PMOS transistor MP3 and charging capacitor CLThe positive electrode of the transistor 3, the drain electrode of the PMOS transistor TP3, the drain electrode of the NMOS transistor TN3, the gate electrode of the NMOS transistor TN4 and the gate electrode of the PMOS transistor TP4 are simultaneously connected to a point, and the output borrow inverse amount of the point
Figure BDA0003171945700000083
A grid electrode of the PMOS tube TP3, a grid electrode of the NMOS tube TN3, a drain electrode of the PMOS tube TP4, a drain electrode of the NMOS tube TN4, a drain electrode of the PMOS tube MP4 and a charging capacitor CL4 is connected with a point at the same time, and the point outputs a borrow variable Ci+1；CiA borrowing variable, C, from the lower bit to the current biti+1Representing a borrow variable for the current bit to the higher bit. Charging capacitor CL3 negative electrode, charging capacitor CL4, the negative electrode of the power supply is simultaneously connected with the negative electrode of the power supply of the full-reduction device; the No. 2 CMOS double-rail circuit comprises NMOS transistors T9-T12; the drain electrode of the NMOS tube T9 and the drain electrode of the NMOS tube T10 are connected, and are simultaneously connected with the source electrode of the NMOS tube TN 3; the source electrode of the NMOS tube T9 is connected with the source electrode of the NMOS tube T10 and is also connected with one end of the MTJ 3; the drain electrode of the NMOS tube T11 and the drain electrode of the NMOS tube T12 are connected, and the drain electrode of the NMOS tube TN4 is connected; the source electrode of the NMOS tube T11 is connected with the source electrode of the NMOS tube T12 and is connected with one end of the MTJ 4; grid input signal of NMOS tube T9
Figure BDA0003171945700000091
The gate of the NMOS transistor T10 receives a signal B; the gate of the NMOS transistor T11 inputs a signal A; grid input signal of NMOS tube T12
Figure BDA0003171945700000092
The other end of the MTJ4 of the MTJ3 is connected to the drain of the NMOS transistor TN6, and the source of the NMOS transistor TN6 is connected to the negative electrode of the full-reduction power supply.
The precharge sense amplifier PCSA of the present embodiment has advantages of high readout accuracy, high readout speed, low power consumption, and the like, as shown by the dotted line portion.
The voltage of the write circuit power supply is higher than the voltage of the full-subtractor power supply. In this embodiment, the negative electrode of the write circuit power supply and the negative electrode of the full-subtractor power supply are separated from each other, thereby preventing crosstalk.
In a preferred embodiment, equation (5) gives the switching current I of the magnetic tunnel junctioncoOnly when the write current I iswrite>IcoOnly then can the MTJ be "written". In the formula (1), IcoThe magnetic damping coefficient alpha, the gyromagnetic ratio gamma, the electronic electricity e and the free layer magnetization mu0MSAnisotropy field HKThe free layer volume V is determined jointly. Fig. 7 shows a transient characteristic diagram of a MTJ device model used in this embodiment mode. As can be seen from fig. 7, when a voltage is applied across the MTJ, after a certain time delay, the state of the MTJ changes from "0" to "1", and the current is about 100uA in this embodiment; continuing to apply a reverse voltage to the MTJ, after a certain time, the MTJ state changes from "1" back to "0" at a current of about-100 uA. Therefore, to change the state of the MTJ, i.e., to "write" to the MTJ, a bi-directional current of about 100uA or more needs to be externally supplied.
Figure BDA0003171945700000093
Assuming that the input signal a is equal to 0 and B is equal to 0, the contents of the memories in MTJ1 and MTJ3 are logic "memory", i.e., CiThe memory contents in MTJ2 and MTJ4 corresponding to 0 are "memory",
Figure BDA0003171945700000094
in the write mode, Sub,
Figure BDA0003171945700000095
Ci+1、
Figure BDA0003171945700000096
The terminal is pulled to high level; in the calculation mode, clk is high, TN5 is on, and in track 2: T2-T4-MTJ1-TN5 and 3: a conductive path is formed in T5-T7-MTJ2-TN 5. But because the storage in MTJ2 is "storage", MTJ2 exhibits low resistance state, so the current in track 3 is large, and Sub-end reaches low level first and then later
Figure BDA0003171945700000097
The terminal goes high. At this time, Sub is equal to 0, and the difference function is realized; at the same time, TN6 turned on, at track 5T9-MTJ3-TN6 and track 8: the conductive path is formed in T12-MTJ4-TN6, because the memory content in MTJ4 is "memory", and at this time MTJ4 exhibits a low resistance state, the current of rail 8 is large, and C isi+1The terminal reaches low level first and then later
Figure BDA0003171945700000098
Reaches a high level, at which time Ci+1When the value is 0, the borrowing function is realized.
When the input signal A, B, and the content (C) stored in the MTJ devicei) For other combinations of sampling values, the outputs Sub and C are obtained according to the same working principlei+1The value of (d) is in accordance with the truth table of the full subtracter. The truth table for the 1-bit full subtracter is given in table 1.
Table 11 bit full subtracter truth table
Figure BDA0003171945700000101
Verification was performed using the full subtracter of the present embodiment.
A, B, C are set according to the full subtractor truth tableiFigure 8 shows a verification waveform. As can be seen from the simulation result, in the "write" mode, when clk1 is equal to 0, "write" is performed on the MTJ, and the stored content in MTJ1 changes from "0" to "1" (C)i) At the same time, the memory content in MTJ2 changes from "1" to "0"
Figure BDA0003171945700000102
When clk2 is equal to 0, the memory content in MTJ1 changes from "1" to "0", and the memory content in MTJ2 changes from "0" to "1".
In the "calculation mode", when a is 0, B is 0, CiWhen 0, Sub 0, C i+10; when A is 1, B is 0, CiWhen 0, Sub 1, C i+10; when A is 0, B is 1, CiWhen 0, Sub 1, C i+11 is ═ 1; when A is 1, B is 1, CiWhen 0, Sub 0, C i+10; when A is 0, B is 0, CiWhen 1, Sub 1, C i+11 is ═ 1; when A is 1, B is 0, CiWhen 1, Sub is 0, C i+10; when A is 0, B is 1, CiWhen 1, Sub is 0, C i+11 is ═ 1; when A is 1, B is 1, CiWhen 1, Sub 1, C i+11 is ═ 1; it can be seen that the simulation results are consistent with the functions described in the truth table.
As can be seen from the simulation results, the write circuit designed in this embodiment can control the full-subtractor to switch between the write mode and the calculation mode according to the system timing, and simultaneously perform correct and reliable write to the MTJ without affecting the normal function of the full-subtractor.
The present embodiment provides a control circuit capable of switching a full subtractor between a write mode and a read mode. In a write mode, reliably writing to the MTJ; in the calculation mode, the input signal is calculated to realize the function of a full reducer. Fig. 8 shows a timing diagram and an operation result diagram of the full subtractor designed in this embodiment, and it can be seen that the addition of the write circuit can control the full subtractor to normally switch between the write mode and the calculation mode, thereby implementing the normal logic function of the subtractor. Meanwhile, the MTJ is applied, and compared with a common memory device, the system power consumption can be greatly saved.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims (6)

1. A full-subtractor using MTJ comprises a 1-bit full-subtractor, two write circuits, and two clock logic control circuits;
the 1-bit full subtracter comprises a difference circuit and a borrow bit circuit, wherein the difference circuit and the borrow bit circuit respectively comprise two MTJs, and the MTJ1 and the MTJ2 of the difference circuit are respectively used for storing a borrow variable C during difference calculationiBorrow inverse volume
Figure FDA0003171945690000011
The MTJ3 and MTJ4 of the borrow circuit are used to store the borrow variable C during borrow respectivelyiBorrow inverse volume
Figure FDA0003171945690000012
MTJ1 has the same resistance state as MTJ3, MTJ2 has the same resistance state as MTJ4, and MTJ1 has the opposite resistance state as MTJ 2;
each write circuit has two input clock signals clk1 and clk2, when clk1 is 0, a forward current is input to MTJ1 and MTJ3, a reverse current is input to MTJ2 and MTJ4, when clk2 is 0, a forward current is input to MTJ2 and MTJ4, and a reverse current is input to MTJ1 and MTJ 3; the clock signals clk1 and clk2 cannot be 0 at the same time;
the clock signal clk1 output by the No. 1 clock logic control circuit simultaneously transmits two write-in circuits, and the clock signal clk2 output by the No. 2 clock logic control circuit simultaneously transmits two write-in circuits;
the clock logic control circuits are all realized by NOR gate circuits;
the three inputs of the clock logic control circuit No. 1 comprise clk, en1 and clkw1, wherein clk represents a full-subtracting device working clock, en1 represents an enabling control signal for the forward writing of the writing circuit, clkw1 represents an input clock signal for the forward writing of the writing circuit, and the output of the clock logic control circuit No. 1 is a clock signal clk 1; the three inputs of the clock logic control circuit 2 comprise clk, en2 and clkw2, en2 represents an enable control signal for the write circuit to write reversely, clkw2 represents an input clock signal for the write circuit to write reversely, and the output of the clock logic control circuit 2 is a clock signal clk 2.
2. The full subtractor using MTJ of claim 1, wherein the write circuit comprises a PMOS transistor MP11, a PMOS transistor MP12, an NMOS transistor MN11, and an NMOS transistor MN 12;
the source electrode of the PMOS tube MP11 and the source electrode of the PMOS tube MP12 are simultaneously connected with the positive electrode of the power supply;
the grid electrode of the PMOS pipe MP11 is connected with the output end of a clock signal clk1 of the clock logic control circuit No. 1;
the grid electrode of the PMOS pipe MP12 is connected with the output end of a clock signal clk2 of the clock logic control circuit No. 2;
the drain electrode of the PMOS tube MP11 is connected with the drain electrode of the NMOS tube MN11, and the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN 12;
the source electrode of the NMOS tube MN11 and the source electrode of the NMOS tube MN12 are simultaneously connected with the negative electrode of the power supply of the write-in circuit;
the gate of the NMOS transistor MN11 inputs the clock signal clk1 _; clk1_ and clk1 are complementary clocks;
the gate of the NMOS transistor MN12 inputs the clock signal clk2 _; clk2_ is complementary to clk 2.
3. The MTJ-applied full subtractor of claim 2 wherein the differencing circuit comprises a precharge-sensitive amplifier PCSA # 1, a CMOS dual-rail circuit # 1, MTJ1, MTJ2, and TN 5;
the No. 1 precharge sensitive amplifier PCSA comprises a PMOS tube MP1, a PMOS tube TP1, an NMOS tube TN1, a PMOS tube MP2, a PMOS tube TP2, an NMOS tube TN2 and a charging capacitor CL1 and a charging capacitor CL2；
The grid of the PMOS tube MP1 and the grid of the PMOS tube MP2 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP1, the source electrode of the PMOS tube TP1, the source electrode of the PMOS tube TP2 and the source electrode of the PMOS tube MP2 are connected with the positive electrode of the full-subtracting device power supply;
drain electrode of PMOS transistor MP1 and charging capacitor CLThe positive electrode of 1, the drain electrode of PMOS tube TP1, the drain electrode of NMOS tube TN1, the gate electrode of NMOS tube TN2 and the gate electrode of PMOS tube TP2 are simultaneously connected to a point, and the point outputs a difference variable
Figure FDA0003171945690000021
A grid electrode of the PMOS tube TP1, a grid electrode of the NMOS tube TN1, a drain electrode of the PMOS tube TP2, a drain electrode of the NMOS tube TN2, a drain electrode of the PMOS tube MP2 and a charging capacitor CL2, the positive poles of the two electrodes are simultaneously connected with a point, and the point outputs the inverse difference Sub;
charging capacitor CL1 negative electrode, charging capacitor CL2, the negative electrode of the power supply is simultaneously connected with the negative electrode of the full-reduction device;
the No. 1 CMOS double-track circuit comprises NMOS tubes T1-T8;
the drain electrode of the NMOS tube T1 is connected with the drain electrode of the NMOS tube T2 and is simultaneously connected with the source electrode of the NMOS tube TN 1;
the drain electrode of the NMOS tube T5 is connected with the drain electrode of the NMOS tube T6 and is simultaneously connected with the source electrode of the NMOS tube TN 2;
the drain electrode of the NMOS tube T1 is simultaneously connected with the drain electrode of the NMOS tube T3, the source electrode of the NMOS tube T5 and the drain electrode of the NMOS tube T7;
the drain electrode of the NMOS tube T2 is simultaneously connected with the drain electrode of the NMOS tube T4, the source electrode of the NMOS tube T6 and the drain electrode of the NMOS tube T8;
the drain electrode of the NMOS tube T3 is connected with the source electrode of the NMOS tube T4, and is simultaneously connected with one end of the MTJ 1;
the drain electrode of the NMOS tube T7 is connected with the source electrode of the NMOS tube T8, and is simultaneously connected with one end of the MTJ 2;
the grid input signals A of the NMOS tube T1 and the NMOS tube T6 are A, and A represents a reduced number;
the grid input signals B of the NMOS tube T3 and the NMOS tube T8 represent the number of subtractions;
grid input signals of NMOS tube T2 and NMOS tube T5
Figure FDA0003171945690000022
Grid input signals of NMOS tube T4 and NMOS tube T7
Figure FDA0003171945690000023
A and
Figure FDA0003171945690000024
is a pair of complementary signals;
b and
Figure FDA0003171945690000025
is a pair of complementary signals;
the other end of the MTJ1 and the other end of the MTJ2 are connected to the drain of the NMOS transistor TN5, the source of the NMOS transistor TN5 is connected to the negative electrode of the full-subtractor power supply, and the gate of the NMOS transistor TN5 is connected to the clock signal clk.
4. The MTJ-applied full subtractor according to claim 3, wherein the borrowing circuit comprises a precharge-sensitive amplifier PCSA No. 2, a CMOS dual-rail circuit No. 2, MTJ3, MTJ4 and NMOS transistor TN 6;
the No. 2 precharge sensitive amplifier PCSA comprises a PMOS tube MP3, a PMOS tube TP3, an NMOS tube TN3, a PMOS tube MP4, a PMOS tube TP4, an NMOS tube TN4 and a charging capacitor CL3 and a charging capacitor CL4；
The grid of the PMOS tube MP3 and the grid of the PMOS tube MP4 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP3, the source electrode of the PMOS tube TP3, the source electrode of the PMOS tube TP4 and the source electrode of the PMOS tube TP4 are connected with the anode of the power supply;
drain electrode of PMOS transistor MP3 and charging capacitor CLThe positive electrode of the transistor 3, the drain electrode of the PMOS transistor TP3, the drain electrode of the NMOS transistor TN3, the gate electrode of the NMOS transistor TN4 and the gate electrode of the PMOS transistor TP4 are simultaneously connected to a point, and the output borrow inverse amount of the point
Figure FDA0003171945690000031
A grid electrode of the PMOS tube TP3, a grid electrode of the NMOS tube TN3, a drain electrode of the PMOS tube TP4, a drain electrode of the NMOS tube TN4, a drain electrode of the PMOS tube MP4 and a charging capacitor CL4 is connected with a point at the same time, and the point outputs a borrow variable Ci+1；
CiA borrowing variable, C, from the lower bit to the current biti+1A borrow variable representing the current bit to the high bit;
charging capacitor CL3 negative electrode, charging capacitor CL4, the negative electrode of the power supply is simultaneously connected with the negative electrode of the power supply of the full-reduction device;
the No. 2 CMOS double-rail circuit comprises NMOS transistors T9-T12;
the drain electrode of the NMOS tube T9 and the drain electrode of the NMOS tube T10 are connected, and are simultaneously connected with the source electrode of the NMOS tube TN 3;
the source electrode of the NMOS tube T9 is connected with the source electrode of the NMOS tube T10 and is also connected with one end of the MTJ 3;
the drain electrode of the NMOS tube T11 and the drain electrode of the NMOS tube T12 are connected, and the drain electrode of the NMOS tube TN4 is connected;
the source electrode of the NMOS tube T11 is connected with the source electrode of the NMOS tube T12 and is connected with one end of the MTJ 4;
grid input signal of NMOS tube T9
Figure FDA0003171945690000032
The gate of the NMOS transistor T10 receives a signal B;
the gate of the NMOS transistor T11 inputs a signal A;
grid input signal of NMOS tube T12
Figure FDA0003171945690000033
The other end of the MTJ4 at the other end of the MTJ3 is connected to the drain of the NMOS transistor TN6, the source of the NMOS transistor TN6 is connected to the negative electrode of the full-subtracting device power supply, and the gate of the NMOS transistor TN6 is connected to the clock signal clk.
5. The full reducer using MTJ of claim 3, wherein a voltage of a write circuit power supply is higher than a voltage of a full reducer power supply.
6. The full-subtractor using an MTJ of claim 3, wherein the current of the forward current is greater than 100uA and the current of the reverse current is less than-100 uA.
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CN112564899A (en) * 2020-12-07 2021-03-26 哈尔滨工业大学（威海） Double-track MTJ (magnetic tunnel junction) and CMOS (complementary metal oxide semiconductor) mixed lookup table circuit

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