CN113470715B - Full-subtracting device applying MTJ (magnetic tunnel junction) - Google Patents

Full-subtracting device applying MTJ (magnetic tunnel junction) Download PDF

Info

Publication number
CN113470715B
CN113470715B CN202110821028.1A CN202110821028A CN113470715B CN 113470715 B CN113470715 B CN 113470715B CN 202110821028 A CN202110821028 A CN 202110821028A CN 113470715 B CN113470715 B CN 113470715B
Authority
CN
China
Prior art keywords
nmos tube
electrode
tube
pmos
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110821028.1A
Other languages
Chinese (zh)
Other versions
CN113470715A (en
Inventor
王晨旭
宫月红
罗敏
王新胜
常亮
蔡济济
石薇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Jiaotong University
Innovation Academy for Microsatellites of CAS
Harbin Institute of Technology Weihai
Original Assignee
Shandong Jiaotong University
Innovation Academy for Microsatellites of CAS
Harbin Institute of Technology Weihai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong Jiaotong University, Innovation Academy for Microsatellites of CAS, Harbin Institute of Technology Weihai filed Critical Shandong Jiaotong University
Priority to CN202110821028.1A priority Critical patent/CN113470715B/en
Publication of CN113470715A publication Critical patent/CN113470715A/en
Application granted granted Critical
Publication of CN113470715B publication Critical patent/CN113470715B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)

Abstract

A full-reduction device applying MTJ solves the problem that write-in power consumption is increased due to the mode of increasing MOS tubes in the direction of power supply voltage when the MTJ of the full-reduction device is written at any time in the prior art, and belongs to the technical field of electronic circuits. The invention relates to a full-subtracting device applying MTJ, which comprises a 1-bit full-subtracting device, two write-in circuits and two clock logic control circuits; the clock signals output by the two clock logic control circuits simultaneously send two write-in circuits; the clock logic control circuits are all realized by NOR gate circuits; the three inputs of the clock logic control circuit comprise a full-subtracter working clock, a positive/negative writing enabling control signal and a positive/negative writing input clock signal. The invention controls the clock of the write-in circuit by adding the control gate, reduces the number of MOS tubes in the clock power supply voltage direction of the write-in circuit, and achieves the purpose of reducing the write-in power consumption.

Description

Full-subtracting device applying MTJ (magnetic tunnel junction)
Technical Field
The invention relates to a full-reduction device, in particular to a full-reduction device applying MTJ (magnetic tunnel junction), belonging to the technical field of electronic circuits.
Background
Further development of mobile communication technology puts higher requirements on the performance and power consumption of the analog-to-digital conversion circuit of the signal receiving end. In order to improve the performance of Analog to Digital converters (ADCs), the application of new memory devices in Digital correction circuits is a promising design direction. Memory development also encounters bottlenecks as integrated circuit fabrication technology evolves further. Currently, the conventional memory has the problems of high power consumption, limited access speed, low storage density, easy loss in storage and the like. Spin transfer torque Magnetic random access memory (STT-MRAM) based on Magnetic Tunnel Junction (MTJ) has the advantages of low power consumption, high speed, high storage density, nonvolatility, easy 3d integration and the like, and has wide application prospect, thereby becoming a new memory research direction. The STT-MRAM is applied to the analog-to-digital conversion circuit, so that the energy efficiency of the analog-to-digital converter can be further improved, and the STT-MRAM has very important significance for the development of mobile communication technology and the development of the whole information industry.
Currently, there have been some corresponding research results on the performance of MTJ devices and applications of MTJs, such as studying the magnetic sensitivity and spin injection characteristics of MgO-based magnetic tunnel junctions, applying MTJs as memory devices in Look-Up tables (LUTs), and applying full reducers of MTJ memory devices.
Some functional circuits applying the MTJ can only write the MTJ once, and some functional circuits can write the MTJ periodically by setting regular clocks (clk 1 and clk 2), so that the functional circuits cannot ensure that the functional circuits have two functions of writing at any time and periodically writing. If writing is needed at any time, a control MOS tube is generally added in the direction of the power supply voltage of the writing circuit, and the grid electrode of the MOS tube is connected with a writing enable signal EN, as shown in fig. 1, the number of the MOS tubes in the direction of the writing power supply is increased, so that the power supply voltage required for maintaining conduction is increased, and the MTJ writing power consumption is increased.
Disclosure of Invention
Aiming at the problem that the write-in power consumption is increased due to the mode of adding an MOS tube in the direction of power voltage when the MTJ of the full reducer is written at any time, the invention provides the full reducer applying the MTJ, which saves the power consumption.
The invention relates to a full-subtracting device applying MTJ, which comprises a 1-bit full-subtracting device, two write-in circuits and two clock logic control circuits;
the 1-bit full subtracter comprises a difference circuit and a borrow circuit, wherein the difference circuit and the borrow circuit respectively comprise two MTJs, and the MTJ1 and the MTJ2 of the difference circuit are respectively used for storing a borrow variable C during difference calculation i Borrow inverse volume
Figure GDA0003884535840000022
The MTJ3 and MTJ4 of the borrow circuit are used for storing the borrow variable C during borrow respectively i Borrow inverse volume
Figure GDA0003884535840000021
The resistance states of the MTJ1 and the MTJ3 are the same, the resistance states of the MTJ2 and the MTJ4 are the same, and the resistance states of the MTJ1 and the MTJ2 are opposite;
each writing circuit has two input clock signals clk1 and clk2, when clk1 is 0, forward current is input to MTJ1 and MTJ3, reverse current is input to MTJ2 and MTJ4, when clk2 is 0, forward current is input to MTJ2 and MTJ4, and reverse current is input to MTJ1 and MTJ 3; the clock signals clk1 and clk2 cannot be 0 at the same time;
a clock signal clk1 output by the No. 1 clock logic control circuit simultaneously sends two write-in circuits, and a clock signal clk2 output by the No. 2 clock logic control circuit simultaneously sends two write-in circuits;
the clock logic control circuits are all realized by NOR gate circuits;
the three inputs of the clock logic control circuit No. 1 comprise clk, en1 and clkw1, wherein clk represents a full-subtracting device working clock, en1 represents an enabling control signal written by a writing circuit in the forward direction, clkw1 represents an input clock signal written by the writing circuit in the forward direction, and the output of the clock logic control circuit No. 1 is a clock signal clk1; the three inputs of the clock logic control circuit No. 2 comprise clk, en2 and clkw2, en2 represents an enable control signal written reversely by the writing circuit, clkw2 represents an input clock signal written reversely by the writing circuit, and the output of the clock logic control circuit No. 2 is a clock signal clk2.
Preferably, the write circuit comprises a PMOS tube MP11, a PMOS tube MP12, an NMOS tube MN11 and an NMOS tube MN12;
the source electrode of the PMOS tube MP11 and the source electrode of the PMOS tube MP12 are simultaneously connected with the positive electrode of the power supply;
the grid electrode of the PMOS pipe MP11 is connected with the output end of a clock signal clk1 of the clock logic control circuit No. 1;
the grid electrode of the PMOS pipe MP12 is connected with the output end of a clock signal clk2 of the clock logic control circuit No. 2;
the drain electrode of the PMOS tube MP11 is connected with the drain electrode of the NMOS tube MN11, and the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN12;
the source electrode of the NMOS tube MN11 and the source electrode of the NMOS tube MN12 are simultaneously connected with the negative electrode of the power supply of the write-in circuit;
the gate of the NMOS transistor MN12 inputs the clock signal clk1_; clk1_ and clk1 are complementary clocks;
the gate of the NMOS transistor MN11 inputs the clock signal clk2_; clk2_ and clk2 are complementary clocks.
Preferably, the difference circuit comprises a No. 1 precharge sensitive amplifier PCSA, a No. 1 CMOS double-track circuit, an MTJ1, an MTJ2 and an NMOS tube TN5;
the No. 1 precharging sensitive amplifier PCSA comprises a PMOS tube MP1, a PMOS tube TP1, an NMOS tube TN1, a PMOS tube MP2, a PMOS tube TP2, an NMOS tube TN2 and a charging capacitor C L 1 and a charging capacitor C L 2；
The grid electrode of the PMOS tube MP1 and the grid electrode of the PMOS tube MP2 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP1, the source electrode of the PMOS tube TP2 and the source electrode of the PMOS tube MP2 are connected with the positive electrode of the full-reduction unit power supply;
drain electrode and charging capacitor C of PMOS transistor MP1 L The positive electrode of the transistor 1, the drain electrode of the PMOS transistor TP1, the drain electrode of the NMOS transistor TN1, the grid electrode of the NMOS transistor TN2 and the grid electrode of the PMOS transistor TP2 are simultaneously connected with one point, and the inverse quantity of the output difference of the point is
Figure GDA0003884535840000031
A grid electrode of the PMOS tube TP1, a grid electrode of the NMOS tube TN1, a drain electrode of the PMOS tube TP2, a drain electrode of the NMOS tube TN2, a drain electrode of the PMOS tube MP2 and a charging capacitor C L 2, the positive poles of the two electrodes are simultaneously connected with a point which outputs a difference variable Sub;
charging capacitor C L 1 negative electrode, charging capacitor C L 2, the negative electrode of the power supply is simultaneously connected with the negative electrode of the full-reduction device;
the No. 1 CMOS double-track circuit comprises NMOS tubes T1 to T8;
the drain electrode of the NMOS tube T1 is connected with the drain electrode of the NMOS tube T2, and is simultaneously connected with the source electrode of the NMOS tube TN 1;
the drain electrode of the NMOS tube T5 is connected with the drain electrode of the NMOS tube T6, and is simultaneously connected with the source electrode of the NMOS tube TN 2;
the source electrode of the NMOS tube T1 is simultaneously connected with the drain electrode of the NMOS tube T3, the source electrode of the NMOS tube T5 and the drain electrode of the NMOS tube T7;
the source electrode of the NMOS tube T2 is simultaneously connected with the drain electrode of the NMOS tube T4, the source electrode of the NMOS tube T6 and the drain electrode of the NMOS tube T8;
the source electrode of the NMOS tube T3 is connected with the source electrode of the NMOS tube T4 and is simultaneously connected with one end of the MTJ 1;
the source electrode of the NMOS tube T7 is connected with the source electrode of the NMOS tube T8 and is simultaneously connected with one end of the MTJ 2;
the grid input signals A of the NMOS tube T1 and the NMOS tube T6 represent the number of the subtractions;
the grid input signals B of the NMOS tube T3 and the NMOS tube T8 represent the number of subtractions;
grid input signals of NMOS (N-channel metal oxide semiconductor) tube T2 and NMOS tube T5
Figure GDA0003884535840000032
A and
Figure GDA0003884535840000033
is a pair of complementary signals;
grid input signals of NMOS tube T4 and NMOS tube T7
Figure GDA0003884535840000034
B and
Figure GDA0003884535840000035
is a pair of complementary signals;
the other end of the MTJ1 and the other end of the MTJ2 are connected with the drain electrode of the NMOS tube TN5, the source electrode of the NMOS tube TN5 is connected with the negative electrode of the full-reduction unit power supply, and the gate electrode of the NMOS tube TN5 is connected with the clock signal clk.
Preferably, the borrowing circuit comprises a No. 2 precharge sensitive amplifier PCSA, a No. 2 CMOS double-track circuit, an MTJ3, an MTJ4 and an NMOS tube TN6;
the No. 2 precharging sensitive amplifier PCSA comprises a PMOS tube MP3, a PMOS tube TP3, an NMOS tube TN3, a PMOS tube MP4, a PMOS tube TP4, an NMOS tube TN4 and a charging capacitor C L 3 and a charging capacitor C L 4；
The grid electrode of the PMOS pipe MP3 and the grid electrode of the PMOS pipe MP4 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP3, the source electrode of the PMOS tube TP4 and the source electrode of the PMOS tube MP4 are connected with the anode of the power supply;
drain electrode of PMOS transistor MP3 and charging capacitor C L The positive electrode of the transistor 3, the drain electrode of the PMOS transistor TP3, the drain electrode of the NMOS transistor TN3, the grid electrode of the NMOS transistor TN4 and the grid electrode of the PMOS transistor TP4 are simultaneously connected with one point, and the output borrow inverse quantity of the point
Figure GDA0003884535840000041
A grid electrode of the PMOS tube TP3, a grid electrode of the NMOS tube TN3, a drain electrode of the PMOS tube TP4, a drain electrode of the NMOS tube TN4, a drain electrode of the PMOS tube MP4 and a charging capacitor C L 4 is connected with a point at the same time, and the point outputs a borrow variable C i+1 ；
C i A borrowing variable, C, from the lower bit to the current bit i+1 Representing a borrow variable for the current bit to the higher bit.
Charging capacitor C L 3 negative electrode, charging capacitor C L 4, the negative electrode of the power supply is simultaneously connected with the negative electrode of the power supply of the full-reduction device;
the No. 2 CMOS double-track circuit comprises NMOS tubes T9 to T12;
the drain electrode of the NMOS tube T9 and the drain electrode of the NMOS tube T10 are connected and simultaneously connected with the source electrode of the NMOS tube TN 3;
the source electrode of the NMOS tube T9 is connected with the source electrode of the NMOS tube T10 and is simultaneously connected with one end of the MTJ 3;
the drain electrode of the NMOS tube T11 and the drain electrode of the NMOS tube T12 are connected, and are connected with the source electrode of the NMOS tube TN 4;
the source electrode of the NMOS tube T11 is connected with the source electrode of the NMOS tube T12 and is connected with one end of the MTJ 4;
grid input signal of NMOS tube T9
Figure GDA0003884535840000042
A grid electrode of the NMOS tube T10 inputs a signal B;
a grid electrode input signal A of an NMOS tube T11;
grid input signal of NMOS tube T12
Figure GDA0003884535840000043
The other end of the MTJ4 at the other end of the MTJ3 is connected with the drain electrode of the NMOS tube TN6, the source electrode of the NMOS tube TN6 is connected with the negative electrode of the full-subtracting device power supply, and the grid electrode of the NMOS tube TN6 is connected with a clock signal clk.
Preferably, the voltage of the write circuit power supply is higher than the voltage of the full-subtractor power supply.
Preferably, the forward current has a current of more than 100uA, and the reverse current has a current of less than-100 uA.
The invention has the advantages that the clock of the write-in circuit is controlled by adding the control gate, the number of MOS (metal oxide semiconductor) tubes in the clock power supply voltage direction of the write-in circuit is reduced, and the aim of reducing the write-in power consumption is fulfilled. The circuit of the invention can complete the function of a subtracter and select by setting a write enable signal: 1. the MTJ is periodically written. 2. The MTJ is written aperiodically.
Drawings
FIG. 1 is a schematic diagram of a conventional write control circuit;
FIG. 2 is a structure diagram of an MTJ with CoFeB/mgO/CoFeB as material;
FIG. 3 is a schematic diagram of the differencing or borrowing bit of the full subtracter;
FIG. 4 is a schematic diagram of a write circuit according to the present invention;
FIG. 5 is a schematic diagram of a clock logic control circuit according to the present invention;
FIG. 6 is a schematic diagram of a 1-bit full subtractor of the present invention;
FIG. 7 is a graph of MTJ transients;
FIG. 8 is a diagram illustrating the operation timing and operation result of the full subtracter.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The full subtractor working process of the embodiment is divided into a writing mode and a calculating mode, and the two modes are switched under the control of a clock clk. In the calculation mode of this embodiment, the logic function of the full subtracter needs to be implemented:
the expressions (1) to (4) give the logical function expressions of the full subtracter, including the functions of difference and borrow bit. Wherein formula (1) is a difference variable Sub expression, and formula (2) is a difference inverse variable
Figure GDA0003884535840000051
Expression formula (3) is borrow C i+1 The variable expression, formula (4) is borrow inverse quantity
Figure GDA0003884535840000052
And (5) expressing. The corresponding circuit is divided into two parts, and the functions of difference finding and borrowing of the full subtracter are respectively realized.
Figure GDA0003884535840000053
Figure GDA0003884535840000054
Figure GDA0003884535840000055
Figure GDA0003884535840000061
Wherein C is i And
Figure GDA0003884535840000062
writing to the MTJ1-MTJ4 is required; in order to implement the above functions, the present embodiment provides a full-subtractor using an MTJ, including a 1-bit full-subtractor, two write circuits, and two clock logic control circuits;
the 1-bit full subtractor of the present embodiment includes a difference circuit and a borrow circuit, each of the difference circuit and the borrow circuit includes two MTJs, where the MTJ1 and MTJ2 of the difference circuit are respectively used for storing a borrow variable C during difference calculation i Borrow inverse volume
Figure GDA0003884535840000063
The MTJ3 and MTJ4 of the borrow circuit are used for storing the borrow variable C during borrow respectively i Borrow inverse volume
Figure GDA0003884535840000064
The schematic diagram of the structure of the MTJ device is shown in fig. 2, and the device consists of three layers, namely, an oxide insulating layer (e.g., mgO) in the middle, and two ferromagnetic layers (e.g., coFeB). In FIG. 2, when the magnetization directions of the two ferromagnetic layers are opposite, the MTJ exhibits a high resistance state, which corresponds to a logic "0" for the stored content; when the relative magnetization directions of the electrons of the two ferromagnetic layers are the same, the MTJ assumes a low resistance state, which corresponds to a logic "0" stored therein. To achieve a "write" operation, i.e., to change the stored contents of the MTJ, the relative electronic magnetization directions of the two ferromagnetic layers need to be changed, requiring an externally supplied current. In application, it is generally considered that the magnetization direction of electrons on one side is fixed, and only the magnetization direction of electrons on the other side needs to be changed by applying current, so that the "write" operation can be realized.
The resistance states of the MTJ1 and the MTJ3 are the same, the resistance states of the MTJ2 and the MTJ4 are the same, and the resistance states of the MTJ1 and the MTJ2 are opposite;
when the clock is clk at a low level, the four MTJs are turned on, and writing is realized by inputting current to the MTJs;
each writing circuit has two input clock signals clk1 and clk2, when clk1 is 0, forward current is input to MTJ1 and MTJ3, reverse current is input to MTJ2 and MTJ4, when clk2 is 0, forward current is input to MTJ2 and MTJ4, and reverse current is input to MTJ1 and MTJ 3; the clock signals clk1 and clk2 cannot be 0 at the same time;
a clock signal clk1 output by the No. 1 clock logic control circuit simultaneously transmits two write-in circuits, and a clock signal clk2 output by the No. 2 clock logic control circuit simultaneously transmits two write-in circuits;
the clock logic control circuits are all realized by NOR gate circuits;
as shown in fig. 5, three inputs of the clock logic control circuit No. 1 of the present embodiment include clk, en1, and clkw1, clk represents a full-subtractor operating clock, en1 represents an enable control signal for forward writing by the write circuit, clkw1 represents an input clock signal for forward writing by the write circuit, and an output of the clock logic control circuit No. 1 is a clock signal clk1; the three inputs of the clock logic control circuit No. 2 comprise clk, en2 and clkw2, en2 represents an enable control signal written reversely by the writing circuit, clkw2 represents an input clock signal written reversely by the writing circuit, and the output of the clock logic control circuit No. 2 is a clock signal clk2;
in the embodiment, under the clock control of the operation, the operation is divided into two stages by combining a control circuit. In the first stage, when clk is in high level, the write circuit is in a blocking state, and the existence of the write circuit does not influence the normal operation process of the full subtracter; when clk is low, the control circuit is turned on to perform the write operation on the MTJ, and when the write clock clk1 is active, a loop indicated by a thick line is formed to provide the write current in the direction shown in the figure for the write operation on the MTJ; when the write clock clk2 is active, a write current loop 2 is formed, providing a reverse current for MTJ "write"; the writing clock clk1 is controlled by clk, en1 and clkw1 at the same time, and writing can be realized only when clk =0, en1=0 and clkw1=0, and the control function is realized by a nor gate circuit; similarly, the write clock clk2 is controlled by clk, en2, and clkw 2. When designing the write timing, it is necessary to ensure that clk1 and clk2 cannot be active at the same time, i.e. that two write paths cannot be turned on at the same time. The magnitude of the write current is realized by adjusting the width-to-length ratios of the MP11, the MP12, the MN11 and the MN 12.
In a preferred embodiment, the write circuit of this embodiment is shown in fig. 4, where a PMOS transistor MP11, a PMOS transistor MP12, an NMOS transistor MN11, and an NMOS transistor MN12; the source electrode of the PMOS tube MP11 and the source electrode of the PMOS tube MP12 are simultaneously connected with the positive electrode of the power supply; the grid electrode of the PMOS pipe MP11 is connected with the output end of a clock signal clk1 of the clock logic control circuit No. 1; the grid electrode of the PMOS pipe MP12 is connected with the output end of a clock signal clk2 of the clock logic control circuit No. 2; the drain electrode of the PMOS tube MP11 is connected with the drain electrode of the NMOS tube MN11, and the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN12; the source electrode of the NMOS tube MN11 and the source electrode of the NMOS tube MN12 are simultaneously connected with the negative electrode of the power supply of the write-in circuit; the gate of the NMOS transistor MN12 inputs the clock signal clk1_; clk1_ and clk1 are complementary clocks; the gate of the NMOS transistor MN11 inputs the clock signal clk2_; clk2_ and clk2 are complementary clocks.
In fig. 4, complementary control clocks are applied to the gates of MP11 and MN12, and MP12 and MN11 are turned on to form a write current path 1: MP11 → MTJ1 → MTJ2 → MN12; when complementary control clocks are applied to the gates of the MP12 and the MN11, another current path 2 is formed: MP12 → MTJ2 → MTJ1 → MN11. In practical applications, the channel 1 and the channel 2 cannot be opened simultaneously, and the opening and closing time of the two channels needs to be controlled according to the requirement of the MTJ "writing" timing.
In this embodiment, the 1-bit full subtractor includes a difference finding circuit and a borrow bit circuit, and as shown in fig. 3, the difference finding or borrow bit circuit includes a Pre-Charge Sense Amplifier (PCSA), a CMOS dual-rail circuit, and an MTJ. Wherein the PCSA is operative to read out the memory contents of the MTJ device.
As shown in fig. 6, the difference circuit of the present embodiment includes a precharge sensitive amplifier PCSA No. 1, a CMOS dual-rail circuit No. 1, an MTJ2, and an NMOS transistor TN5; the No. 1 precharging sensitive amplifier PCSA comprises a PMOS tube MP1, a PMOS tube TP1, an NMOS tube TN1, a PMOS tube MP2, a PMOS tube TP2, an NMOS tube TN2 and a charging capacitor C L 1 and a charging capacitor C L 2; the grid electrode of the PMOS tube MP1 and the grid electrode of the PMOS tube MP2 are simultaneously connected with a clock signal clk; the source electrode of the PMOS tube MP1, the source electrode of the PMOS tube TP2 and the source electrode of the PMOS tube MP2 are connected with the positive electrode of the full-reduction unit power supply; drain electrode and charging capacitor C of PMOS transistor MP1 L The positive electrode of the transistor 1, the drain electrode of the PMOS transistor TP1, the drain electrode of the NMOS transistor TN1, the grid electrode of the NMOS transistor TN2 and the grid electrode of the PMOS transistor TP2 are simultaneously connected with one point, and the inverse quantity of the output difference of the point is
Figure GDA0003884535840000081
A grid electrode of the PMOS tube TP1, a grid electrode of the NMOS tube TN1, a drain electrode of the PMOS tube TP2, a drain electrode of the NMOS tube TN2, a drain electrode of the PMOS tube MP2 and a charging capacitor C L 2, the positive poles of the two electrodes are simultaneously connected with a point which outputs a difference variable Sub; charging capacitor C L 1 negative electrode, charging capacitor C L 2, the negative electrode of the power supply is simultaneously connected with the negative electrode of the full-reduction device; the No. 1 CMOS double-track circuit comprises NMOS tubes T1 to T8; the drain electrode of the NMOS tube T1 is connected with the drain electrode of the NMOS tube T2, and is simultaneously connected with the source electrode of the NMOS tube TN 1; the drain electrode of the NMOS tube T5 is connected with the drain electrode of the NMOS tube T6, and is simultaneously connected with the source electrode of the NMOS tube TN 2; the source electrode of the NMOS tube T1 is simultaneously connected with the drain electrode of the NMOS tube T3, the source electrode of the NMOS tube T5 and the drain electrode of the NMOS tube T7; the source electrode of the NMOS tube T2 is the same as the drain electrode of the NMOS tube T4, the source electrode of the NMOS tube T6 and the drain electrode of the NMOS tube T8Connecting; the source electrode of the NMOS tube T3 is connected with the source electrode of the NMOS tube T4 and is simultaneously connected with one end of the MTJ 1; the source electrode of the NMOS tube T7 is connected with the source electrode of the NMOS tube T8 and is simultaneously connected with one end of the MTJ 2; grid input signals A of the NMOS tube T1 and the NMOS tube T6, wherein A represents a reduced number; the grid input signals B of the NMOS tube T3 and the NMOS tube T8 represent the number of subtractions; grid input signals of NMOS (N-channel metal oxide semiconductor) tube T2 and NMOS tube T5
Figure GDA0003884535840000082
Grid input signals of NMOS tube T4 and NMOS tube T7
Figure GDA0003884535840000083
The other end of the MTJ1 and the other end of the MTJ2 are connected with the drain electrode of the NMOS tube TN5, and the source electrode of the NMOS tube TN5 is connected with the negative electrode of the full-reduction unit power supply.
As shown in fig. 6, the borrowing bit circuit of the present embodiment includes a precharge sensitive amplifier PCSA No. 2, a CMOS dual-rail circuit No. 2, an MTJ3, an MTJ4, and an NMOS transistor TN6; the No. 2 precharging sensitive amplifier PCSA comprises a PMOS tube MP3, a PMOS tube TP3, an NMOS tube TN3, a PMOS tube MP4, a PMOS tube TP4, an NMOS tube TN4 and a charging capacitor C L 3 and a charging capacitor C L 4; the grid electrode of the PMOS pipe MP3 and the grid electrode of the PMOS pipe MP4 are simultaneously connected with a clock signal clk; the source electrode of the PMOS tube MP3, the source electrode of the PMOS tube TP4 and the source electrode of the PMOS tube MP4 are connected with the anode of the power supply; drain electrode of PMOS transistor MP3 and charging capacitor C L The positive electrode of the transistor 3, the drain electrode of the PMOS transistor TP3, the drain electrode of the NMOS transistor TN3, the grid electrode of the NMOS transistor TN4 and the grid electrode of the PMOS transistor TP4 are simultaneously connected with one point, and the output borrow inverse quantity of the point
Figure GDA0003884535840000084
A grid electrode of the PMOS tube TP3, a grid electrode of the NMOS tube TN3, a drain electrode of the PMOS tube TP4, a drain electrode of the NMOS tube TN4, a drain electrode of the PMOS tube MP4 and a charging capacitor C L 4 is connected with a point at the same time, and the point outputs a borrow variable C i+1 ；C i A borrowing variable, C, from the lower bit to the current bit i+1 Representing a borrow variable for the current bit to the higher bit. Charging capacitor C L 3 negative electrode, charging capacitor C L 4 the negative pole of the generator is connected with the full-reduction unit at the same time for power supplyA negative electrode of a power supply; the No. 2 CMOS double-track circuit comprises NMOS tubes T9 to T12; the drain electrode of the NMOS tube T9 and the drain electrode of the NMOS tube T10 are connected and simultaneously connected with the source electrode of the NMOS tube TN 3; the source electrode of the NMOS tube T9 is connected with the source electrode of the NMOS tube T10 and is simultaneously connected with one end of the MTJ 3; the drain electrode of the NMOS tube T11 and the drain electrode of the NMOS tube T12 are connected, and are connected with the source electrode of the NMOS tube TN 4; the source electrode of the NMOS tube T11 is connected with the source electrode of the NMOS tube T12 and is connected with one end of the MTJ 4; grid input signal of NMOS tube T9
Figure GDA0003884535840000091
A grid electrode of the NMOS tube T10 inputs a signal B; a grid electrode input signal A of an NMOS tube T11; grid input signal of NMOS tube T12
Figure GDA0003884535840000092
The other end of the MTJ4 at the other end of the MTJ3 is connected with the drain electrode of the NMOS tube TN6 at the same time, and the source electrode of the NMOS tube TN6 is connected with the negative electrode of the full-reduction unit power supply.
The precharge sense amplifier PCSA of the present embodiment has advantages of high readout accuracy, high readout speed, low power consumption, and the like, as shown by the dotted line portion.
The voltage of the write circuit power supply is higher than the voltage of the full-subtractor power supply. In this embodiment, the negative electrode of the write circuit power supply and the negative electrode of the full-subtractor power supply are separated from each other, thereby preventing crosstalk.
In a preferred embodiment, equation (5) gives the switching current I of the magnetic tunnel junction co Only when the write current I is write >I co Only then can the MTJ be "written". In the formula (1), I co The magnetic damping coefficient alpha, the gyromagnetic ratio gamma, the electronic electricity e and the free layer magnetization mu 0 M S Anisotropy field H K The free layer volume V is determined jointly. Fig. 7 shows a transient characteristic diagram of a MTJ device model used in this embodiment mode. As can be seen from fig. 7, when a voltage is applied across the MTJ, after a certain time delay, the state of the MTJ changes from "0" to "1", and the current is about 100uA in this embodiment; continuing to apply reverse voltage to MTJ, changing MTJ state from "1" to "0" after a certain time, and making it pass throughThe current was about-100 uA. Therefore, to change the state of the MTJ, i.e., to "write" to the MTJ, an external supply of bi-directional current of about 100uA or more is required.
Figure GDA0003884535840000093
Suppose the memory contents in the input signals A =0, B =0, MTJ1 and MTJ3 are logic memory, namely C i =0, the memory contents in the corresponding MTJ2, MTJ4 are "memory",
Figure GDA0003884535840000094
in the write mode, sub,
Figure GDA0003884535840000095
C i+1 、
Figure GDA0003884535840000096
The terminal is pulled to high level; in the compute mode, clk is high, TN5 is on, track 2: T2-T4-MTJ1-TN5 and 3: and a conductive path is formed in the T5-T7-MTJ2-TN 5. However, because the storage content in the MTJ2 is "storage", the MTJ2 exhibits a low resistance state at this time, the current of the track 3 is large, and the Sub terminal reaches a low level first and then reaches a low level later
Figure GDA0003884535840000097
The terminal goes high. Sub =0 at this time, the difference function is realized; at the same time, TN6 is turned on, and at track 5T9-MTJ3-TN6 and track 8: a conductive path is formed in the T12-MTJ4-TN6, because the memory content in the MTJ4 is 'memory', and the MTJ4 is in a low resistance state at the time, the current of the track 8 is large, and C is i+1 The terminal reaches low level first and then later
Figure GDA0003884535840000098
Reaches a high level, at which time C i+1 And =0, realizing a borrowing function.
When the input signal A, B, and the content (C) stored in the MTJ device i ) For other combinations of sampling values, the output is obtained according to the same working principleSub and C i+1 The value of (d) is in accordance with the truth table of the full subtracter. The truth table for the 1-bit full subtracter is given in table 1.
TABLE 1 bit full subtracter truth table
Figure GDA0003884535840000101
Verification was performed using the full subtracter of the present embodiment.
According to the full subtractor truth table, set A, B, C i Figure 8 shows a verification waveform. From simulation results, in the write mode, when clk1=0, the MTJ is written, and the memory content in MTJ1 changes from "0" to "1" (C) i ) At the same time, the stored content in MTJ2 changes from "1" to "0"
Figure GDA0003884535840000102
When clk2=0, the memory content in MTJ1 changes from "1" to "0", and the memory content in MTJ2 changes from "0" to "1".
In "calculation mode", when a =0, b =0, c i (Sub =0,C) =0 i+1 =0; when A =1,B =0,C i Sub =1,C when =0 i+1 =0; when A =0,B =1,C i (Sub =1,C) =0 i+1 =1; when A =1,B =1,C i (Sub =0,C) =0 i+1 =0; when A =0,B =0,C i =1, sub =1,C i+1 =1; when A =1,B =0,C i Sub =0,C when =1 i+1 =0; when A =0,B =1,C i =1, sub =0,C i+1 =1; when A =1,B =1,C i =1, sub =1,C i+1 =1; it can be seen that the simulation results are consistent with the functions described in the truth table.
As can be seen from the simulation results, the write circuit designed in this embodiment can control the full-subtractor to switch between the write mode and the calculation mode according to the system timing, and simultaneously perform correct and reliable write to the MTJ without affecting the normal function of the full-subtractor.
The present embodiment provides a control device capable of switching between a write mode and a read mode. In a write mode, reliably writing to the MTJ; in the calculation mode, the input signal is calculated to realize the function of a full reducer. Fig. 8 shows a timing diagram and an operation result diagram of the full subtractor designed in this embodiment, and it can be seen that the addition of the write circuit can control the full subtractor to normally switch between the write mode and the calculation mode, thereby implementing the normal logic function of the subtractor. Meanwhile, the MTJ is applied, and compared with a common memory device, the system power consumption can be greatly saved.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that various dependent claims and the features described herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims (6)

1. A full-subtractor using MTJ comprises a 1-bit full-subtractor, two write circuits, and two clock logic control circuits;
the 1-bit full subtracter comprises a difference finding circuit and a borrow bit circuit, wherein the difference finding circuit and the borrow bit circuit respectively comprise two MTJs, and the MTJ1 and the MTJ2 of the difference finding circuit are respectively used for storing a borrow variable C during difference finding i Borrow inverse volume
Figure FDA0003884535830000011
The MTJ3 and MTJ4 of the borrow circuit are used for storing the borrow variable C during borrow respectively i Borrow inverse volume
Figure FDA0003884535830000012
The resistance states of the MTJ1 and the MTJ3 are the same, the resistance states of the MTJ2 and the MTJ4 are the same, and the resistance states of the MTJ1 and the MTJ2 are opposite;
each writing circuit has two input clock signals clk1 and clk2, when clk1 is 0, forward current is input to MTJ1 and MTJ3, reverse current is input to MTJ2 and MTJ4, when clk2 is 0, forward current is input to MTJ2 and MTJ4, and reverse current is input to MTJ1 and MTJ 3; the clock signals clk1 and clk2 cannot be 0 at the same time;
a clock signal clk1 output by the No. 1 clock logic control circuit simultaneously transmits two write-in circuits, and a clock signal clk2 output by the No. 2 clock logic control circuit simultaneously transmits two write-in circuits;
the clock logic control circuits are all realized by NOR gate circuits;
the three inputs of the clock logic control circuit No. 1 comprise clk, en1 and clkw1, wherein clk represents a full-subtracting device working clock, en1 represents an enabling control signal written in the forward direction of a writing circuit, clkw1 represents an input clock signal written in the forward direction of the writing circuit, and the output of the clock logic control circuit No. 1 is a clock signal clk1; the three inputs of the clock logic control circuit No. 2 comprise clk, en2 and clkw2, en2 represents an enable control signal written reversely by the writing circuit, clkw2 represents an input clock signal written reversely by the writing circuit, and the output of the clock logic control circuit No. 2 is a clock signal clk2.
2. The full subtractor using MTJ of claim 1, wherein the write circuit comprises a PMOS transistor MP11, a PMOS transistor MP12, an NMOS transistor MN11, and an NMOS transistor MN12;
the source electrode of the PMOS tube MP11 and the source electrode of the PMOS tube MP12 are simultaneously connected with the positive electrode of the power supply;
the grid electrode of the PMOS pipe MP11 is connected with the output end of a clock signal clk1 of the clock logic control circuit No. 1;
the grid electrode of the PMOS pipe MP12 is connected with the output end of a clock signal clk2 of the clock logic control circuit No. 2;
the drain electrode of the PMOS tube MP11 is connected with the drain electrode of the NMOS tube MN11, and the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN12;
the source electrode of the NMOS tube MN11 and the source electrode of the NMOS tube MN12 are simultaneously connected with the negative electrode of the power supply of the write-in circuit;
the gate of the NMOS transistor MN12 inputs the clock signal clk1_; clk1_ and clk1 are complementary clocks;
the gate of the NMOS transistor MN11 inputs the clock signal clk2_; clk2_ and clk2 are complementary clocks.
3. The MTJ-applied full subtractor of claim 2 wherein the differencing circuit comprises a precharge-sensitive amplifier PCSA # 1, a CMOS dual-rail circuit # 1, MTJ2, and NMOS transistor TN5;
the No. 1 precharging sensitive amplifier PCSA comprises a PMOS tube MP1, a PMOS tube TP1, an NMOS tube TN1, a PMOS tube MP2, a PMOS tube TP2, an NMOS tube TN2 and a charging capacitor C L 1 and a charging capacitor C L 2；
The grid electrode of the PMOS tube MP1 and the grid electrode of the PMOS tube MP2 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP1, the source electrode of the PMOS tube TP2 and the source electrode of the PMOS tube MP2 are connected with the positive electrode of the power supply of the full reducer;
drain electrode and charging capacitor C of PMOS transistor MP1 L The positive electrode of the transistor 1, the drain electrode of the PMOS transistor TP1, the drain electrode of the NMOS transistor TN1, the grid electrode of the NMOS transistor TN2 and the grid electrode of the PMOS transistor TP2 are simultaneously connected with one point, and the inverse quantity of the point output difference
Figure FDA0003884535830000021
A grid electrode of the PMOS tube TP1, a grid electrode of the NMOS tube TN1, a drain electrode of the PMOS tube TP2, a drain electrode of the NMOS tube TN2, a drain electrode of the PMOS tube MP2 and a charging capacitor C L 2, the positive poles of the two electrodes are simultaneously connected with a point which outputs a difference variable Sub;
charging capacitor C L 1 negative electrode, charging capacitor C L 2, the negative electrode of the power supply is simultaneously connected with the negative electrode of the full-reduction device;
the No. 1 CMOS double-track circuit comprises NMOS tubes T1 to T8;
the drain electrode of the NMOS tube T1 is connected with the drain electrode of the NMOS tube T2, and is simultaneously connected with the source electrode of the NMOS tube TN 1;
the drain electrode of the NMOS tube T5 is connected with the drain electrode of the NMOS tube T6, and is simultaneously connected with the source electrode of the NMOS tube TN 2;
the source electrode of the NMOS tube T1 is simultaneously connected with the drain electrode of the NMOS tube T3, the source electrode of the NMOS tube T5 and the drain electrode of the NMOS tube T7;
the source electrode of the NMOS tube T2 is simultaneously connected with the drain electrode of the NMOS tube T4, the source electrode of the NMOS tube T6 and the drain electrode of the NMOS tube T8;
the source electrode of the NMOS tube T3 is connected with the source electrode of the NMOS tube T4 and is simultaneously connected with one end of the MTJ 1;
the source electrode of the NMOS tube T7 is connected with the source electrode of the NMOS tube T8 and is simultaneously connected with one end of the MTJ 2;
the grid input signals A of the NMOS tube T1 and the NMOS tube T6 represent the number of the subtractions;
the grid input signals B of the NMOS tube T3 and the NMOS tube T8 represent the number of subtractions;
grid input signals of NMOS (N-channel metal oxide semiconductor) tube T2 and NMOS tube T5
Figure FDA0003884535830000022
Grid input signals of NMOS tube T4 and NMOS tube T7
Figure FDA0003884535830000023
A and
Figure FDA0003884535830000024
is a pair of complementary signals;
b and B
Figure FDA0003884535830000025
Is a pair of complementary signals;
the other end of the MTJ1 and the other end of the MTJ2 are connected with the drain electrode of the NMOS tube TN5, the source electrode of the NMOS tube TN5 is connected with the negative electrode of the full-reduction unit power supply, and the gate electrode of the NMOS tube TN5 is connected with the clock signal clk.
4. The MTJ-applied full subtractor according to claim 3, wherein the borrowing circuit comprises a precharge-sensitive amplifier PCSA No. 2, a CMOS dual-rail circuit No. 2, MTJ3, MTJ4 and NMOS transistor TN6;
the No. 2 precharging sensitive amplifier PCSA comprises a PMOS tube MP3, a PMOS tube TP3, an NMOS tube TN3, a PMOS tube MP4, a PMOS tube TP4, an NMOS tube TN4 and a charging capacitor C L 3 and a charging capacitor C L 4；
The grid electrode of the PMOS pipe MP3 and the grid electrode of the PMOS pipe MP4 are simultaneously connected with a clock signal clk;
the source electrode of the PMOS tube MP3, the source electrode of the PMOS tube TP4 and the source electrode of the PMOS tube MP4 are connected with the anode of the power supply;
drain electrode and charging capacitor C of PMOS (P-channel metal oxide semiconductor) transistor MP3 L The positive electrode of the transistor 3, the drain electrode of the PMOS transistor TP3, the drain electrode of the NMOS transistor TN3, the grid electrode of the NMOS transistor TN4 and the grid electrode of the PMOS transistor TP4 are simultaneously connected with one point, and the output borrow inverse quantity of the point
Figure FDA0003884535830000031
A grid electrode of the PMOS tube TP3, a grid electrode of the NMOS tube TN3, a drain electrode of the PMOS tube TP4, a drain electrode of the NMOS tube TN4, a drain electrode of the PMOS tube MP4 and a charging capacitor C L 4 is connected with a point at the same time, and the point outputs a borrow variable C i+1 ；
C i A borrowing variable, C, from the lower bit to the current bit i+1 A borrow variable representing the current bit to the high bit;
charging capacitor C L 3 negative electrode, charging capacitor C L 4, the negative electrode of the power supply is simultaneously connected with the negative electrode of the power supply of the full-reduction device;
the No. 2 CMOS double-track circuit comprises NMOS tubes T9 to T12;
the drain electrode of the NMOS tube T9 and the drain electrode of the NMOS tube T10 are connected and simultaneously connected with the source electrode of the NMOS tube TN 3;
the source electrode of the NMOS tube T9 is connected with the source electrode of the NMOS tube T10 and is simultaneously connected with one end of the MTJ 3;
the drain electrode of the NMOS tube T11 and the drain electrode of the NMOS tube T12 are connected, and are connected with the source electrode of the NMOS tube TN 4;
the source electrode of the NMOS tube T11 is connected with the source electrode of the NMOS tube T12 and is connected with one end of the MTJ 4;
grid input signal of NMOS tube T9
Figure FDA0003884535830000032
A grid electrode of the NMOS tube T10 inputs a signal B;
a grid electrode input signal A of an NMOS tube T11;
grid input signal of NMOS tube T12
Figure FDA0003884535830000033
The other end of the MTJ4 at the other end of the MTJ3 is connected with the drain electrode of the NMOS tube TN6, the source electrode of the NMOS tube TN6 is connected with the negative electrode of the full-subtracting device power supply, and the grid electrode of the NMOS tube TN6 is connected with a clock signal clk.
5. The full reducer using MTJ of claim 3, wherein a voltage of a write circuit power supply is higher than a voltage of a full reducer power supply.
6. The full-subtractor using an MTJ of claim 3, wherein the current of the forward current is greater than 100uA and the current of the reverse current is less than-100 uA.
CN202110821028.1A 2021-07-20 2021-07-20 Full-subtracting device applying MTJ (magnetic tunnel junction) Active CN113470715B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110821028.1A CN113470715B (en) 2021-07-20 2021-07-20 Full-subtracting device applying MTJ (magnetic tunnel junction)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110821028.1A CN113470715B (en) 2021-07-20 2021-07-20 Full-subtracting device applying MTJ (magnetic tunnel junction)

Publications (2)

Publication Number Publication Date
CN113470715A CN113470715A (en) 2021-10-01
CN113470715B true CN113470715B (en) 2022-11-25

Family

ID=77881408

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110821028.1A Active CN113470715B (en) 2021-07-20 2021-07-20 Full-subtracting device applying MTJ (magnetic tunnel junction)

Country Status (1)

Country Link
CN (1) CN113470715B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104778967A (en) * 2015-04-20 2015-07-15 北京航空航天大学 Spin-hall-effect-assisted spin-transfer torque nonvolatile trigger
CN109861685A (en) * 2018-12-29 2019-06-07 宁波大学 A kind of full subtracter realized using three-phase double track preliminary filling logic
CN112564899A (en) * 2020-12-07 2021-03-26 哈尔滨工业大学（威海） Double-track MTJ (magnetic tunnel junction) and CMOS (complementary metal oxide semiconductor) mixed lookup table circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8543635B2 (en) * 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104778967A (en) * 2015-04-20 2015-07-15 北京航空航天大学 Spin-hall-effect-assisted spin-transfer torque nonvolatile trigger
CN109861685A (en) * 2018-12-29 2019-06-07 宁波大学 A kind of full subtracter realized using three-phase double track preliminary filling logic
CN112564899A (en) * 2020-12-07 2021-03-26 哈尔滨工业大学（威海） Double-track MTJ (magnetic tunnel junction) and CMOS (complementary metal oxide semiconductor) mixed lookup table circuit

Also Published As

Publication number Publication date
CN113470715A (en) 2021-10-01

Similar Documents

Publication Publication Date Title
Trinh et al. Magnetic adder based on racetrack memory
JP4631090B2 (en) Logic-in-memory circuit using magnetoresistance effect element
Konno et al. Fully functional operation of low-power 64-kb Josephson-CMOS hybrid memories
Huang et al. A low-power low-VDD nonvolatile latch using spin transfer torque MRAM
WO2012149569A1 (en) Self-body biasing sensing circuit for resistance-based memories
CN113470715B (en) Full-subtracting device applying MTJ (magnetic tunnel junction)
US20040196082A1 (en) Circuit arrangement
CN113452354B (en) RS trigger based on MTJ device
US11764786B2 (en) Magnetoelectric majority gate device
CN116665728A (en) Memory full adder circuit for magnetic random access memory
CN113889158A (en) Memory computing circuit and device based on SRAM and electronic equipment
CN109872741B (en) Multi-voltage control nonvolatile Boolean logic architecture based on magnetic tunnel junction
CN110120237B (en) STT-MRAM sensing circuit with good sensing margin
Yamani et al. Design and performance benchmarking of hybrid tunnel FET/STT-MTJ-based logic in-memory designs for energy efficiency
Gong et al. An MTJ Based 1-Bit Full Subtractor and Its Reading and Writing Circuit
Zeinali et al. Sensing of spintronic memories
CN104795089A (en) Control method for low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit
Kim et al. Variation-tolerant separated pre-charge sense amplifier for resistive non-volatile logic circuit
Liu et al. Novel nonvolatile lookup table design based on voltage-controlled spin orbit torque memory
US20240120923A1 (en) Spin logic device based on magnetic tunnel junction and electronic apparatus comprising the same
Wang et al. Magnetic random-access memory-based approximate computing: An overview
Samiee et al. Energy efficient mobile service computing with differential Spintronic-C-elements: A logic-in-memory asynchronous computing paradigm
CN215731719U (en) Bit unit and data analysis unit
Gong et al. An MTJ reading and writing control circuit applied in a 1-bit full adder
Wu et al. Circuit Sensing Techniques in Magnetoresistive Random-Access Memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant