CN215731719U - Bit unit and data analysis unit - Google Patents

Abstract

The application provides a bit unit and a data parsing unit. In the bit unit, two inverters are connected end to form a latch structure, the latch structure is respectively connected with a first bit line and a first bit bar line through a first switch module, and the first switch module is controlled by a first word line, so that data writing and reading can be realized; in addition, as the reverser and the first switch module comprise MOS tubes and at least one MOS tube is an FDSOI-MOS tube, the leakage current of the bit unit in the actual operation process is reduced, and the influence of the leakage current on the operation of the bit unit is reduced; moreover, after the FDSOI-MOS tube is adopted, the FDSOI-MOS tube has extremely small threshold voltage variability, namely has better threshold voltage uniformity, and is further favorable for timing convergence of a digital integrated circuit corresponding to the bit unit.

Description

Bit unit and data analysis unit

Technical Field

The present invention relates to the field of semiconductor technology, and in particular, to a bit cell and a data parsing unit.

Background

On any new process, developing the bit cells of the memory is one of the most important jobs, and only this makes the process capable of data storage. Among various bit cells, high density bit cells are the most important, for example, in a highly integrated chip, the high density bit cells occupying about 30% to 60% of the whole chip area can directly affect the performance of the chip.

At present, in the prior art, there is a bit cell, which has a high leakage current during the actual operation process, thereby affecting the operation of the bit cell.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention provides a bit cell and a data parsing unit to reduce the influence of the leakage current of the bit cell on the operation of the bit cell during the actual operation process.

In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

one aspect of the present application provides a bit cell, including: a first switch module and two inverters; wherein:

the two inverters are connected end to form a latch structure, and the latch structure is respectively connected with a first bit line and a first bit bar line through the first switch module; the first switch module is controlled by a first word line;

the inverter and the first switch module both comprise MOS (metal oxide semiconductor) tubes, and at least one MOS tube is an FDSOI-MOS tube.

Optionally, the FDSOI-MOS transistor is further provided with: a body-biased connecting pole; the body bias voltage connection is connected to a voltage generator.

Optionally, the bulk bias connection receives a positive or negative voltage to form a forward or reverse bias.

Optionally, the first switch module includes: the method comprises the following steps: the MOS transistor comprises a first MOS transistor and a second MOS transistor; wherein:

the first MOS tube and the second MOS tube are both NMOS tubes;

the grid electrode of the first MOS tube is connected with the first word line, the source electrode of the first MOS tube is connected with any one connection point of the latch structure, and the drain electrode of the first MOS tube is connected with the first bit line;

the grid electrode of the second MOS tube is connected with the first word line, the source electrode of the second MOS tube is connected with the other connection point of the latch structure, and the drain electrode of the second MOS tube is connected with the first bit line.

Optionally, the method further includes: a second switch module; wherein:

the latch structure is connected with the data transmission line through the second switch module;

the second switch module is controlled by a second word line.

Optionally, if the data transmission line includes a second bit line, the second switch module includes: a third MOS transistor and a fourth MOS transistor; wherein:

the third MOS tube and the fourth MOS tube are both NMOS tubes;

the grid electrode of the third MOS tube is connected with the second word line, the drain electrode of the third MOS tube is connected with the second bit line, the source electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, the grid electrode of the fourth MOS tube is connected with any connection point of the latch structure, and the source electrode of the fourth MOS tube is connected with the public ground.

Optionally, if the data transmission line includes a second bit line and a second bit bar line, the second switch module includes: a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube; wherein

The fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are all NMOS transistors;

the grid electrode of the fifth MOS tube is connected with the second word line, the drain electrode of the fifth MOS tube is connected with the second bit line, the source electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube, the grid electrode of the sixth MOS tube is connected with any connection point of the latch structure, and the source electrode of the sixth MOS tube is connected with the common ground;

the grid electrode of the seventh MOS tube is connected with the second word line, the drain electrode of the seventh MOS tube is connected with the second bit line, the source electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube, the grid electrode of the eighth MOS tube is connected with the other connection point of the latch structure, and the source electrode of the eighth MOS tube is connected with the public ground.

Optionally, the inverter includes: a ninth MOS transistor and a tenth MOS transistor; wherein:

the ninth MOS transistor is a PMOS transistor, and the tenth MOS transistor is an NMOS transistor;

the ninth MOS tube and the tenth MOS tube are connected in a common grid mode, and a connection point is used as an input end of the inverter;

the ninth MOS tube and the tenth MOS tube are connected with a common drain electrode, and a connection point is used as an output end of the inverter;

and the source electrode of the ninth MOS tube is connected with a working power supply, and the source electrode of the tenth MOS tube is connected with the public ground.

Another aspect of the present application provides a data parsing unit, including: a data parsing module and a bit unit as described in any one of the previous aspects of the present application; wherein:

when the bit unit only comprises a first switch module, two input ends of the data analysis module are respectively connected with a first bit line and a first bit bar line of the bit unit;

when the bit unit further comprises a second switch module, if the second switch module comprises two MOS, one input end of the data analysis module receives a reference voltage, and the other input end is connected with a second bit line;

when the bit unit further comprises a second switch module, if the second switch module comprises four MOS transistors, two input ends of the data analysis module are respectively connected with the second bit line and the second bit bar line;

the output end of the data analysis module outputs the stored data of the bit unit; the stored data is obtained by analyzing the voltage of the corresponding bit line by the data analysis module.

Optionally, the data analysis module is a sense amplifier; wherein:

two input ends of the sensing amplifier are used as two input ends of the data analysis module, and an output end of the sensing amplifier is used as an output end of the data analysis module.

As can be seen from the above technical solutions, the present invention provides a bit cell, including: a first switch module and two inverters. In the bit unit, two inverters are connected end to form a latch structure, the latch structure is respectively connected with a first bit line and a first bit bar line through a first switch module, and the first switch module is controlled by a first word line, so that data writing and reading can be realized; in addition, as the reverser and the first switch module comprise MOS tubes and at least one MOS tube is an FDSOI-MOS tube, the leakage current of the bit unit in the actual operation process is reduced, and the influence of the leakage current on the operation of the bit unit is reduced; moreover, after the FDSOI-MOS tube is adopted, the FDSOI-MOS tube has extremely small threshold voltage variability, namely has better threshold voltage uniformity, and is further favorable for timing convergence of a digital integrated circuit corresponding to the bit unit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a bit cell provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of the internal structure of a bulk silicon MOS transistor;

FIG. 3 is a schematic diagram of the internal structure of the FDSOI-MOS transistor;

FIG. 4 is a schematic diagram of another internal structure of the FDSOI-MOS transistor;

fig. 5 is a schematic structural diagram of a 6T bit cell provided in an embodiment of the present application;

fig. 6 is a schematic diagram of another structure of a bit cell according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an 8T bit cell provided in an embodiment of the present application;

fig. 8 is a schematic structural diagram of a 10T bit cell according to an embodiment of the present application;

fig. 9 to 11 are schematic diagrams of three structures of a data parsing unit according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In this application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In order to reduce the influence of leakage current of a bit cell on the operation of the bit cell in the actual operation process, an embodiment of the present application provides a bit cell, as shown by a dashed-dotted line frame in fig. 1, specifically including: a first switching module 01 and two inverters 02.

The two inverters 02 are connected end to form a latch structure, i.e., they output and input each other, so that original data, such as 0 or 1, can be always maintained even without external input, i.e., can be used for storing data.

The latch structure is connected to a first bit line BLT1 and a first inverted bit line BLC1 through a first switch module 01, and a control terminal of the first switch module 01 is connected to a first word line WL 1.

When new data is written, the first word line WL1 is set to high level, and the first switch module 01 is turned on; after the first switch module 01 is turned on, new data is placed on the first bit line BLT1 and the first bar bit line BLC1, i.e. the first bit line BLT1 and the first bar bit line BLC1 are set to low level and high level, respectively, for example, if the new data is 1, the first bit line BLT1 is set to high level and the first bar bit line BLC1 is set to low level, so that the new data can be stored in the latch structure.

When reading the stored data, the first bit line BLT1 and the first bar bit line BLC1 are charged to a high level and then released such that the first bit line BLT1 and the first bar bit line BLC1 are both in a floating or weakly pulled-up state; then, setting the first word line WL1 to a high level, and making the potentials of the two connection points of the latch structure to be respectively neutralized with the potentials of the first bit line BLT1 and the first bit bar line BLC1, and finally, by determining the potential relationship between the first bit line BLT1 and the first bit bar line BLC1, the stored data can be read.

In the above, during the process of writing new data and reading stored data, whether to write or read is controlled by the first word line WL1, i.e. the first word line WL1 is a read-write word line; in the process, data is written or read through the first bit line BLT1 and the first bit bar line BLC1, i.e., the first bit line BLT1 and the first bit bar line BLC1 are a read-write bit line and a read-write bit bar line, respectively; therefore, in this embodiment, the read and write channels of the bit cell are the same.

In addition, the inverter 02 and the first switch module 01 both include MOS transistors, and in the prior art, all the MOS transistors in the inverter 02 and the first switch module 01 are bulk silicon MOS transistors, and the internal structure of the bulk silicon MOS transistor is shown in fig. 2 (only NMOS transistors are shown as an example in the figure):

if a forward voltage VGS is applied between the gate G and the source S, i.e., VGS > 0, SiO will be between the gate G and the P-type silicon substrate₂In the insulating layer, an electric field pointing to the P-type silicon substrate from the gate G is generated; but due to SiO₂The forward voltage VGS applied to the gate G cannot form a current due to the insulating effect of the insulating layer, so that SiO is generated₂A capacitor is formed on two sides of the insulating layer, namely VGS is equivalent to capacitor charging, and an electric field is formed at the same time; as the forward voltage VGS gradually increases, attracted by the forward voltage VGS of the gate G, a large number of electrons are accumulated on the other side of the capacitor, thereby forming an N-type electric channel from the drain D to the source S; when the forward voltage VGS of the grid G is larger than the starting voltage of the NMOS tube, the N channel starts to be conducted, and drain current is formed.

In the present application, at least one of the MOS transistors in the inverter 02 and the switch module 01 is an FDSOI-MOS transistor, and the internal structure of the FDSOI-MOS transistor is shown in fig. 3 (only an NMOS transistor is shown as an example in the figure):

as can be seen from comparing fig. 3 and fig. 2, compared with the bulk silicon MOS transistor, the FDSOI-MOS transistor has an extra thin buried oxide layer 10, so that the leakage of the FDSOI-MOS transistor is greatly reduced, that is, the output level value of the FDSOI-MOS transistor is more stable; in addition, the channel between the source S and the drain D of the FDSOI-MOS transistor is not doped at all, i.e., the channel is a fully depleted region, so in this case, the FDSOI-MOS transistor has a very small threshold voltage variability, i.e., has better threshold voltage uniformity, compared to a bulk silicon MOS transistor.

Therefore, the bit cell provided by the application reduces the leakage current of the bit cell in the actual operation process, and further reduces the influence of the leakage current on the operation of the bit cell. And, since the FDSOI-MOS has better uniformity of the threshold voltage, timing convergence of the digital integrated circuit corresponding to the bit cell is facilitated.

In addition, as shown in fig. 4, the FDSOI-MOS transistor is further provided with a bulk bias connection VB connected to the voltage generator; specifically, the Body Bias voltage connection VB may be connected to a positive voltage or a negative voltage to form FBB (Forward Bias) and RBB (Reverse Bias); when the FDSOI-MOS tube is an NMOS tube, if the body bias voltage connecting pole VB receives a positive voltage, a forward bias voltage is formed, and if the body bias voltage connecting pole VB receives a negative voltage, a reverse bias voltage is formed; when the FDSOI-MOS transistor is a PMOS transistor, a forward bias is formed when the bulk bias connection terminal VB receives a negative voltage, and a reverse bias is formed when the bulk bias connection terminal VB receives a positive voltage.

And, the FDSOI-MOS tube can dynamically adjust the whole bias voltage according to the use condition, namely: the switching speed of the FBB can be accelerated by applying the FBB, and the leakage current of the RBB can be reduced by applying the RBB; therefore, the bit cell using the FDSOI-MOS transistor also has the above advantages, and the description thereof is omitted.

It should be noted that the larger the number of FDSOI-MOS transistors included in the bit cell, the better the advantage of the FDSOI-MOS transistors can be embodied, and the number of FDSOI-MOS transistors in the bit cell is not limited herein, which may be determined according to specific situations, and is within the protection scope of the present application.

In one embodiment of the present application, the specific structure of the inverter 02 is shown in fig. 5, 7-11, and includes: a ninth MOS transistor T9 and a tenth MOS transistor T10; the ninth MOS transistor T9 is a PMOS transistor, the tenth MOS transistor T10 is an NMOS transistor, the ninth MOS transistor T9 and the tenth MOS transistor T10 are connected in common-gate, and the connection point is used as the input end of the corresponding inverter 02; the ninth MOS transistor T9 and the tenth MOS transistor T10 are connected with a common drain electrode, and the connection point is used as the output end of the corresponding inverter 02; the source of the ninth MOS transistor T9 is connected to the operating power supply VDD, and the source of the tenth MOS transistor T10 is connected to the common ground VSS.

The above is only one specific structure of the inverter, and in practical applications, including but not limited to this embodiment, there is no specific limitation here, and it is within the scope of the present application as the case may be.

Another embodiment of the present application provides a specific implementation manner of the first switch module 01, and a specific structure thereof is shown in fig. 5, and the implementation manner includes: a first MOS transistor T1 and a second MOS transistor T2.

In this embodiment of the first switch module 01, the gate of the first MOS transistor T1 is connected to the first word line WL1, the source of the first MOS transistor T1 is connected to any connection point of the latch structure, and the drain of the first MOS transistor T1 is connected to the first bit line BLT 1; the gate of the second MOS transistor T2 is connected to the first word line WL1, the source of the second MOS transistor T2 is connected to the other connection point of the latch structure, and the drain of the second MOS transistor T2 is connected to the first flip-bit line BLC 1.

The first MOS transistor T1 and the second MOS transistor T2 are both NMOS transistors; in practical applications, including but not limited to the above embodiments, there is no specific limitation, and the embodiments are within the scope of the present application.

The above is only one embodiment of the data reading and writing module, and in practical applications, including but not limited to the above embodiments, the embodiments are not specifically limited herein, and may be within the protection scope of the present application as the case may be.

In the bit cell in which the first switch module 01 adopts the above-described embodiment, the two inverters 02 include four MOS transistors in total, and the first switch module 01 includes two MOS transistors including six MOS transistors in total, so that the bit cell is also referred to as a 6T bit cell.

In the 6T bit cell, six MOS transistors are FDSOI-MOS transistors, where VB of the first MOS transistor T1, the second MOS transistor T2, the ninth MOS transistor T9, and the tenth MOS transistor T10 in fig. 5 is a body bias connection pole of the FDSOI-MOS transistor.

The writing process of the 6T bit unit is:

the first word line WL1 is selected, i.e. the first word line WL1 is asserted high, so that the first MOS transistor T1 and the second MOS transistor T2 are turned on; after the first MOS transistor T1 and the second MOS transistor T2 are turned on, new data, for example, 0 or 1, is placed on the first bit line BLT1 and the first bit bar line BLC1, that is, the first bit line BLT1 is set to a low level or a high level, and the first bit bar line BLC1 is set to a level opposite to the low level, so that the new data can be introduced into the latch structure formed by the two inverters 02 through the first MOS transistor T1 and the second MOS transistor T2, and the purpose of storing the new data is further achieved.

The reading process of the 6T bit cell is as follows:

before the first MOS transistor T1 and the second MOS transistor T2 are turned on, the first bit line BLT1 and the first flip bit line BLC1 are charged to a high level, and then the first bit line BLT1 and the first flip bit line BLC1 are released, so that the first bit line BLT1 and the first flip bit line BLC1 are both in a floating or weak pull-up state; at this time, the first word line WL1 controls the first MOS transistor T1 and the second MOS transistor T2 to be turned on, if the data originally stored in the latch structure is 1, that is, the connection point of the latch structure and the first MOS transistor T1 is at a high level, and the connection point of the latch structure and the second MOS transistor T2 is at a low level, the first bit line BLT1 still maintains at the high level, and part of the charge on the first bit line BLC1 is released through the second MOS transistor T2, so that the potential of the first bit line BLC1 drops between the high level and the low level, and at this time, the potential of the first bit line BLC1 is usually higher than half of the difference between the high level and the low level, but is not equal to the low level, therefore, when it is determined that the potential of the first bit line BLT1 is higher than the potential of the first bit line BLC1, the data stored in the latch structure is known to be 1; if the data in the original latch structure is 0, the above procedure is reversed, and the above procedure can be referred to, and the details are not repeated here.

Since the two MOS transistors in the inverter 02 are respectively connected to the operating power supply VDD and the common ground VSS in the 6T bit cell, the high level of the two MOS transistors is equal to the voltage value of the operating power supply VDD, and the low level of the two MOS transistors is equal to the voltage value of the common ground VSS, so that half of the difference between the high level and the low level is half of the rated voltage of the 6T bit cell.

It should be noted that in the 6T unit, the MOS transistors are all FDSOI-MOS transistors, so that leakage current during the operation of the MOS transistors can be reduced, and further, the influence of the leakage current on the operation of the MOS transistors can be reduced; and, since the FDSOI-MOS transistor has better uniformity of threshold voltage, timing convergence of the digital integrated circuit corresponding to the 6T bit cell is facilitated; in addition, the FDSOI-MOS tube is provided with a body bias voltage connection pole VB, the body bias voltage connection pole VB can be connected with a common ground VSS or a working power supply VDD according to the difference between an N-type MOS tube and a P-type MOS tube, so that the 6T bit unit can also dynamically adjust the body bias voltage of each MOS tube, and the operation speed can be effectively accelerated or the leakage current can be reduced.

Another embodiment of the present application provides another implementation of a bit cell, which may be seen in a dashed-dotted line frame in fig. 6, and on the basis of the above implementation, the implementation further includes: a second switch module 03.

In this embodiment of the bit cell, the latch structure is connected to the data transmission line 04 through the second switch module 03, and the second switch module 03 is controlled by the second word line WL 2.

When new data is written, the same procedure as that in the above embodiment can be referred to the description in the above embodiment, and the description is omitted here.

When reading the stored data, the second word line WL2 is set to high level, and the stored data can be read by the potential of the data transmission line 04.

From the above, it can be seen that whether writing is controlled by the first word line WL1 in the process of writing new data, i.e. when the first word line WL1 is a write word line, and whether reading is controlled by the second word line WL2 in the process of reading stored data, i.e. when the second word line WL2 is a read word line; also, the write data is passed through the first bit line BLT1 and the first bar bit line BLC1, and the read data is passed through the data transmission line 04; therefore, in this embodiment, the read and write channels of the bit cells are different.

It should be noted that, compared with the above embodiment, the embodiment can implement data reading and data writing simultaneously, so that the processing speed of the bit unit on the data is increased, that is, the silicon wafer speed is increased, and thus the embodiment is applicable to more complex data calling scenarios, and further brings great economic benefits, and is beneficial to long-term popularization.

Another embodiment of the present application provides an implementation manner of the second switch module 03, which is suitable for a case where the data transmission line 04 is a second bit line BLT2, and the specific structure of the implementation manner is as shown in fig. 7, and specifically includes: a third MOS transistor T3 and a fourth MOS transistor T4.

In this embodiment of the second switch module 03, the gate of the third MOS transistor T3 is connected to the second word line WL2, the drain of the third MOS transistor T3 is connected to the second bit line BLT2, the source of the third MOS transistor T3 is connected to the drain of the fourth MOS transistor T4, the gate of the fourth MOS transistor T4 is connected to any connection point of the latch structure, and the source of the fourth MOS transistor T4 is connected to the common ground VSS.

The third MOS transistor T3 and the fourth MOS transistor T4 are NMOS transistors, and in practical applications, including but not limited to the foregoing embodiments, the embodiments are not limited herein, and all of them are within the protection scope of the present application as the case may be.

The above is only one embodiment of the second switch module 03, and in practical applications, including but not limited to the above embodiments, the embodiments are not specifically limited herein, and may be within the protection scope of the present application as the case may be.

In the bit cell in which the second switch module 03 adopts the above embodiment, the two inverters 02 include four MOS transistors in total, the first switch module 01 includes two MOS transistors, and the second switch module 03 includes two MOS transistors and eight MOS transistors in total, so that the bit cell is also referred to as an 8T bit cell.

As shown in fig. 7, in the 8T bit cell, eight MOS transistors are FDSOI-MOS transistors, wherein VB of the third MOS transistor T3 and the fourth MOS transistor T4 in fig. 7 is also the body bias connection pole of the FDSOI-MOS transistor.

The writing process of the 8T bit unit is the same as that of the 6T bit unit, and reference is made to the above description, which is not repeated herein.

The reading process of the 8T bit cell is as follows:

the second word line WL2 is selected, i.e. the second word line WL2 is set to high level, if the data originally stored in the latch structure is 1, i.e. the potential at the connection point of the latch structure and the fourth MOS transistor T4 is high level, the fourth MOS transistor T4 is turned on; after the fourth MOS transistor T4 is turned on, the source of the third MOS transistor T3 is connected to the common ground VSS, i.e., the source potential of the third MOS transistor T3 is pulled low to a low level, so that the high level of the second word line WL2 turns on the third MOS transistor T3, i.e., the drain potential of the third MOS transistor T3 is pulled low to a low level, i.e., the second bit line BLT2 is a low level, and therefore, when the level of the second bit line BLT2 is determined to be a low level, it is known that the data stored in the latch structure is 1.

If the data originally stored in the latch structure is 0, the fourth MOS transistor T4 is turned off, so that the source of the third MOS transistor T3 is in an open circuit state; however, the high level of the second word line WL2 will pull the drain potential of the third MOS transistor T3 high, that is, the drain potential of the third MOS transistor T3 is between the high level and the low level, that is, the potential of the second bit line BLT2 is between the high level and the low level; therefore, when the level of the second bit line BLT2 is determined to be higher than the low level, the data stored in the latch structure is known to be 0.

Since the two MOS transistors in the inverter 02 are respectively connected to the operating power supply VDD and the common ground VSS in the 8T bit cell, the high level thereof is equal to the voltage value of the operating power supply VDD, and the low level thereof is equal to the voltage value of the common ground VSS.

It should be noted that in the 8T unit, the MOS transistors are all FDSOI-MOS transistors, so that leakage current during the operation of the MOS transistors can be reduced, and further, the influence of the leakage current on the operation of the MOS transistors can be reduced; and, since the FDSOI-MOS transistor has better uniformity of threshold voltage, timing convergence of the digital integrated circuit corresponding to the 8T bit cell is facilitated; in addition, the FDSOI-MOS transistor is provided with a body bias voltage connection pole VB, the body bias voltage connection pole VB can be connected with a common ground VSS or a working power supply VDD according to the difference between an N-type MOS transistor and a P-type MOS transistor, so that the 8T bit unit can also dynamically adjust the body bias voltage of each MOS transistor, and the operation speed can be effectively accelerated or the leakage current can be reduced.

Another embodiment of the present application provides another implementation manner of the second switch module 03, which is applicable to a case where the data transmission line 04 includes a second bit line BLT2 and a second bit bar BLC2, and the specific structure thereof is as shown in fig. 8, and specifically includes: a fifth MOS transistor T5, a sixth MOS transistor T6, a seventh MOS transistor T7, and an eighth MOS transistor T8.

In the bit cell of the second switch module 03 adopting the above embodiment, the gate of the fifth MOS transistor T5 is connected to the second word line WL2, the drain of the fifth MOS transistor T5 is connected to the second bit line BLT2, the source of the fifth MOS transistor T5 is connected to the drain of the sixth MOS transistor T6, the gate of the sixth MOS transistor T6 is connected to any connection point of the latch structure, and the source of the sixth MOS transistor T6 is connected to the common ground VSS; the gate of the seventh MOS transistor T7 is connected to the second word line WL2, the drain of the seventh MOS transistor T7 is connected to the second bit bar line BLC2, the source of the seventh MOS transistor T7 is connected to the drain of the eighth MOS transistor T8, the gate of the eighth MOS transistor T8 is connected to another connection point of the latch structure, and the source of the eighth MOS transistor T8 is connected to the common ground VSS.

In practical applications, including but not limited to the foregoing embodiments, the fifth MOS transistor T5, the sixth MOS transistor T6, the seventh MOS transistor T7, and the eighth MOS transistor T8 are all NMOS transistors, and are not particularly limited herein, and all of them are within the protection scope of the present application as the case may be.

The above is only one embodiment of the second switch module 03, and in practical applications, including but not limited to the above embodiments, the embodiments are not specifically limited herein, and may be within the protection scope of the present application as the case may be.

In the bit cell in which the second switch module 03 adopts the above-described embodiment, the two inverters 02 include four MOS transistors in total, the first switch module 01 includes two MOS transistors, and the second switch module 03 includes four MOS transistors and ten MOS transistors in total, so that the bit cell is also referred to as a 10T bit cell.

As shown in fig. 8, in the 10T bit cell, ten MOS transistors are FDSOI-MOS transistors, where VB of the fifth MOS transistor T5, the sixth MOS transistor T6, the seventh MOS transistor T7, and the eighth MOS transistor T8 in fig. 8 is a body bias connection pole of the FDSOI-MOS transistor.

The writing process of the 10T bit unit is the same as the writing process of the 8T bit unit, and is not repeated here, and reference may be made to the description in the previous embodiment.

The reading process of the 10T bit unit is as follows:

the second word line WL2 is selected, i.e. the second word line WL2 is set to high level, if the data originally stored in the latch structure is 1, i.e. the potential of the connection point between the latch structure and the sixth MOS transistor T6 is high level, and the potential of the connection point between the latch structure and the eighth MOS transistor T8 is low level, the sixth MOS transistor T6 is turned on, and the eighth MOS transistor T8 is turned off; after the sixth MOS transistor T6 is turned on, the source of the fifth MOS transistor T5 is connected to the common ground VSS, that is, the source potential of the fifth MOS transistor T5 is pulled low to a low level, so that the high level of the second word line WL2 turns on the fifth MOS transistor T5, that is, the drain potential of the fifth MOS transistor T5 is pulled low to a low level, that is, the second bit line BLT2 is at a low level; after the eighth MOS transistor T8 is turned off, the source of the seventh MOS transistor T7 is in an off state; however, the high level of the second word line WL2 will pull the drain potential of the seventh MOS transistor T7 high, that is, the drain potential of the seventh MOS transistor T7 is between the high level and the low level, that is, the potential of the second bar bit line BLC2 is between the high level and the low level; therefore, when the potential of the second bar line BLC2 is higher than the potential of the second bit line BLT2, it is determined that the data stored in the latch structure is 1.

If the data in the original latch structure is 0, the above procedure is reversed, and the above procedure is referred to, and will not be described herein again.

Since the two MOS transistors in the inverter 02 are respectively connected to the operating power supply VDD and the common ground VSS in the 10T bit cell, the high level thereof is equal to the voltage value of the operating power supply VDD, and the low level thereof is equal to the voltage value of the common ground VSS.

It should be noted that in the 10T unit, the MOS transistors are all FDSOI-MOS transistors, so that leakage current during the operation of the MOS transistors can be reduced, and further, the influence of the leakage current on the operation of the MOS transistors can be reduced; and, since the FDSOI-MOS transistor has better uniformity of threshold voltage, timing convergence of the digital integrated circuit corresponding to the 10T bit cell is facilitated; in addition, the FDSOI-MOS transistor has a body bias voltage connection pole VB, the body bias voltage connection pole VB can be connected with a common ground VSS or a working power supply VDD according to the difference between the N-type MOS transistor and the P-type MOS transistor, so that the 10T bit unit can also dynamically adjust the body bias voltage of each MOS transistor, and the operation speed can be effectively accelerated or the leakage current can be reduced.

Another embodiment of the present application provides a data parsing unit, which can refer to fig. 9-11, including: the data parsing module 04 and the bit unit provided in the above embodiments.

When the bit cell only includes the first switch module 01, as shown in fig. 9, two input terminals of the data parsing module 04 are respectively connected to the first bit line BLT1 and the first bit bar BLC1 of the bit cell, an output terminal of the data parsing module 04 is used as an output terminal of the data parsing unit, and the data stored in the bit cell can be obtained after the data parsing module 04 parses voltages of the first bit line BLT1 and the first bit bar BLC 1.

Specifically, when the data analysis module 04 determines that the potential of the first bit line BLT1 is greater than the potential of the first inverted bit line BLC1, the data stored in the bit cell may be determined to be 1, and conversely, the data stored in the bit cell may be determined to be 0.

When the bit cell further includes the second switch module 03, if the second switch module 03 includes two MOS transistors, as shown in fig. 10, one input terminal of the data analysis module 04 receives the reference voltage VREF, the other input terminal is connected to the second bit line BLT2, the output terminal of the data analysis module 04 is used as the output terminal of the data analysis unit, and the data stored in the bit cell can be obtained after the data analysis module 04 analyzes the voltage of the second bit line BLT 2. The reference voltage VREF is a voltage value of the common ground VSS.

Specifically, the data analysis module 04 may determine that the data stored in the bit cell is 1 when the potential of the second bit line BLT2 is equal to the reference voltage VREF, and the data analysis module 04 may determine that the data stored in the bit cell is 0 when the potential of the second bit line BLT2 is greater than the reference voltage VREF.

If the second switch module 03 includes four MOS transistors, as shown in fig. 11, two input terminals of the data analysis module 04 are respectively connected to the second bit line BLT2 and the second bit bar BLC2, an output terminal of the data analysis module 04 is used as an output terminal of the data analysis unit, and the data analysis module 04 analyzes the voltages of the second bit line BLT2 and the second bit bar BLC2, so as to obtain the data stored in the bit cell.

Specifically, when the data analysis module 04 determines that the potential of the second bar bit line BLC2 is higher than the potential of the second bit line BLT2, the data stored in the bit cell may be determined to be 1, and conversely, the data stored in the bit cell may be determined to be 0.

In this embodiment, the data analysis module 04 may be a sense amplifier 05, wherein two input terminals of the sense amplifier 05 serve as two input terminals of the data analysis module 04, and an output terminal serves as an output terminal of the data analysis module 04.

The above is only one preferred embodiment of the data parsing module 04, and in practical applications, including but not limited to this embodiment, it is within the scope of the present application as the case may be.

In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. The foregoing is merely a preferred embodiment of the utility model and is not intended to limit the utility model in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A bit cell, comprising: a first switch module and two inverters; wherein:

the two inverters are connected end to form a latch structure, and the latch structure is respectively connected with a first bit line and a first bit bar line through the first switch module; the first switch module is controlled by a first word line;

the inverter and the first switch module both comprise MOS (metal oxide semiconductor) tubes, and at least one MOS tube is an FDSOI-MOS tube.

2. The bit cell of claim 1, wherein the FDSOI-MOS transistor is further configured with: a body-biased connecting pole; the body bias voltage connection is connected to a voltage generator.

3. The bitcell of claim 2, wherein the body bias connection receives a positive or negative voltage to form a forward or reverse bias.

4. The bit cell of claim 1, wherein the first switching module comprises: the MOS transistor comprises a first MOS transistor and a second MOS transistor; wherein:

the first MOS tube and the second MOS tube are both NMOS tubes;

the grid electrode of the first MOS tube is connected with the first word line, the source electrode of the first MOS tube is connected with any one connection point of the latch structure, and the drain electrode of the first MOS tube is connected with the first bit line;

the grid electrode of the second MOS tube is connected with the first word line, the source electrode of the second MOS tube is connected with the other connection point of the latch structure, and the drain electrode of the second MOS tube is connected with the first bit line.

5. The bit cell of any one of claims 1-4, further comprising: a second switch module; wherein:

the latch structure is connected with the data transmission line through the second switch module;

the second switch module is controlled by a second word line.

6. The bit cell of claim 5, wherein if the data transmission line comprises a second bit line, the second switch module comprises: a third MOS transistor and a fourth MOS transistor; wherein:

the third MOS tube and the fourth MOS tube are both NMOS tubes;

the grid electrode of the third MOS tube is connected with the second word line, the drain electrode of the third MOS tube is connected with the second bit line, the source electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, the grid electrode of the fourth MOS tube is connected with any connection point of the latch structure, and the source electrode of the fourth MOS tube is connected with the public ground.

7. The bit cell of claim 5, wherein if the data transmission line comprises a second bit line and a second bit bar line, the second switching module comprises: a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube; wherein

The fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are all NMOS transistors;

the grid electrode of the fifth MOS tube is connected with the second word line, the drain electrode of the fifth MOS tube is connected with the second bit line, the source electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube, the grid electrode of the sixth MOS tube is connected with any connection point of the latch structure, and the source electrode of the sixth MOS tube is connected with the common ground;

the grid electrode of the seventh MOS tube is connected with the second word line, the drain electrode of the seventh MOS tube is connected with the second bit line, the source electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube, the grid electrode of the eighth MOS tube is connected with the other connection point of the latch structure, and the source electrode of the eighth MOS tube is connected with the public ground.

8. Bit cell according to any of claims 1 to 4, wherein the inverter comprises: a ninth MOS transistor and a tenth MOS transistor; wherein:

the ninth MOS transistor is a PMOS transistor, and the tenth MOS transistor is an NMOS transistor;

the ninth MOS tube and the tenth MOS tube are connected in a common grid mode, and a connection point is used as an input end of the inverter;

the ninth MOS tube and the tenth MOS tube are connected with a common drain electrode, and a connection point is used as an output end of the inverter;

and the source electrode of the ninth MOS tube is connected with a working power supply, and the source electrode of the tenth MOS tube is connected with the public ground.

9. A data parsing unit, comprising: a data parsing module and a bit unit as claimed in any one of claims 1 to 8; wherein:

when the bit unit only comprises a first switch module, two input ends of the data analysis module are respectively connected with a first bit line and a first bit bar line of the bit unit;

when the bit unit further comprises a second switch module, if the second switch module comprises two MOS, one input end of the data analysis module receives a reference voltage, and the other input end is connected with a second bit line;

when the bit unit further comprises a second switch module, if the second switch module comprises four MOS transistors, two input ends of the data analysis module are respectively connected with the second bit line and the second bit bar line;

the output end of the data analysis module outputs the stored data of the bit unit; the stored data is obtained by analyzing the voltage of the corresponding bit line by the data analysis module.

10. The data parsing unit of claim 9, wherein the data parsing module is a sense amplifier; wherein:

two input ends of the sensing amplifier are used as two input ends of the data analysis module, and an output end of the sensing amplifier is used as an output end of the data analysis module.

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