CN111613262B - Novel static memory cell - Google Patents

Novel static memory cell Download PDF

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Publication number
CN111613262B
CN111613262B CN202010324686.5A CN202010324686A CN111613262B CN 111613262 B CN111613262 B CN 111613262B CN 202010324686 A CN202010324686 A CN 202010324686A CN 111613262 B CN111613262 B CN 111613262B
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transistor
novel static
memory cell
terminal
static memory
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CN202010324686.5A
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CN111613262A (en
Inventor
陈静
吕迎欢
王硕
葛浩
谢甜甜
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Shanghai Huali Microelectronics Corp
Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Huali Microelectronics Corp
Shanghai Institute of Microsystem and Information Technology of CAS
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The embodiment of the application provides a novel static storage unit which is a novel static storage unit with a specific function and is obtained through a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and the electrical connection of the eight transistors. Compared with the original memory cell, the novel static memory cell obtained by combining the added first transistor, the added second transistor and other 6 transistors adopts the FDSOI process, can inhibit the body effect under the condition of not increasing the area, and has the advantages of low power consumption and high performance; in addition, the novel static storage unit can not only improve the single event effect resistance, but also increase the stability of stored data.

Description

Novel static memory cell
Technical Field
The invention relates to the field of integrated circuits, in particular to a novel static memory unit.
Background
Generally, in a computer system, a Random Access Memory (DRAM) and a Static RAM (SRAM) are commonly used, and the difference between the DRAM and the SRAM is that the DRAM needs to be refreshed by a Memory control circuit according to a certain period to maintain data storage, and the SRAM can also store internally stored data without a refresh circuit during the operation of the computer system. Therefore, the SRAM is widely used because of its good performance.
There exists in the prior art a conventional memory cell as shown in fig. 1, fig. 1 beingA circuit diagram of a six-transistor static memory cell includes a first transistor T 1 A second transistor T 2 A third transistor T 3 A fourth transistor T 4 A fifth transistor T 5 And a sixth transistor T 6 Wherein, T 1 And T 3 Form an inverter, T 2 And T 4 Forming an inverter, two inverters being connected to form a latch, T 5 And T 6 And the data is selectively read, written and stored through the pipe. Although the existing six-tube static storage unit can store data, the single event effect resistance of the six-tube static storage unit is weak, and when the six-tube static storage unit is applied to special fields such as aerospace, single event effect caused by irradiation can cause errors of stored data, and further great loss can be caused, so that single event strengthening resistance is inevitable.
Disclosure of Invention
The invention provides a novel static storage unit, which can improve the single event effect resistance of the novel static storage unit and enhance the stability of the novel static storage unit.
The embodiment of the application provides a novel static memory cell, and this novel static memory cell includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
the first end of the first transistor is connected with the first end of the second transistor, the second end of the first transistor is connected with the first end of the third transistor, and the third end of the first transistor is connected with the first end of the fifth transistor;
the second end of the second transistor is connected with the first end of the fourth transistor, and the third end of the second transistor is connected with the first end of the sixth transistor;
the third end of the third transistor is connected with the second end of the fifth transistor and the third end of the second transistor;
the third end of the fourth transistor is connected with the second end of the sixth transistor and the third end of the first transistor;
the first end of the seventh transistor is connected with the third end of the third transistor;
and the first end of the eighth transistor is connected with the third end of the fourth transistor.
Further, the unit further comprises: a word line, a first bit line and a second bit line;
the first end of the first transistor is connected with the word line, the first end of the second transistor is connected with the word line, the second end of the seventh transistor is connected with the word line, and the second end of the eighth transistor is connected with the word line;
a third end of the seventh transistor is connected with the first bit line;
and the third end of the eighth transistor is connected with the second bit line.
Further, a second end of the third transistor is connected with a power supply in a pull mode; the second terminal of the fourth transistor is connected with a power supply in a pulling mode.
Further, a third terminal of the fifth transistor is grounded; and the third end of the sixth transistor is grounded.
Further, the first transistor and the second transistor are both N-type field effect transistors.
Further, the third transistor and the fourth transistor are both P-type field effect transistors.
Further, the fifth transistor and the sixth transistor are both N-type field effect transistors.
Further, the seventh transistor and the eighth transistor are both N-type field effect transistors, and the seventh transistor and the eighth transistor are both gate tubes.
The embodiment of the invention has the following beneficial effects:
the invention discloses a novel static storage unit, which comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein the first end of the first transistor is connected with the first end of the second transistor, the second end of the first transistor is connected with the first end of the third transistor, the third end of the first transistor is connected with the first end of the fifth transistor, the second end of the second transistor is connected with the first end of the fourth transistor, the third end of the second transistor is connected with the first end of the sixth transistor, the third end of the third transistor is connected with the second end of the fifth transistor and the third end of the second transistor, the third end of the fourth transistor is connected with the second end of the sixth transistor and the third end of the first transistor, the first end of the seventh transistor is connected with the third end of the third transistor, and the first end of the eighth transistor is connected with the third end of the fourth transistor. The novel static memory unit is a novel static memory unit with a specific function, which is obtained by electrically connecting a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and the eight transistors. Compared with the original memory cell, the novel static memory cell obtained by combining the added first transistor, the added second transistor and other 6 transistors adopts the FDSOI process, can inhibit the body effect under the condition of not increasing the area, and has the advantages of low power consumption and high performance; in addition, the novel static storage unit can not only improve the single event effect resistance, but also increase the stability of stored data.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic circuit diagram of a six-transistor static novel static memory cell according to an embodiment of the present application;
fig. 2 is a circuit diagram of a novel static memory cell according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings. It should be apparent that the described embodiment is only one embodiment of the embodiments of the application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that "embodiment" as referred to herein refers to a particular feature, structure, or characteristic that may be included in at least one implementation of an embodiment of the present application. In the description of the embodiments of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or implying any indication of the number of technical features indicated, whereby the features defined as "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" may explicitly or implicitly include one or more of such features. Also, the terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," and "eighth" are used for distinguishing between similar elements and not for describing a particular sequential or chronological order, and it is to be understood that such usage data may be interchanged where appropriate. Furthermore, the terms "comprises" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a list of elements does not necessarily limit the order in which they are listed, but may include elements not expressly listed or inherent to such elements.
Referring to fig. 2, a circuit diagram of a novel static memory cell provided in an embodiment of the present application is shown, where the circuit diagram includes: first transistor 1, second transistor 2, third transistor 3, fourth transistor 4, fifth transistor 5, sixth transistor 6, seventh transistor 7, and eighth transistor 8, first terminal 11 of first transistor 1 is connected to first terminal 21 of second transistor 2, second terminal 12 of first transistor 1 is connected to first terminal 31 of third transistor 3, third terminal 13 of first transistor 1 is connected to first terminal 51 of fifth transistor 5, second terminal 22 of second transistor 2 is connected to first terminal 41 of fourth transistor 4, third terminal 23 of second transistor 2 is connected to first terminal 61 of sixth transistor 6, second terminal 32 of third transistor 3 is connected to a power supply, third terminal 33 of third transistor 3 is connected to second terminal 52 of fifth transistor 5, and to third terminal 23 of second transistor 2, second terminal 42 of fourth transistor 4 is connected to a power supply, third terminal 43 of fourth transistor 4 is connected to third terminal 62 of sixth transistor 6, and third terminal 13 of first transistor 1, third terminal 13 of fifth transistor 5 is connected to third terminal 23 of second transistor 2, third terminal 43 of fourth transistor 4 is connected to third terminal 71, seventh transistor 7 is connected to third terminal 81 of sixth transistor 3, third terminal 43 of third transistor 4 is connected to third terminal 62, and to third terminal 13 of first transistor 1, and seventh transistor 7 is connected to third terminal 81.
In the embodiment of the present application, the novel static memory cell further includes a word line WL, a first bit line BL, and a second bit line BLB. The first terminal 11 of the first transistor 1 is connected to the word line WL, the first terminal 21 of the second transistor 2 is connected to the word line WL, the second terminal 72 of the seventh transistor 7 is connected to the word line WL, the second terminal 82 of the eighth transistor 8 is connected to the word line WL, the third terminal 73 of the seventh transistor 7 is connected to the first bit line BL, and the third terminal 83 of the eighth transistor 8 is connected to the second bit line BLB.
In the embodiment of the present application, the first transistor 1 and the second transistor 2 are both N-type field effect transistors, the third transistor 3 and the fourth transistor 4 are both P-type field effect transistors, the fifth transistor 5 and the sixth transistor 6 are both N-type field effect transistors, the seventh transistor 7 and the eighth transistor 8 are both N-type field effect transistors, and the seventh transistor 7 and the eighth transistor are both gate transistors, so as to implement data storage.
By adopting the novel static storage unit provided by the embodiment of the application, the novel static storage unit with the specific function is obtained by electrically connecting the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor. Compared with the original memory cell, the novel static memory cell obtained by combining the added first transistor, the added second transistor and other 6 transistors adopts the FDSOI process, can inhibit the body effect under the condition of not increasing the area, and has the advantages of low power consumption and high performance; in addition, the novel static storage unit can not only improve the single event effect resistance, but also increase the stability of stored data.
Several embodiments of the operating states of the novel static memory cell are described below based on the novel static memory cell shown in fig. 2. Presetting a novel static memory cell in a holding state, namely a word line WL is in a '0' state, bombarding transistors in the novel static memory cell through high-energy particles, forming two inverters by a third transistor 3, a fourth transistor 4, a fifth transistor 5 and a sixth transistor, wherein a sensitive node in the novel static memory cell is a drain terminal of four transistors in the two inverters, and the drain terminals of two transistors can cause inversion under a storage condition. Assume that point Q is high and point QB is low. At this time, the sensitive node is a reverse-biased junction of the drains of the fifth transistor 5 and the second transistor 2.
In an optional implementation manner, high-energy particles bombard the fifth transistor 5, the fifth transistor 5 generates a transient current to pull down the voltage of the point Q, because the second transistor 2 is in an off state, which can be regarded as a resistor with a very large resistance, the voltage of the point Q2 is slowly reduced, and the voltage of the point QB is slowly increased, so that the delay of the feedback loop can be increased, and meanwhile, because the first transistor 1 is also in an off state, the point QB2 maintains an original low voltage, the third transistor 3 is turned on, thereby realizing the charging of the point Q, and further greatly improving the anti-overturning capability of the novel static storage unit 1 to 0.
In another optional implementation mode, high-energy particles bombard the fourth transistor 4, the fourth transistor 4 generates transient current to raise the potential of the QB point, and then the fifth transistor 5 is turned on and performs discharge operation on the Q point, and since the second transistor 2 is in an off state, the transistor can be regarded as a resistor with a very large resistance value, so that the voltage of the Q2 point is slowly reduced, the delay of a feedback loop can be increased, and the turning capability of the novel static memory cell 0 to 1 can be improved.
As can be seen from the above embodiments of the novel static memory cell provided in the present application, the novel static memory cell in the present application includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, a first end of the first transistor is connected to a first end of the second transistor, a second end of the first transistor is connected to a first end of the third transistor, a third end of the first transistor is connected to a first end of the fifth transistor, a second end of the second transistor is connected to a first end of the fourth transistor, a third end of the second transistor is connected to a first end of the sixth transistor, a third end of the third transistor is connected to a second end of the fifth transistor and to a third end of the second transistor, a third end of the fourth transistor is connected to a second end of the sixth transistor and to a third end of the first transistor, a first end 71 of the seventh transistor 7 is connected to a third end 33 of the third transistor 3, and a first end 81 of the eighth transistor 8 is connected to a third end 43 of the fourth transistor 4. The novel static memory unit is a novel static memory unit with a specific function, which is obtained by electrically connecting a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and the eight transistors. Compared with the original memory cell, the novel static memory cell obtained by combining the added first transistor, the added second transistor and other 6 transistors adopts the FDSOI process, can inhibit the body effect under the condition of not increasing the area, and has the advantages of low power consumption and high performance; in addition, the novel static storage unit can not only improve the single event effect resistance, but also increase the stability of stored data.
It should be noted that: the foregoing descriptions of the embodiments of the present application are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking parallel processing may also be implemented.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.
Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing associated hardware, and the program may be stored in a computer readable medium.
While the foregoing is directed to the preferred embodiment of the present application, it will be appreciated by those skilled in the art that various changes and modifications may be made therein without departing from the principles of the embodiments of the present application, and it is intended that such changes and modifications be considered as within the scope of the embodiments of the present application.

Claims (8)

1. A novel static memory cell, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
a first end of the first transistor is connected with a first end of the second transistor, a second end of the first transistor is connected with a first end of the third transistor, and a third end of the first transistor is connected with a first end of the fifth transistor;
a second end of the second transistor is connected with a first end of the fourth transistor, and a third end of the second transistor is connected with a first end of the sixth transistor;
the third end of the third transistor is connected with the second end of the fifth transistor and the third end of the second transistor;
the third end of the fourth transistor is connected with the second end of the sixth transistor and the third end of the first transistor;
a first end of the seventh transistor is connected with a third end of the third transistor;
and the first end of the eighth transistor is connected with the third end of the fourth transistor.
2. The unit of claim 1, further comprising: a word line, a first bit line and a second bit line;
a first end of the first transistor is connected with the word line, a first end of the second transistor is connected with the word line, a second end of the seventh transistor is connected with the word line, and a second end of the eighth transistor is connected with the word line;
a third end of the seventh transistor is connected with the first bit line;
and the third end of the eighth transistor is connected with the second bit line.
3. The cell of claim 1, wherein a power supply is pulled on a second terminal of the third transistor;
and the second end of the fourth transistor is connected with a power supply in a pulling mode.
4. The cell of claim 1, wherein a third terminal of the fifth transistor is grounded;
and the third end of the sixth transistor is grounded.
5. The cell defined by claim 1 wherein the first transistor and the second transistor are both N-type field effect transistors.
6. The cell of claim 1, wherein the third transistor and the fourth transistor are both P-type field effect transistors.
7. The cell defined by claim 1 wherein the fifth and sixth transistors are both N-type field effect transistors.
8. The cell of claim 1, wherein the seventh transistor and the eighth transistor are both N-type field effect transistors;
the seventh transistor and the eighth transistor are both gate tubes.
CN202010324686.5A 2020-04-22 2020-04-22 Novel static memory cell Active CN111613262B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5040146A (en) * 1989-04-21 1991-08-13 Siemens Aktiengesellschaft Static memory cell
US9001571B1 (en) * 2014-01-20 2015-04-07 National Tsing Hua University 6T static random access memory cell, array and memory thereof
CN105575421B (en) * 2014-10-13 2018-09-18 中芯国际集成电路制造(上海)有限公司 Static RAM

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