CN111045643B - Multiplication unit circuit using threshold voltage characteristic and multiplier - Google Patents

Multiplication unit circuit using threshold voltage characteristic and multiplier Download PDF

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CN111045643B
CN111045643B CN201911134935.8A CN201911134935A CN111045643B CN 111045643 B CN111045643 B CN 111045643B CN 201911134935 A CN201911134935 A CN 201911134935A CN 111045643 B CN111045643 B CN 111045643B
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nmos transistor
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tube
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CN111045643A (en
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吴秋丰
张跃军
李憬
张会红
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Ningbo University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

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Abstract

The invention discloses a multiplication unit circuit and a multiplier utilizing threshold voltage characteristics, wherein the multiplication unit circuit is composed of two exclusive-OR gates, four NAND gates and four inverters, the multiplier is composed of a plurality of multiplication unit circuits, the exclusive-OR gates and the NAND gates are used as two basic units of the multiplication unit circuit, the exclusive-OR gates and the NAND gates are realized by adopting the same circuit structure, the circuit structure can respectively realize an exclusive-OR logic function and a NAND logic function when the threshold voltage characteristics of MOS (metal oxide semiconductor) tubes in the same circuit structure are configured, the multiplication unit circuit realizes one-time evaluation operation in one period, the multiplication unit circuit is divided into three stages in one period, the three stages are respectively a pre-charging stage, an evaluation operation stage and a discharging stage, and differential pull-down networks of the exclusive-OR gates and the NAND gates adopt a single-ended structure; the method has the advantages of small area and power consumption overhead, capability of simultaneously defending reverse engineering and DPA attack, and high safety.

Description

Multiplication unit circuit and multiplier utilizing threshold voltage characteristics
Technical Field
The present invention relates to a multiplier cell circuit, and more particularly, to a multiplier cell circuit and a multiplier using threshold voltage characteristics.
Background
With the development of very large scale integrated circuits and information security technologies, protection of Intellectual Property (IP) is receiving more and more attention. Meanwhile, the attack mode developed for the chip IP core is also infinite. Reverse engineering is one of the ways that attackers currently have a quick mastery of the chip core technology of designers. An attacker analyzes the internal structure of the chip through reverse engineering, extracts the circuit netlist, masters the actual functions of the chip, seriously influences the legal interests of the designer, and seriously infringes the intellectual property of the designer through actions such as chip cloning. For an encryption chip, an attacker bypasses a cryptographic algorithm, collects physical information leaked out in different round function encryption processes, and uses a statistical method to estimate a secret key, and the attack mode is called a side channel attack, wherein Differential Power Analysis (DPA) is an efficient and practical attack mode in the side channel attack, and defense against DPA attack also becomes a hotspot studied at present. Therefore, the cipher device resisting reverse engineering and DPA has wide application prospect.
Addition is the most common operation, and theoretically, multiplication, subtraction and division can be converted into addition. The multiplier is a main component constituting an arithmetic operator, and is widely applied to processing data of different word lengths in various digital encryption systems. In the aspect of multiplier implementation, a multiplier implemented based on adiabatic dynamic differential logic has certain defects in safety, is easily attacked by reverse engineering and DPA, is complex in time sequence control, needs to design a complex interface circuit when interacting with a CMOS circuit, and is complex in circuit structure and large in area and power consumption overhead; although the multiplier realized by the differential logic based on the lookup table has good DPA attack resistance, reverse engineering cannot defend, a large number of transistors are needed, and the area and power consumption overhead are also large; multiplier output load capacitances based on sensitive amplification type logic implementations are not exactly uniform and still may serve as a breakthrough point for reverse engineering and DPA attacks.
Disclosure of Invention
One of the technical problems to be solved by the invention is to provide a multiplication unit circuit which has smaller area and power consumption expenditure, can simultaneously defend reverse engineering and DPA (differential power amplifier) attack and has higher safety and utilizes the threshold voltage characteristic.
The technical scheme adopted by the invention for solving one of the technical problems is as follows: a multiplication unit circuit utilizing threshold voltage characteristics comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, wherein each two-input NAND gate is respectively provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end; each of the two-input exclusive-OR gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS, a source of the eighth PMOS, a source of the ninth PMOS, and a gate of the fourteenth are all connected to a power supply of the fourteenth transistor, the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connection end of the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input XOR gate, the drain electrode of the first PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, the connecting end of the third PMOS tube is the inverted output end of the two-input exclusive-OR gate, and the grid electrode of the fourth PMOS tube, the grid electrode of the seventh NMOS transistor, the grid electrode of the seventh PMOS transistor, the grid electrode of the eighth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input xor gate, the grid electrode of the fifth PMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the sixth PMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the seventh PMOS transistor, the drain electrode of the fifth NMOS transistor, the grid electrode of the eighth PMOS transistor and the grid electrode of the sixth NMOS transistor are connected, the drain electrode of the eighth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input xor gate, the source electrode of the first NMOS transistor is grounded, the source electrode of the second NMOS transistor and the drain electrode of the seventh NMOS transistor are connected, the source electrode of the seventh NMOS transistor is grounded, the source electrode of the third NMOS transistor and the drain electrode of the ninth NMOS transistor are connected, the source of the fourth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor, the drain of the twelfth NMOS transistor, the drain of the thirteenth NMOS transistor, the source of the fifth NMOS transistor and the drain of the eighth NMOS transistor are connected, the source of the eighth NMOS transistor is connected to ground, the source of the sixth NMOS transistor is connected to ground, the source of the ninth NMOS transistor and the drain of the fourteenth NMOS transistor are connected, the source of the tenth NMOS transistor and the drain of the fifteenth NMOS transistor are connected, the gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected at the first inverting input terminal of the two-input xor gate, the source of the eleventh NMOS transistor and the drain of the sixteenth NMOS transistor are connected, the gate of the eleventh NMOS transistor and the gate of the thirteenth NMOS transistor are connected at the second inverting input terminal of the two-input xor gate A first input end of an exclusive-or gate, a source electrode of the twelfth NMOS transistor is connected with a drain electrode of the seventeenth NMOS transistor, a source electrode of the thirteenth NMOS transistor is connected with a drain electrode of the eighteenth NMOS transistor, a source electrode of the fourteenth NMOS transistor, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor, a source electrode of the seventeenth NMOS transistor, a source electrode of the eighteenth NMOS transistor and a drain electrode of the nineteenth NMOS transistor are connected, a source electrode of the nineteenth NMOS transistor is grounded, a gate electrode of the fifteenth NMOS transistor is connected with a gate electrode of the sixteenth NMOS transistor and a connection end thereof is a second inverting input end of the two-input exclusive-or gate, a gate electrode of the seventeenth NMOS transistor is connected with a gate electrode of the eighteenth NMOS transistor and a connection end thereof is a second input end of the two-input exclusive-or gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold voltage transistors, a threshold voltage of the fourteenth NMOS transistor is 0.243, a voltage of the seventeenth NMOS transistor and a voltage of the nineteenth NMOS transistor is a sub-threshold voltage, a sub-threshold voltage of the nineteenth NMOS transistor is a sub-threshold voltage of the NMOS transistor, a sub-threshold voltage of the seventeenth NMOS transistor and a sub-threshold voltage of the NMOS transistor is 0.489; each of the two-input NAND gates respectively comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-eleventh NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube and an eighth NMOS tube, wherein the source electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube, the source electrode of the eleventh PMOS tube, the source electrode NMOS gate of the twelfth PMOS tube, the fifteenth tube, the source electrode of the sixteenth PMOS tube, the sixteenth NMOS and the eighth gate of the twentieth NMOS tube are all connected to the gate of the NMOS tubes, the grid electrode of the ninth PMOS transistor, the grid electrode of the tenth PMOS transistor, the grid electrode of the twenty-first NMOS transistor and the grid electrode of the twenty-fourth NMOS transistor are connected, the connection end of the grid electrode of the twenty-first PMOS transistor and the grid electrode of the twenty-fourth NMOS transistor is the first control end of the two-input nand gate, the drain electrode of the ninth PMOS transistor is connected with the source electrode of the thirteenth PMOS transistor, the drain electrode of the tenth PMOS transistor is connected with the source electrode of the fourteenth PMOS transistor, the grid electrode of the eleventh PMOS transistor, the grid electrode of the twentieth NMOS transistor, the drain electrode of the twelfth PMOS transistor, the drain electrode of the twenty-first NMOS transistor, the drain electrode of the thirteenth PMOS transistor, the drain electrode of the twenty-second NMOS transistor, the grid electrode of the fourteenth NMOS transistor and the grid electrode of the twenty-third NMOS transistor are connected, the drain of the eleventh PMOS transistor is connected to the drain of the twentieth NMOS transistor, and the connection end thereof is the inverted output end of the two-input nand gate, the gate of the twelfth PMOS transistor, the gate of the twenty-sixth NMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the twenty-seventh NMOS transistor and the gate of the thirty-eighth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input nand gate, the gate of the thirteenth PMOS transistor, the gate of the twenty-second NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the twenty-third NMOS transistor, the drain of the fifteenth PMOS transistor, the drain of the twenty-fourth NMOS transistor, the gate of the sixteenth PMOS transistor and the gate of the twenty-fifth NMOS transistor are connected, the drain of the sixteenth PMOS transistor and the drain of the twenty-fifth NMOS transistor are connected, and the connection end thereof is the output end of the two-input nand gate, the source electrode of the twenty-first NMOS transistor is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-fifth NMOS transistor, the drain electrode of the thirty-first NMOS transistor and the drain electrode of the thirty-second NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, and the source electrode of the twenty-eighth NMOS transistor is connected with the drain electrode of the thirty-third NMOS transistor, a source of the twenty ninth NMOS transistor is connected to a drain of the thirty fourth NMOS transistor, a gate of the twenty ninth NMOS transistor is connected to a gate of the thirty eleventh NMOS transistor, a connection end of the twenty ninth NMOS transistor is a first inverting input end of the two-input nand gate, a source of the thirty NMOS transistor is connected to a drain of the thirty fifth NMOS transistor, a gate of the thirty NMOS transistor is connected to a gate of the thirty second NMOS transistor, a connection end of the thirty second NMOS transistor is a first input end of the two-input nand gate, a source of the thirty eleventh NMOS transistor is connected to a drain of the thirty sixth NMOS transistor, a source of the thirty second NMOS transistor is connected to a drain of the thirty seventh NMOS transistor, a source of the thirty third NMOS transistor, a source of the thirty fourth NMOS transistor, a source of the thirty fifth NMOS transistor, a source of the thirty sixth NMOS transistor, a source of the thirty seventh NMOS transistor and a drain of the thirty eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor is connected to the gate of the thirty-fifth NMOS transistor, the connection end of the thirty-fourth NMOS transistor is the second inverting input end of the two-input nand gate, the gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, the connection end of the thirty-sixth NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are both high-threshold NMOS transistors, and the threshold voltage is 0.489V. The four two-input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two-input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first two-input nand gate is the first control end of the multiplication unit circuit and is used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the multiplication unit circuit is the multiplication unit circuit A second control terminal of the first two-input nand gate, a first inverting input terminal of the third two-input nand gate and a first inverting input terminal of the first two-input xor gate are connected, an inverting output terminal of the first two-input nand gate, a first input terminal of the third two-input xor gate and a first input terminal of the first two-input xor gate are connected, a second input terminal of the first two-input xor gate and a second input terminal of the third two-input nand gate and an input terminal of the third inverter are connected, a connection terminal of the first two-input xor gate and the second two-input xor gate is a third input terminal of the multiplication unit circuit and is used for connecting a third multiplier, a second inverting input terminal of the first two-input xor gate, a second inverting input terminal of the third two-input nand gate and an output terminal of the third inverter are connected, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal with low-order output, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting a product signal, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting an inverted signal of the product signal, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit and is used for outputting a carry signal to a high order, and the inverted output end of the carry signal of the multiplication unit circuit is used for outputting an inverted carry signal to a high order.
Compared with the prior art, the multiplication unit circuit has the advantages that the multiplication unit circuit is formed by two exclusive-OR gates, four NAND gates and four inverters, the multiplication unit circuit realizes one-time evaluation operation in one period, the multiplication unit circuit is divided into three stages in one period, namely a pre-charging stage, an evaluation operation stage and a discharging stage, the exclusive-OR gate and the NAND gate are used as two basic units of the multiplication unit circuit, the exclusive-OR gate and the NAND gate are realized by adopting the same circuit structure, the circuit structure can realize an exclusive-OR logic function and a NAND logic function when the threshold voltage characteristics of MOS (metal oxide semiconductor) tubes in the same circuit structure are configured, the exclusive-OR gate comprises a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube and an eighteenth NMOS tube, the differential pull-down network is formed by a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-eleventh NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube and a sixth NMOS tube, the differential pull-down network is formed by twenty-NMOS tubes, the differential pull-down network has the characteristics of being lower than that the reverse power consumption of the single-end of the reverse power consumption is lower than that the single-end of the differential pull-NMOS circuit structure, and the reverse power consumption is lower than that the single-end of the reverse-NMOS circuit structure is lower than that the reverse-end of the single-end of the double-NMOS circuit structure is lower than that the single-end of the reverse-end of the single-NMOS circuit structure is lower than that the reverse-end of the single-NMOS circuit.
The second technical problem to be solved by the invention is to provide a multiplier which has small area and power consumption overhead, can simultaneously defend reverse engineering and DPA attack, and has high safety and threshold voltage characteristic.
The second technical solution adopted by the present invention to solve the above technical problems is: a multiplier utilizing threshold voltage characteristics comprises mxn multiplication unit circuits, wherein the value of m is equal to the number of digits of a multiplicand, the value of n is equal to the number of digits of the multiplicand, the mxn multiplication unit circuits are arranged according to n rows and m columns, and each multiplication unit circuit is respectively provided with a first input end, a second input end, a third input end, a first control end, a second control end, a low-order carry signal input end, a high-order carry signal output end and a product output end; the first control terminals of the mxn multiplication unit circuits are connected together, the connection terminal of the M × N multiplication unit circuits is the first control terminal of the multiplier and is used for accessing a discharge control signal, the second control terminals of the mxn multiplication unit circuits are connected together, the connection terminal of the M × N multiplication unit circuits is the second control terminal of the multiplier and is used for accessing an evaluation control signal, the first input terminals of the M multiplication unit circuits in the Nth row are respectively accessed to the Nth bit data of the multiplier, N =1,2, \ 8230, N, the second input terminals of the N multiplication unit circuits in the Mth column are respectively accessed to the M- (M-1) th bit data of the multiplicand, M =1,2, \\ 8230, M, the third input terminals of the M multiplication unit circuits in the 1 st row are respectively accessed to a signal 0, the low-order carry signal input ends of N multiplication unit circuits positioned in the mth column are respectively connected with a signal 0, the high-order carry signal output ends of the multiplication unit circuits positioned in the nth row and the kth column are connected with the low-order carry signal input ends of the multiplication unit circuits positioned in the nth row and the kth column, K =2,3, \\ 8230;. M, the high-order carry signal output ends of the multiplication unit circuits positioned in the jth row and the 1 st column are connected with the third input ends of the multiplication unit circuits positioned in the jth +1 row and the 1 st column, j =1,2, \\ 8230;. N-1, the product output ends of the multiplication unit circuits positioned in the nth row and the kth column are connected with the third input ends of the multiplication unit circuits positioned in the nth row and the kth +1 column, K =1,2, \\ 8230, M-1, the product output end of the multiplication unit circuit positioned in the jth row and the mth column is the jth output end of the multiplier, the product output end of the multiplication unit circuit positioned in the Nth row and the Mth column is the (n-1 + M- (M-1) th output end of the multiplier, outputs the (n-1 + M- (M-1) th bit of the product, and the high carry signal output end of the multiplication unit circuit positioned in the Nth row and the 1 st column is the (n + M) th output end of the multiplier and outputs the (n + M) th bit of the product; each multiplication unit circuit comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, each two-input NOR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end, and each two-input exclusive-OR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end; each of the two input exclusive-or gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a gate of the ninth NMOS transistor, and a fourteenth NMOS transistor are all connected to a power supply, the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connecting end of the grid electrode of the second PMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input XOR gate, the drain electrode of the first PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube are connected, the connecting end of the third PMOS tube and the drain electrode of the first NMOS tube are the inverted output end of the two-input XOR gate, the grid electrode of the fourth PMOS tube and the grid electrode of the fifth NMOS tube are connected in a reverse phase, the gate of the seventh NMOS transistor, the gate of the seventh PMOS transistor, the gate of the eighth NMOS transistor, and the gate of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input xor gate, the gate of the fifth PMOS transistor, the gate of the third NMOS transistor, the drain of the sixth PMOS transistor, the drain of the fourth NMOS transistor, the drain of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the gate of the eighth PMOS transistor, and the gate of the sixth NMOS transistor are connected, the drain of the eighth PMOS transistor and the drain of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input xor gate, the source of the first NMOS transistor is grounded, the source of the second NMOS transistor and the drain of the seventh NMOS transistor are connected, the source of the seventh NMOS transistor is grounded, the source of the third NMOS transistor and the drain of the ninth NMOS transistor are connected, the source of the fourth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor, the drain of the twelfth NMOS transistor, the drain of the thirteenth NMOS transistor, the source of the fifth NMOS transistor and the drain of the eighth NMOS transistor, the source of the eighth NMOS transistor is grounded, the source of the sixth NMOS transistor is grounded, the source of the ninth NMOS transistor and the drain of the fourteenth NMOS transistor are connected, the source of the tenth NMOS transistor and the drain of the fifteenth NMOS transistor are connected, the gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected and the connection end is the first inverting input end of the two-input xor gate, the source of the eleventh NMOS transistor and the drain of the sixteenth NMOS transistor are connected, the gate of the eleventh NMOS transistor and the gate of the thirteenth NMOS transistor are connected and the connection end is the two-input xor gate A first input terminal of the exclusive-or gate, a source of the twelfth NMOS transistor is connected to a drain of the seventeenth NMOS transistor, a source of the thirteenth NMOS transistor is connected to a drain of the eighteenth NMOS transistor, a source of the fourteenth NMOS transistor, a source of the fifteenth NMOS transistor, a source of the sixteenth NMOS transistor, a source of the seventeenth NMOS transistor, a source of the eighteenth NMOS transistor and a drain of the nineteenth NMOS transistor are connected, a source of the nineteenth NMOS transistor is grounded, a gate of the fifteenth NMOS transistor is connected to a gate of the sixteenth NMOS transistor, and a connection terminal thereof is a second inverting input terminal of the two-input exclusive-or gate, the gate of the seventeenth NMOS transistor is connected to the gate of the eighteenth NMOS transistor, and the connection end of the seventeenth NMOS transistor is the second input end of the two-input xor gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold NMOS transistors with a threshold voltage of 0.243V, the ninth NMOS transistor and the fourteenth NMOS transistor are all sub-threshold transistors with a threshold voltage of 0.367V, the tenth NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor and the eighteenth NMOS transistor are all high-threshold NMOS transistors with a threshold voltage of 0.489V; each of the two-input NAND gates comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-eleventh NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube and a thirty-eighth NMOS tube respectively, wherein the source electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube, the source electrode of the eleventh PMOS tube, the source electrode of the twelfth PMOS tube, the source electrode of the fifteenth tube, the source electrode of the sixteenth PMOS tube, the twenty-eighth NMOS tube and the thirty-eighth NMOS tubes are all connected to the grid electrodes of the NMOS tubes, the grid electrode of the ninth PMOS transistor, the grid electrode of the tenth PMOS transistor, the grid electrode of the twenty-first NMOS transistor and the grid electrode of the twenty-fourth NMOS transistor are connected, the connection end of the grid electrode of the twenty-first PMOS transistor and the grid electrode of the twenty-fourth NMOS transistor is the first control end of the two-input nand gate, the drain electrode of the ninth PMOS transistor is connected with the source electrode of the thirteenth PMOS transistor, the drain electrode of the tenth PMOS transistor is connected with the source electrode of the fourteenth PMOS transistor, the grid electrode of the eleventh PMOS transistor, the grid electrode of the twentieth NMOS transistor, the drain electrode of the twelfth PMOS transistor, the drain electrode of the twenty-first NMOS transistor, the drain electrode of the thirteenth PMOS transistor, the drain electrode of the twenty-second NMOS transistor, the grid electrode of the fourteenth NMOS transistor and the grid electrode of the twenty-third NMOS transistor are connected, the drain of the eleventh PMOS transistor is connected to the drain of the twentieth NMOS transistor, and the connection end thereof is the inverted output end of the two-input nand gate, the gate of the twelfth PMOS transistor, the gate of the twenty-sixth NMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the twenty-seventh NMOS transistor and the gate of the thirty-eighth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input nand gate, the gate of the thirteenth PMOS transistor, the gate of the twenty-second NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the twenty-third NMOS transistor, the drain of the fifteenth PMOS transistor, the drain of the twenty-fourth NMOS transistor, the gate of the sixteenth PMOS transistor and the gate of the twenty-fifth NMOS transistor are connected, the drain of the sixteenth PMOS transistor and the drain of the twenty-fifth NMOS transistor are connected, and the connection end thereof is the output end of the two-input nand gate, the source electrode of the twenty-first NMOS transistor is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-fifth NMOS transistor, the drain electrode of the thirty-eleventh NMOS transistor is connected with the drain electrode of the thirty-second NMOS transistor, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, and the source electrode of the twenty-eighth NMOS transistor is connected with the drain electrode of the thirty-third NMOS transistor, the source of the twenty-ninth NMOS transistor is connected to the drain of the thirty-fourth NMOS transistor, the gate of the twenty-ninth NMOS transistor is connected to the gate of the thirty-eleventh NMOS transistor, and the connection end thereof is the first inverting input end of the two-input nand gate, the source of the thirty-ninth NMOS transistor is connected to the drain of the thirty-fifth NMOS transistor, the gate of the thirty-ninth NMOS transistor is connected to the gate of the thirty-second NMOS transistor, and the connection end thereof is the first input end of the two-input nand gate, the source of the thirty-eleventh NMOS transistor is connected to the drain of the thirty-sixth NMOS transistor, the source of the thirty-second NMOS transistor is connected to the drain of the thirty-seventh NMOS transistor, the source of the thirty-third NMOS transistor, the source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor and the drain of the thirty-eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor is connected to the gate of the thirty-fifth NMOS transistor, the connection end of the thirty-fourth NMOS transistor is the second inverting input end of the two-input nand gate, the gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, the connection end of the thirty-seventh NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are all high-threshold NMOS transistors, and the threshold voltage is 0.489V. The four second input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two second input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first two-input xor gate and the first control end of the second two-input xor gate is the first control end of the multiplication unit circuit and is used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the multiplication unit circuit is the multiplication unit circuit A second control terminal of the first two-input nand gate, a first inverting input terminal of the third two-input nand gate and a first inverting input terminal of the first two-input xor gate are connected, an inverting output terminal of the first two-input nand gate, a first input terminal of the third two-input nand gate and a first input terminal of the first two-input xor gate are connected, a second input terminal of the first two-input xor gate and a second input terminal of the third two-input nand gate and an input terminal of the third inverter are connected, a connection terminal of the first two-input xor gate and the second two-input nand gate is a third input terminal of the multiplication unit circuit and is used for connecting a third multiplier, a second inverting input terminal of the first two-input xor gate, a second inverting input terminal of the third two-input nand gate and an output terminal of the third inverter are connected, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal output at a low order, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting a product signal, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting an inverted signal of the product signal, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit and is used for outputting a carry signal to a high order, and the inverted output end of the carry signal of the multiplication unit circuit is used for outputting an inverted carry signal to a high order.
Compared with the prior art, the multiplier of the invention has the advantages that the integral framework is realized by adopting a grid-form laminated strip array structure, the structure is simple, the realization is easy, in addition, the regular layout structure can be realized, the realization is particularly suitable for VLSI realization, in addition, the multiplication unit circuit forming the multiplier of the invention realizes one evaluation operation in one period, and the multiplication unit circuit is divided into three stages in one period, namely a pre-charging stage, an evaluation operation stage and a discharging stage respectively, an XOR gate and an NAND gate are taken as two basic units of the multiplication unit circuit, the XOR gate and the NAND gate are realized by adopting the same circuit structure, when the threshold voltage characteristic of an MOS tube in the same circuit structure is configured, the circuit structure can respectively realize an XOR logic function and an NAND logic function, and the XOR gate is composed of the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube and the eighteenth NMOS tube, and the NAND gate is composed of the twenty eighth NMOS tube, the twenty ninth NMOS tube, the thirty eleventh NMOS tube, the thirty second NMOS tube, the thirty third NMOS tube, the thirty fourth NMOS tube, the thirty fifth NMOS tube, the thirty sixth NMOS tube and the thirty seventh NMOS tube, and the differential pull-down network is composed of the twenty eighth NMOS tube, the twenty ninth NMOS tube, the thirty eleventh NMOS tube, the thirty second NMOS tube, the thirty third NMOS tube, the thirty fourth NMOS tube, the thirty fifth NMOS tube, the thirty sixth NMOS tube and the thirty seventh NMOS tube, and has a single-ended structure.
Drawings
FIG. 1 is a block diagram of a multiplication unit circuit using threshold voltage characteristics according to the present invention;
FIG. 2 is a circuit diagram of an XOR gate of the multiplier unit circuit/multiplier using threshold voltage characteristics according to the present invention;
FIG. 3 is a circuit diagram of the NAND gate of the multiplier/multiplier circuit using the threshold voltage characteristic according to the present invention;
FIG. 4 is a block diagram of a multiplier utilizing threshold voltage characteristics according to the present invention;
FIG. 5 is a timing diagram illustrating the operation of the XOR gate of the multiplier unit/multiplier using the threshold voltage characteristic according to the present invention;
FIG. 6 is a graph of a functional simulation of an XOR gate of a multiplier cell circuit/multiplier utilizing threshold voltage characteristics according to the present invention;
FIG. 7 is a simulated graph of power consumption of the XOR gate of the multiplier cell circuit/multiplier using threshold voltage characteristics according to the present invention;
FIG. 8 is a graph of a functional simulation of the NAND gate of the multiplier unit circuit/multiplier using threshold voltage characteristics according to the present invention;
FIG. 9 is a functional verification diagram of the multiplier utilizing threshold voltage characteristics according to the present invention;
fig. 10 is a power consumption simulation graph of the multiplier using the threshold voltage characteristic of the present invention.
Detailed Description
The invention discloses a multiplication unit circuit utilizing threshold voltage characteristics, which is described in further detail below with reference to the embodiment of the attached drawings.
The embodiment is as follows: as shown in fig. 1,2 and3, a multiplication unit circuit using threshold voltage characteristics includes a first inverter F1, a second inverter F2, a third inverter F3, a fourth inverter F4, four two-input nand gates with the same structure and two-input xor gates with the same structure, each two-input nor gate has a first input terminal, a first inverting input terminal, a second inverting input terminal, a first control terminal, a second control terminal, an output terminal and an inverting output terminal, and each two-input xor gate has a first input terminal, a first inverting input terminal, a second inverting input terminal, a first control terminal, a second control terminal, an output terminal and an inverting output terminal; each two-input exclusive-or gate comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, a sixteenth NMOS tube N16, a seventeenth NMOS tube N17, an eighteenth NMOS tube N18 and a nineteenth NMOS tube N19, a source of the first PMOS tube P1, a source of the second PMOS tube P2, a source of the third PMOS tube P3, a fourteenth NMOS tube P4, a grid of the eighth NMOS tube P9, a fourteenth NMOS tube P14, the grid of the first PMOS pipe P1, the grid of the second PMOS pipe P2, the grid of the second NMOS pipe N2 and the grid of the fifth NMOS pipe N5 are connected, the connection end of the grid of the second PMOS pipe P1 and the grid of the fifth NMOS pipe N5 is the first control end of the two-input XOR gate, the drain of the first PMOS pipe P1 is connected with the source of the fifth PMOS pipe P5, the drain of the second PMOS pipe P2 is connected with the source of the sixth PMOS pipe P6, the grid of the third PMOS pipe P3, the grid of the first NMOS pipe N1, the drain of the fourth PMOS pipe P4, the drain of the second NMOS pipe N2, the drain of the fifth PMOS pipe P5, the drain of the third NMOS pipe N3, the grid of the sixth PMOS pipe P6 and the grid of the fourth NMOS pipe N4 are connected, the drain of the third PMOS pipe P3 and the drain of the first NMOS pipe N1 are connected, the connection end of the third PMOS pipe P3 and the drain of the first NMOS pipe N1 is the inverted output end of the two-input XOR gate, the grid of the fourth PMOS pipe P4, the grid of the seventh NMOS pipe N7, the seventh PMOS pipe P7, the eighth NMOS pipe P8 and the connection end of the ninth NMOS pipe N19 are connected with the control end of the second NMOS gate of the nineteenth XOR gate, a grid electrode of a fifth PMOS tube P5, a grid electrode of a third NMOS tube N3, a drain electrode of a sixth PMOS tube P6, a drain electrode of a fourth NMOS tube N4, a drain electrode of a seventh PMOS tube P7, a drain electrode of a fifth NMOS tube N5, a grid electrode of an eighth PMOS tube P8 and a grid electrode of a sixth NMOS tube N6 are connected, a drain electrode of an eighth PMOS tube P8 and a drain electrode of a sixth NMOS tube N6 are connected, a connecting end of the drain electrode of the eighth PMOS tube P8 and the drain electrode of the sixth NMOS tube N6 is an output end of a two-input XOR gate, a source electrode of a first NMOS tube N1 is grounded, a source electrode of a second NMOS tube N2 and a drain electrode of a seventh NMOS tube N7 are connected, a source electrode of a seventh NMOS tube N7 is grounded, a source electrode of a third NMOS tube N3 and a drain electrode of a ninth NMOS tube N9 are connected, a source electrode of a fourth NMOS tube N4, a drain electrode of a tenth NMOS tube N10, a drain electrode of an eleventh NMOS tube N11, a drain electrode of a twelfth NMOS tube N12 and a drain electrode of a thirteenth NMOS tube N13 are connected, a source electrode of a fifth NMOS tube N5 and a drain electrode of an eighth NMOS tube N8 are connected, a source electrode of the sixth NMOS transistor N6 is grounded, a source electrode of the ninth NMOS transistor N9 is connected to a drain electrode of the fourteenth NMOS transistor N14, a source electrode of the tenth NMOS transistor N10 is connected to a drain electrode of the fifteenth NMOS transistor N15, a gate electrode of the tenth NMOS transistor N10 is connected to a gate electrode of the twelfth NMOS transistor N12, and a connection end thereof is a first inverting input end of the two-input xor gate, a source electrode of the eleventh NMOS transistor N11 is connected to a drain electrode of the sixteenth NMOS transistor N16, a gate electrode of the eleventh NMOS transistor N11 is connected to a gate electrode of the thirteenth NMOS transistor N13, and a connection end thereof is a first input end of the two-input xor gate, a source electrode of the twelfth NMOS transistor N12 is connected to a drain electrode of the seventeenth NMOS transistor N17, a source electrode of the thirteenth NMOS transistor N13 is connected to a drain electrode of the eighteenth NMOS transistor N18, a source electrode of the fourteenth NMOS transistor N14, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor N16, a source electrode of the seventeenth NMOS transistor N17, a drain electrode of the eighteenth NMOS transistor N18, and a ninth NMOS transistor N19, a source electrode of a nineteenth NMOS transistor N19 is grounded, a gate electrode of a fifteenth NMOS transistor N15 is connected to a gate electrode of a sixteenth NMOS transistor, and a connection end thereof is a second inverting input end of a two-input xor gate, a gate electrode of a seventeenth NMOS transistor N17 is connected to a gate electrode of a seventeenth NMOS transistor N18, and a connection end thereof is a second input end of a two-input xor gate, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, the sixteenth NMOS transistor N16, and the seventeenth NMOS transistor N17 are all low-threshold NMOS transistors, and threshold voltages are 0.243V, the ninth NMOS transistor N9 and the fourteenth NMOS transistor N14 are sub-threshold transistors, and threshold voltages are 0.367V, the tenth NMOS transistor N10, the thirteenth NMOS transistor N13, the fifteenth NMOS transistor N15, and the eighteenth NMOS transistor N18 are all high-threshold NMOS transistors, and threshold voltages are 0.489V; each two-input NAND gate respectively comprises a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a twentieth NMOS tube N20, a twenty-first NMOS tube N21, a twenty-second NMOS tube N22, a twenty-third NMOS tube N23, a twenty-fourth NMOS tube N24, a twenty-fifth NMOS tube N25, a twenty-sixth NMOS tube N26, a twenty-seventh NMOS tube N27, a twenty-eighth NMOS tube N28, a twenty-ninth NMOS tube N29, a thirty-ninth NMOS tube N30, a thirty-eleventh NMOS tube N31, a thirty-second NMOS tube N32, a thirty-third NMOS tube N33, a thirty-fourth NMOS tube N34, a thirty-fifth NMOS tube N35, a thirty-sixth NMOS tube N36, a thirty-seventh NMOS tube N37 and an eighth NMOS tube N38, a ninth NMOS tube P9, a tenth NMOS tube P10, a sixteenth NMOS tube P12, a source P11, a source P16 of the twelfth PMOS tube P11, a twenty-eighth NMOS tube P16, a source P-fifth NMOS tube P16, a source P of the PMOS and a source connected to the source of the source P, the grid of the ninth PMOS tube P9, the grid of the tenth PMOS tube P10, the grid of the twenty-first NMOS tube N21 and the grid of the twenty-fourth NMOS tube N24 are connected, the connection ends of the first control end of the two-input NAND gate, the drain of the ninth PMOS tube P9 is connected with the source of the thirteenth PMOS tube P13, the drain of the tenth PMOS tube P10 is connected with the source of the fourteenth PMOS tube P14, the grid of the eleventh PMOS tube P11, the grid of the twentieth NMOS tube N20, the drain of the twelfth PMOS tube P12, the drain of the twenty-first NMOS tube N21, the drain of the thirteenth PMOS tube P13, the drain of the twenty-second NMOS tube N22, the grid of the fourteenth PMOS tube P14 and the grid of the twenty-third NMOS tube N23 are connected, the drain of the eleventh PMOS tube P11 is connected with the drain of the twentieth NMOS tube N20, the connection ends of the two-input NAND gate are the inverted output ends of the two-input NAND gate, the grid of a twelfth PMOS tube P12, the grid of a twenty-sixth NMOS tube N26, the grid of a fifteenth PMOS tube P15, the grid of a twenty-seventh NMOS tube N27 and the grid of a thirty-eighth NMOS tube N38 are connected, the connecting end of the second control end of a two-input NAND gate is adopted, the grid of a thirteenth PMOS tube P13, the grid of a twenty-second NMOS tube N22, the drain of a fourteenth PMOS tube P14, the drain of a twenty-third NMOS tube N23, the drain of a fifteenth PMOS tube P15, the drain of a twenty-fourth NMOS tube N24, the grid of a sixteenth PMOS tube P16 and the grid of a twenty-fifth NMOS tube N25 are connected, the drain of a sixteenth PMOS tube P16 and the drain of a twenty-fifth NMOS tube N25 are connected, the connecting end of the second input NAND gate is adopted as the output end of the two-input NAND gate, the source of a twentieth NMOS tube N20 is grounded, the source of a twenty-first NMOS tube N21 and the drain of a twenty-sixth NMOS tube N26 are connected, the source of a twenty-sixth NMOS tube N26 is grounded, the drain of a twenty-eighth NMOS tube N22 and a twenty-eighth NMOS tube N28, a source electrode of a twenty-third NMOS transistor N23, a drain electrode of a twenty-ninth NMOS transistor N29, a drain electrode of a thirty-third NMOS transistor N30, a drain electrode of a thirty-first NMOS transistor N31 and a drain electrode of a thirty-second NMOS transistor N32 are connected, a source electrode of a twenty-fourth NMOS transistor N24 and a drain electrode of a twenty-seventh NMOS transistor N27 are connected, a source electrode of the twenty-seventh NMOS transistor N27 is grounded, a source electrode of a twenty-fifth NMOS transistor N25 is grounded, a source electrode of a twenty-eighth NMOS transistor N28 and a drain electrode of a thirty-third NMOS transistor N33 are connected, a source electrode of the twenty-ninth NMOS transistor N29 and a drain electrode of a thirty-fourth NMOS transistor N34 are connected, a gate electrode of the twenty-ninth NMOS transistor N29 and a gate electrode of the thirty-first NMOS transistor N31 are connected and a connection end thereof is a first inverting input end of a two-input NAND gate, a source electrode of the thirty-NMOS transistor N30 and a drain electrode of the thirty-fifth NMOS transistor N35 are connected, a gate electrode of the thirty-second NMOS transistor N30 and a gate electrode of the thirty-second NMOS transistor N32 are connected and a first input end thereof, a source electrode of a thirty-first NMOS transistor N31 is connected with a drain electrode of a thirty-sixth NMOS transistor N36, a source electrode of a thirty-second NMOS transistor N32 is connected with a drain electrode of a thirty-seventh NMOS transistor N37, a source electrode of a thirty-third NMOS transistor N33, a source electrode of a thirty-fourth NMOS transistor N34, a source electrode of a thirty-fifth NMOS transistor N35, a source electrode of a thirty-sixth NMOS transistor N36, a source electrode of a thirty-seventh NMOS transistor N37 is connected with a drain electrode of a thirty-eighth NMOS transistor N38, a source electrode of the thirty-eighth NMOS transistor N38 is grounded, a gate electrode of the thirty-fourth NMOS transistor N34 is connected with a gate electrode of a thirty-fifth NMOS transistor N35, a connecting end of the thirty-fourth NMOS transistor N34 is a second inverting input end of a two-input NAND gate, a gate electrode of the thirty-sixth NMOS transistor N36 is connected with a gate electrode of the thirty-seventh NMOS transistor N37, a connecting end of the thirty-input NAND gate is a second input end of the twenty-ninth NMOS transistor N29, a fourth NMOS transistor N34 is a low threshold voltage NMOS transistor, a threshold voltage is 0.V, a twenty-eighth NMOS transistor N28, a thirty-third threshold voltage is a thirty-sixth NMOS transistor N33, a thirty-sixth NMOS transistor N32, a thirty-sixth NMOS transistor N37 is a thirty-sixth NMOS transistor N32, a thirty-sixth threshold voltage is a thirty-sixth NMOS transistor N37, a thirty-fifth NMOS transistor N32, a thirty-sixth NMOS, a thirty-fifth NMOS transistor N37 is a thirty-sixth threshold voltage is a thirty-fifth high threshold voltage, a thirty-fifth NMOS transistor N37, a thirty-fifth NMOS transistor N32, a thirty-fifth NMOS transistor N37 is a thirty-fifth NMOS voltage is a thirty-fifth NMOS transistor N9, a thirty-fifth NMOS transistor N37 is a thirty-fifth NMOS transistor N32, a thirty-fifth high threshold voltage is a thirty-sixth NMOS, a thirty-high threshold voltage is a thirty-fifth NMOS transistor N37, and a thirty-fifth NMOS transistor N37. The four two-input NAND gates are respectively called a first two-input NAND gate NAND1, a second two-input NAND gate NAND2, a third two-input NAND gate NAND3 and a fourth two-input NAND gate NAND4, the two-input XOR gates are respectively called a first two-input XOR gate XOR1 and a second two-input XOR gate XOR2, the first input end of the first two-input NAND gate NAND1 is connected with the input end of a first inverter F1, the connecting end of the first input end of the first two-input NAND gate is the first input end of a multiplication unit circuit and is used for connecting a first multiplier A, the first inverting input end of the first two-input NAND gate NAND1 is connected with the output end of the first inverter F1, the second input end of the first two-input NAND gate NAND1 is connected with the input end of a second inverter F2, the connecting end of the second input end of the second inverter F2 is the second input end of the multiplication unit circuit and is used for connecting a second multiplier B, the second inverting input end of the first two-input NAND gate NAND1 is connected with the output end of the second inverter F2, a first control end of a first two-input NAND gate NAND1, a first control end of a second two-input NAND gate NAND2, a first control end of a third two-input NAND gate NAND3, a first control end of a fourth two-input NAND gate NAND4, a first control end of a first two-input XOR gate XOR1 and a first control end of a second two-input XOR gate XOR2 are connected, the connection end of the first control end of the multiplication unit circuit is used for accessing a discharge control signal discharge, a second control end of the first two-input NAND gate NAND1, a second control end of the second two-input NAND gate 2, a second control end of the third two-input NAND gate 3, a second control end of the fourth two-input NAND gate NAND4, a second control end of the first two-input XOR gate XOR1 and a second control end of the second two-input XOR gate XOR2 are connected, the connection end of the second control end of the multiplication unit circuit is a second control end of the multiplication unit circuit, the evaluation control signal eval is accessed, the output end of the first two-input NAND gate NAND1, the first inverting input end of the third two-input NAND gate NAND3 and the first inverting input end of the first two-input exclusive-OR gate XOR1 are connected, the inverting output end of the first two-input NAND gate NAND1, the first input end of the third two-input NAND gate NAND3 and the first input end of the first two-input exclusive-OR gate XOR1 are connected, the second input end of the first two-input exclusive-OR gate XOR1 and the second input end of the third two-input NAND gate NAND3 and the input end of the third inverter F3 are connected, and the connection end of the connection end is the third input end of the multiplication unit circuit, for connecting in the third multiplier C, the second inverting input terminal of the first two-input XOR gate XOR1, the second inverting input terminal of the third two-input NAND gate NAND3 and the output terminal of the third inverter F3 are connected, the output terminal of the first two-input XOR gate XOR1, the first input terminal of the second two-input XOR gate XOR2 and the first input terminal of the second two-input NAND gate NAND2 are connected, the inverting output terminal of the first two-input exclusive-or gate XOR1, the first inverting input terminal of the second input exclusive-or gate XOR2 and the first inverting input terminal of the second input NAND gate NAND2 are connected, the second input terminal of the second two-input exclusive-or gate XOR2, the second input terminal of the second input NAND gate NAND2 and the input terminal of the fourth inverter F4 are connected, and the connection terminal thereof is the low-order carry signal input terminal of the multiplication unit circuit for connecting the carry signal CI outputted at the low order, the second inverting input terminal of the second two-input exclusive-or gate XOR2, the second inverting input terminal of the second input NAND gate NAND2 and the output terminal of the fourth inverter F4 are connected, the output terminal of the second two-input exclusive-or gate XOR2 is the output terminal of the multiplication unit circuit for outputting the product signal, the inverting output terminal of the second input exclusive-or gate XOR2 is the inverting output terminal of the multiplication unit circuit, for outputting an inverted signal of the product signal, the output of the second two-input NAND gate NAND2 is connected with the first inverted input of the fourth two-input NAND gate NAND4, the inverted output of the second two-input NAND gate NAND2 is connected with the first input of the fourth two-input NAND gate NAND4, the output of the third two-input NAND gate NAND3 is connected with the second inverted input of the fourth two-input NAND gate NAND4, the inverted output end of the third two-input NAND gate NAND3 is connected with the second input end of the fourth two-input NAND gate NAND4, the output end of the fourth two-input NAND gate NAND4 is the carry signal output end of the multiplication unit circuit and is used for outputting a carry signal CO to the high order, and the inverted output end of the fourth two-input NAND gate NAND4 is the inverted carry signal output end of the multiplication unit circuit and is used for outputting an inverted signal CO of the carry signal to the high order.
The invention also discloses a multiplier realized by adopting the multiplication unit circuit, and the multiplier utilizing the threshold voltage characteristic of the invention is further described in detail by combining the embodiment of the attached drawings.
Example (b): as shown in fig. 4, 2 and3, a multiplier using threshold voltage characteristics includes m × n multiplication unit circuits, where m is equal to the number of multiplicand bits, and the multiplicand is an m-bit binary number X m-1 X m-2 ...X 0 The value of n is equal to the number of bits of a multiplier, which is n-bit binary number Y n-1 Y n-2 …Y 0 The m multiplied by n multiplication unit circuits are arranged according to n rows and m columns, and each multiplication unit circuit is respectively provided with a first input end, a second input end, a third input end, a first control end, a second control end, a low-order carry signal input end, a high-order carry signal output end and a product output end; the first control ends of the m multiplied unit circuits are connected together, the connection end of the m multiplied unit circuits is a first control end of the multiplier and is used for accessing a discharge control signal discharge, the second control ends of the m multiplied unit circuits are connected together, the connection end of the m multiplied unit circuits is a second control end of the multiplier and is used for accessing an evaluation control signal eval, and the first input ends of the m multiplied unit circuits in the Nth row are respectively accessed to the Nth bit data Y of the multiplier N-1 N =1,2, \ 8230, N, the second input ends of the N multiplication unit circuits in the M column are respectively connected with the M- (M-1) th bit data X of the multiplicand m-(M-1)-1 M, the third input ends of M multiplication unit circuits positioned on the 1 st row are respectively connected with a signal 0, the low bit carry signal input ends of N multiplication unit circuits positioned on the M th column are respectively connected with a signal 0, the high bit carry signal output end of the multiplication unit circuit positioned on the N th row and the k th column is connected with the low bit carry signal input end of the multiplication unit circuit positioned on the N th row and the k-1 column, k =2,3 \8230, M, the high bit carry signal output end of the multiplication unit circuit positioned on the j th row and the 1 st column is connected with the third input end of the multiplication unit circuit positioned on the j +1 th row and the 1 st column, and j =1,2Wherein, N-1, the product output end of the multiplication unit circuit positioned in the Nth row and the Kth column is connected with the third input end of the multiplication unit circuit positioned in the Nth row and the Kth +1 column, K =1,2, \ 8230, m-1, the product output end of the multiplication unit circuit positioned in the jth row and the mth column is the jth output end of the multiplier, and the jth bit Z of the product is output j-1 The product output end of the multiplication unit circuit in the Nth row and the Mth column is the (n-1 + M- (M-1) th) output end of the multiplier, and outputs the (n-1 + M- (M-1) th bit Z of the product n-1+m-(M-1)-1 The high-order carry signal output end of the multiplication unit circuit positioned in the n-th row and the 1 st column is the n + m output ends of the multiplier and outputs the n + m Z bits of the product n+m-1 (ii) a Each multiplication unit circuit comprises a first phase inverter F1, a second phase inverter F2, a third phase inverter F3, a fourth phase inverter F4, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, each two-input NAND gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end, and each two-input exclusive-OR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end; each two-input exclusive-or gate comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, a sixteenth NMOS tube N16, a seventeenth NMOS tube N17, an eighteenth NMOS tube N18 and a nineteenth NMOS tube N19, a source of the first PMOS tube P1, a source of the second PMOS tube P2, a source of the third PMOS tube P3, a fourth NMOS tube P4, a fourteenth NMOS tube P2, a fourteenth NMOS gate of the fifth NMOS tube P2, a fourteenth NMOS tube P9, a fourteenth NMOS gate of the fifth NMOS tube P2, a grid of the fifth NMOS tube P2 and a fourteenth NMOS gate of the fifth NMOS tube P9, a grid of the PMOS tube P2The grid of the MOS transistor N5 is connected, the connection end of the MOS transistor N5 is the first control end of the two-input XOR gate, the drain of the first PMOS transistor P1 is connected with the source of the fifth PMOS transistor P5, the drain of the second PMOS transistor P2 is connected with the source of the sixth PMOS transistor P6, the grid of the third PMOS transistor P3, the grid of the first NMOS transistor N1, the drain of the fourth PMOS transistor P4, the drain of the second NMOS transistor N2, the drain of the fifth PMOS transistor P5, the drain of the third NMOS transistor N3, the grid of the sixth PMOS transistor P6 and the grid of the fourth NMOS transistor N4 are connected, the drain of the third PMOS transistor P3 is connected with the drain of the first NMOS transistor N1, the connection end of the third PMOS transistor P3 is the inverted output end of the two-input XOR gate, the grid of the fourth PMOS transistor P4, the grid of the seventh NMOS transistor N7, the grid of the seventh PMOS transistor P7, the grid of the eighth NMOS transistor N8 and the grid of the nineteenth NMOS gate, the connection end of the NMOS gate is the second control end of the second XOR gate, a gate of a fifth PMOS transistor P5, a gate of a third NMOS transistor N3, a drain of a sixth PMOS transistor P6, a drain of a fourth NMOS transistor N4, a drain of a seventh PMOS transistor P7, a drain of a fifth NMOS transistor N5, a gate of an eighth PMOS transistor P8 and a gate of a sixth NMOS transistor N6, a drain of an eighth PMOS transistor P8 and a drain of a sixth NMOS transistor N6 are connected, and a connection end thereof is an output end of a two-input XOR gate, a source of the first NMOS transistor N1 is grounded, a source of the second NMOS transistor N2 and a drain of the seventh NMOS transistor N7 are connected, a source of the seventh NMOS transistor N7 is grounded, a source of the third NMOS transistor N3 and a drain of a ninth NMOS transistor N9 are connected, a source of the fourth NMOS transistor N4, a drain of the tenth NMOS transistor N10, a drain of the eleventh NMOS transistor N11, a drain of the twelfth NMOS transistor N12 and a drain of a thirteenth NMOS transistor N13 are connected, a source of the fifth NMOS transistor N5 and a source of the eighth NMOS transistor N8, a source of the eighth NMOS transistor N8 and a drain of the fourteenth NMOS transistor N14 are grounded, the source electrode of a tenth NMOS transistor N10 is connected with the drain electrode of a fifteenth NMOS transistor N15, the grid electrode of the tenth NMOS transistor N10 is connected with the grid electrode of a twelfth NMOS transistor N12, the connection end of the tenth NMOS transistor N10 is the first inverted input end of a two-input XOR gate, the source electrode of an eleventh NMOS transistor N11 is connected with the drain electrode of a sixteenth NMOS transistor N16, the grid electrode of the eleventh NMOS transistor N11 is connected with the grid electrode of a thirteenth NMOS transistor N13, the connection end of the eleventh NMOS transistor N13 is the first input end of the two-input XOR gate, the source electrode of the twelfth NMOS transistor N12 is connected with the drain electrode of a seventeenth NMOS transistor N17, and the tenth NMOS transistorA source electrode of the thirty-second NMOS transistor N13 is connected to a drain electrode of the eighteenth NMOS transistor N18, a source electrode of the fourteenth NMOS transistor N14, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor N16, a source electrode of the seventeenth NMOS transistor N17, a source electrode of the eighteenth NMOS transistor N18 and a drain electrode of the nineteenth NMOS transistor N19 are connected, a source electrode of the nineteenth NMOS transistor N19 is grounded, a gate electrode of the fifteenth NMOS transistor N15 is connected to a gate electrode of the sixteenth NMOS transistor N15, and a connection end thereof is a second inverted input end of a two-input xor gate, a gate electrode of the seventeenth NMOS transistor N17 is connected to a gate electrode of the eighteenth NMOS transistor N18, and a connection end thereof is a second input end of a two-input xor gate, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, the sixteenth NMOS transistor N16, and the seventeenth NMOS transistor N17 are all low-threshold NMOS transistors, and a threshold voltage of 0.243V, the ninth NMOS transistor N9 and the fourteenth NMOS transistor N14 are all subthreshold transistors, and a threshold voltage is 0.367V, the thirteenth NMOS transistor N10, the thirteenth NMOS transistor N15, the fifteenth NMOS transistor N13 is a high-NMOS transistor N13, and the fifteenth NMOS transistor N18 is a high-NMOS transistor V; each two-input NAND gate comprises a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a twentieth NMOS tube N20, a twenty-first NMOS tube N21, a twenty-second NMOS tube N22, a twenty-third NMOS tube N23, a twenty-fourth NMOS tube N24, a twenty-fifth NMOS tube N25, a twenty-sixth NMOS tube N26, a twenty-seventh NMOS tube N27, a twenty-eighth NMOS tube N28, a twenty-ninth NMOS tube N29, a thirty-ninth NMOS tube N30, a thirty-eleventh NMOS tube N31, a thirty-second NMOS tube N32, a thirty-third NMOS tube N33, a thirty-fourth NMOS tube N34, a thirty-fifth NMOS tube N35, a thirty-sixth NMOS tube N36, a thirty-seventh NMOS tube N37 and an eighth NMOS tube N38, a source electrode of a ninth PMOS transistor P9, a source electrode of a tenth PMOS transistor P10, a source electrode of an eleventh PMOS transistor P11, a source electrode of a twelfth PMOS transistor P12, a source electrode of a fifteenth PMOS transistor P15, a source electrode of a sixteenth PMOS transistor P16, a gate electrode of a twenty-eighth NMOS transistor N28, and a gate electrode of a thirty-third NMOS transistor N33 are all connected to a power supply, a gate electrode of the ninth PMOS transistor P9, a gate electrode of the tenth PMOS transistor P10, a gate electrode of a twenty-first NMOS transistor N21, and a gate electrode of a twenty-fourth NMOS transistor N24 are connected, and a connection end thereof is a first control end of a two-input nand gate, a drain electrode of the ninth PMOS transistor P9 and a thirteenth PMThe source of the OS transistor P13 is connected, the drain of the tenth PMOS transistor P10 is connected with the source of the fourteenth PMOS transistor P14, the gate of the eleventh PMOS transistor P11, the gate of the twentieth NMOS transistor N20, the drain of the twelfth PMOS transistor P12, the drain of the twenty-first NMOS transistor N21, the drain of the thirteenth PMOS transistor P13, the drain of the twenty-second NMOS transistor N22, the gate of the fourteenth PMOS transistor P14 and the gate of the twenty-third NMOS transistor N23 are connected, the drain of the eleventh PMOS transistor P11 is connected with the drain of the twentieth NMOS transistor N20, the connection end of the eleventh PMOS transistor P11 is the inverted output end of the two-input NAND gate, the gate of the twelfth PMOS transistor P12, the gate of the twenty-sixth NMOS transistor N26, the gate of the fifteenth NMOS transistor P15, the gate of the twenty-seventh NMOS transistor N27 and the gate of the thirty-eighth NMOS transistor N38 are connected, and the connection end of the twelfth PMOS is the second control end of the two-input NAND gate, a grid electrode of a thirteenth PMOS tube P13, a grid electrode of a twenty-second NMOS tube N22, a drain electrode of a fourteenth PMOS tube P14, a drain electrode of a twenty-third NMOS tube N23, a drain electrode of a fifteenth PMOS tube P15, a drain electrode of a twenty-fourth NMOS tube N24, a grid electrode of a sixteenth PMOS tube P16 and a grid electrode of a twenty-fifth NMOS tube N25 are connected, a drain electrode of the sixteenth PMOS tube P16 and a drain electrode of the twenty-fifth NMOS tube N25 are connected, a connecting end of the drain electrode is an output end of a two-input NAND gate, a source electrode of the twentieth NMOS tube N20 is grounded, a source electrode of the twenty-first NMOS tube N21 and a drain electrode of the twenty-sixth NMOS tube N26 are connected, a source electrode of the twenty-sixth NMOS tube N26 is grounded, a source electrode of the twenty-second NMOS tube N22 and a drain electrode of the twenty-eighth NMOS tube N28 are connected, a source electrode of the twenty-third NMOS tube N23, a drain electrode of the twenty-ninth NMOS tube N29, a drain electrode of the thirty-NMOS tube N30, a drain electrode of the thirty-NMOS tube N31 and a drain electrode of the thirty-second NMOS tube N32, a drain electrode of the twenty-fourth NMOS tube N24 and a seventh NMOS tube N27 are connected, the source electrode of the twenty-fifth NMOS transistor N25 is grounded, the source electrode of the twenty-eighth NMOS transistor N28 is connected with the drain electrode of the thirty-third NMOS transistor N33, the source electrode of the twenty-ninth NMOS transistor N29 is connected with the drain electrode of the thirty-fourth NMOS transistor N34, the grid of the twenty-ninth NMOS transistor N29 is connected with the grid of the thirty-first NMOS transistor N31, the connection end of the twenty-ninth NMOS transistor N29 is the first inverting input end of the two-input NAND gate, the source of the thirty-fifth NMOS transistor N30 is connected with the drain of the thirty-fifth NMOS transistor N35, the grid of the thirty-second NMOS transistor N30 is connected with the grid of the thirty-second NMOS transistor N32The source of the thirty-first NMOS transistor N31 is connected with the drain of the thirty-sixth NMOS transistor N36, the source of the thirty-second NMOS transistor N32 is connected with the drain of the thirty-seventh NMOS transistor N37, the source of the thirty-third NMOS transistor N33, the source of the thirty-fourth NMOS transistor N34, the source of the thirty-fifth NMOS transistor N35, the source of the thirty-sixth NMOS transistor N36, the source of the thirty-seventh NMOS transistor N37 and the drain of the thirty-eighth NMOS transistor N38 are connected, the source of the thirty-eighth NMOS transistor N38 is grounded, the gate of the thirty-fourth NMOS transistor N34 is connected with the gate of the thirty-fifth NMOS transistor N35, the connection end of the gate of the thirty-fifth NMOS transistor N35 is the second inverting input end of the two-input NAND gate, the gate of the thirty-sixth NMOS transistor N36 is connected with the gate of the thirty-seventh NMOS transistor N243, the connection end of the thirty-seventh NMOS transistor N37 is the second input end of the two-input NAND gate, the twenty-ninth NMOS transistor N29 and the thirty-fourth NMOS transistor N34 are both low threshold transistors, the NMOS threshold voltage is the thirty-0.V 28, the thirty-fifth NMOS transistor N32 is the thirty-fifth NMOS threshold voltage of the thirty-eighth NMOS transistor N33, the thirty-fifth NMOS transistor N32 is the thirty-sixth NMOS transistor N35, the thirty-fifth NMOS transistor V-high threshold of the thirty-NMOS transistor N30 and the thirty-eighth NMOS transistor N32. The four two-input NAND gates are respectively called a first two-input NAND gate NAND1, a second two-input NAND gate NAND2, a third two-input NAND gate NAND3 and a fourth two-input NAND gate NAND4, the two-input XOR gates are respectively called a first two-input XOR gate XOR1 and a second two-input XOR gate XOR2, the first input end of the first two-input NAND gate NAND1 is connected with the input end of a first inverter F1, the connecting end of the first two-input NAND gate is the first input end of the multiplication unit circuit, the first inverting input end of the first two-input NAND gate NAND1 is connected with the output end of the first inverter F1, the second input end of the first two-input NAND gate NAND1 is connected with the input end of the second inverter F2, the connecting end of the first two-input NAND gate NAND1 is the second input end of the multiplication unit circuit, the second inverting input end of the first two-input NAND gate NAND1 is connected with the output end of the second inverter F2, the first control end of the first two-input NAND gate NAND1, the first control end of the second two-input NAND gate NAND2, the first control end of the third two-input NAND gate NAND3 and the first control end of the fourth two-input NAND gate NAND4A first control end of the first two-input exclusive-or gate XOR1 and a first control end of the second two-input exclusive-or gate XOR2 are connected, and a connection end of the first two-input exclusive-or gate XOR1 and the second control end of the second two-input exclusive-or gate XOR2 is a first control end of the multiplication unit circuit, a second control end of the first two-input NAND gate NAND1, a second control end of the second two-input NAND gate NAND2, a second control end of the third two-input NAND gate NAND3, a second control end of the fourth two-input NAND gate NAND4, a second control end of the first two-input exclusive-or gate XOR1 and a second control end of the second two-input exclusive-or gate XOR2 are connected, and a connection end of the first two-input NAND gate NAND1 and a first inverting input end of the third two-input NAND gate NAND3 are connected, an inverting output end of the first two-input NAND gate XOR1 and a first input end of the first two-input exclusive-or gate XOR1 are connected, the second input end of the first two-input exclusive-or gate XOR1, the second input end of the third two-input NAND gate NAND3 and the input end of the third inverter F3 are connected, and the connection ends are the third input end of the multiplication unit circuit, the second inverting input end of the first two-input exclusive-or gate XOR1, the second inverting input end of the third two-input NAND gate NAND3 and the output end of the third inverter F3 are connected, the output end of the first two-input exclusive-or gate XOR1, the first input end of the second two-input exclusive-or gate XOR2 and the first input end of the second two-input NAND gate NAND2 are connected, the inverting output end of the first two-input exclusive-or gate XOR1, the first inverting input end of the second two-input exclusive-or gate XOR2 and the first inverting input end of the second two-input NAND gate NAND2 are connected, the second input end of the second two-input exclusive-or gate XOR2, the second input end of the second two-input NAND gate NAND2 and the input end of the fourth inverter F4 are connected, and the connection end of the connection end is the low carry bit of the multiplication unit circuit A signal input end, a second inverting input end of the second input exclusive-or gate XOR2, a second inverting input end of the second input NAND gate NAND2 and an output end of the fourth inverter F4 are connected, an output end of the second input exclusive-or gate XOR2 is an output end of the multiplication unit circuit and is used for outputting a product signal, and an inverting output end of the second input exclusive-or gate XOR2 is an inverting output end of the multiplication unit circuit and is used for outputting the product signalAnd the output end of the second two-input NAND gate NAND2 is connected with the first inverted input end of the fourth two-input NAND gate NAND4, the inverted output end of the second two-input NAND gate NAND2 is connected with the first input end of the fourth two-input NAND gate NAND4, the output end of the third two-input NAND gate NAND3 is connected with the second inverted input end of the fourth two-input NAND gate NAND4, the inverted output end of the third two-input NAND gate 3 is connected with the second input end of the fourth two-input NAND gate NAND4, the output end of the fourth two-input NAND gate NAND4 is a carry signal output end of the multiplication unit circuit, and the inverted output end of the fourth two-input NAND gate NAND4 is an inverted carry signal output end of the multiplication unit circuit.
The multiplier of the invention realizes the multiplication operation of binary numbers, and the working principle is as follows: the multiplicand X is m bits and is marked as X m-1 X m-2 ...X 0 The multiplier Y is n bits and marked as Y n-1 Y n-2 823080 and Y0, the product is m + n and is denoted as Z m+n-1 Z m+n-2 …Z 0 The multiplication method comprises the following steps of performing AND operation on each bit of an m-bit multiplicand and an n-bit multiplier to obtain n partial products with the number of bits being m, adding the n partial products by using an adder array (the multiplication unit circuit mainly comprises the adder circuit, so the adder array exists in the multiplication unit circuit array), and obtaining products. X m-1 X m-2 ...X 0 、Y n-1 Y n-2 8230that Y0 is an input numerical signal, evaluation control signal eval and discharge control signal discharge are input two control signals, Z m+n-1 Z m+n-2 …Z 0 Is the output signal. One evaluation operation is realized in one period, the period is divided into three stages, and when the eval and discharge signals are 01 and 00, the circuit enters a pre-charging stage; when the eval and discharge signals are 10, the circuit realizes evaluation operation and realizes the function of the circuit; when the eval and discharge signals are 11, the circuit enters a discharge state and is ready for the next evaluation operation. In the multiplier of the invention, the two-input exclusive-OR gate and the NAND gate have the same circuit structure and only configure the threshold of the MOS tubeThe voltage realizes different logic functions, the output is discharged from a pre-charging high level to a low level in each working period, the consumed energy is constant, the characteristics of mutual independence of energy consumption and processed data are realized, and the anti-DPA attack characteristic is realized while the reverse engineering attack is defended.
The operational timing diagram of the exclusive or gate of the multiplication unit circuit/multiplier using the threshold voltage characteristic of the present invention is shown in fig. 5. The connection node of the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube is marked as X, the connection node of the grid electrode of the fifth PMOS tube P5, the grid electrode of the third NMOS tube N3, the drain electrode of the sixth PMOS tube P6, the drain electrode of the fourth NMOS tube N4, the drain electrode of the seventh PMOS tube P7, the drain electrode of the fifth NMOS tube N5, the grid electrode of the eighth PMOS tube P8 and the grid electrode of the sixth NMOS tube N6 is marked as Y, as can be seen from fig. 5, the working process of the xor gate is divided into three stages of pre-charging, evaluation and discharging, when the evaluation control signal eval and the discharge control signal discharge are both at low level 0 or the evaluation control signal eval is at low level 0 and the discharge control signal discharge1, the xor gate enters the pre-charging stage, the fourth PMOS transistor P4 and the seventh PMOS transistor P7 are both turned on, X and Y are charged to high levels, and then the xor gate respectively operates through the first phase inverter composed of the third PMOS transistor and the first NMOS transistor and the second phase inverter composed of the eighth PMOS transistor and the sixth NMOS transistor, and outputs an output signal
Figure BDA0002279334390000231
And OUT are both pulled low; when eval becomes high level and discharge is low level 0, the fourth PMOS transistor P4 and the seventh PMOS transistor P7 are turned off, the pre-charging is finished, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, the nineteenth NMOS transistor N19 of the evaluation transistor is turned on, the circuit enters the evaluation stage, at this time, a =1, b =1, the thirteenth NMOS transistor N13 and the eighteenth NMOS transistor N18 in the pull-down network are turned on, the gate voltages of the third NMOS transistor N3 and the fourth NMOS transistor N4 are pre-charged to high level before, so that the currents I1 and I2 flow through, since the ninth NMOS transistor N9 and the fourteenth NMOS transistor N14 are subthreshold transistors, they are in the normally-on state,the current difference is amplified by a sensitive amplifier consisting of a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube and a fourth NMOS tube, the X rate is discharged to a low level firstly, and is subjected to operation by a phase inverter consisting of the third PMOS tube and the first NMOS tube and then is subjected to ion-binding>
Figure BDA0002279334390000241
When the voltage is pulled to a high level, the seventh PMOS tube P7 is conducted, Y still keeps the high level, and OUT is a low level; when eval and discharge are high level 1 at the same time, a second NMOS tube N2, a fifth NMOS tube N5, a seventh NMOS tube N7 and an eighth NMOS tube N8 are conducted, the circuit enters a discharging stage, X and Y are discharged to low level, then the circuit is respectively operated through a first phase inverter formed by a third PMOS tube and a first NMOS tube and a second phase inverter formed by an eighth PMOS tube and a sixth NMOS tube, and OUT and & accumulator>
Figure BDA0002279334390000242
All are pulled to high level, and one working period is finished, so that the exclusive-or logic function is realized.
The functional simulation graph of the exclusive or gate of the multiplier/multiplier unit circuit using the threshold voltage characteristic of the present invention is shown in fig. 6, and it can be seen from an analysis of fig. 6 that: the exclusive-or gate circuit provided by the invention traverses all input conditions and has a correct logic function.
The simulation graph of the power consumption of the exclusive or gate of the multiplier/multiplier unit circuit using the threshold voltage characteristic of the present invention is shown in fig. 7, and it can be seen from an analysis of fig. 7 that: the exclusive-OR gate circuit has the characteristics that power consumption curves are consistent in different clock periods no matter what input signals are, the power consumption is independent of the input signals, and DPA attacks can be effectively resisted.
The functional simulation graph of the nand gate of the multiplier unit circuit/multiplier circuit using the threshold voltage characteristic of the present invention is shown in fig. 8, and it can be known from an analysis of fig. 8 that: the NAND gate of the invention traverses all input conditions and has correct logic function.
The functional verification diagram of the 4-bit multiplier utilizing the threshold voltage characteristic of the invention is shown in fig. 9, and the analysis of fig. 9 shows that: the multiplier circuit of the present invention has a correct logic function.
The power consumption simulation graph of the multiplier using the threshold voltage characteristic of the present invention is shown in fig. 10, and it can be seen from an analysis of fig. 10 that: compared with the traditional multiplier, the power consumption of the traditional multiplier depends on input signals, and different power consumptions can be generated by different input signals.

Claims (2)

1. A multiplication unit circuit utilizing threshold voltage characteristics is characterized by comprising a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, wherein each two-input NAND gate is respectively provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end;
each of the two-input exclusive-OR gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS, a source of the eighth PMOS, a source of the ninth PMOS, and a gate of the fourteenth are all connected to a power supply of the fourteenth transistor, the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connection end of the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input XOR gate, the drain electrode of the first PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, the connecting end of the third PMOS tube is the inverted output end of the two-input exclusive-OR gate, and the grid electrode of the fourth PMOS tube, the grid electrode of the seventh NMOS transistor, the grid electrode of the seventh PMOS transistor, the grid electrode of the eighth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input xor gate, the grid electrode of the fifth PMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the sixth PMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the seventh PMOS transistor, the drain electrode of the fifth NMOS transistor, the grid electrode of the eighth PMOS transistor and the grid electrode of the sixth NMOS transistor are connected, the drain electrode of the eighth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input xor gate, the source electrode of the first NMOS transistor is grounded, the source electrode of the second NMOS transistor and the drain electrode of the seventh NMOS transistor are connected, the source electrode of the seventh NMOS transistor is grounded, the source electrode of the third NMOS transistor and the drain electrode of the ninth NMOS transistor are connected, the source of the fourth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor, the drain of the twelfth NMOS transistor, the drain of the thirteenth NMOS transistor, the source of the fifth NMOS transistor and the drain of the eighth NMOS transistor, the source of the eighth NMOS transistor is grounded, the source of the sixth NMOS transistor is grounded, the source of the ninth NMOS transistor and the drain of the fourteenth NMOS transistor are connected, the source of the tenth NMOS transistor and the drain of the fifteenth NMOS transistor are connected, the gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected and the connection end is the first inverting input end of the two-input xor gate, the source of the eleventh NMOS transistor and the drain of the sixteenth NMOS transistor are connected, the gate of the eleventh NMOS transistor and the gate of the thirteenth NMOS transistor are connected and the connection end is the second inverting input end A first input end of the input xor gate, a source of the twelfth NMOS is connected to a drain of the seventeenth NMOS, a source of the thirteenth NMOS is connected to a drain of the eighteenth NMOS, a source of the fourteenth NMOS, a source of the fifteenth NMOS, a source of the sixteenth NMOS, a source of the seventeenth NMOS, a source of the eighteenth NMOS and a drain of the nineteenth NMOS are connected, a source of the nineteenth NMOS is grounded, a gate of the fifteenth NMOS is connected to a gate of the sixteenth NMOS, and a connection end of the fifteenth NMOS and a connection end of the sixteenth NMOS is a second inverting input end of the two-input xor gate, the gate of the seventeenth NMOS transistor is connected to the gate of the eighteenth NMOS transistor, and the connection end of the seventeenth NMOS transistor is the second input end of the two-input xor gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold NMOS transistors with a threshold voltage of 0.243V, the ninth NMOS transistor and the fourteenth NMOS transistor are all sub-threshold transistors with a threshold voltage of 0.367V, the tenth NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor and the eighteenth NMOS transistor are all high-threshold NMOS transistors with a threshold voltage of 0.489V;
each of the two-input NAND gates comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-eleventh NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube and a thirty-eighth NMOS tube respectively, wherein the source electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube, the source electrode of the eleventh PMOS tube, the source electrode of the twelfth PMOS tube, the source electrode of the fifteenth tube, the source electrode of the sixteenth PMOS tube, the twenty-eighth NMOS tube and the thirty-eighth NMOS tubes are all connected to the grid electrodes of the NMOS tubes, the grid electrode of the ninth PMOS tube, the grid electrode of the tenth PMOS tube, the grid electrode of the twenty-first NMOS tube and the grid electrode of the twenty-fourth NMOS tube are connected, the connecting end of the grid electrode of the twenty-first NMOS tube and the grid electrode of the twenty-fourth NMOS tube is the first control end of the two-input NAND gate, the drain electrode of the ninth PMOS tube is connected with the source electrode of the thirteenth PMOS tube, the drain electrode of the tenth PMOS tube is connected with the source electrode of the fourteenth PMOS tube, the grid electrode of the eleventh PMOS tube, the grid electrode of the twentieth NMOS tube, the drain electrode of the twelfth PMOS tube, the drain electrode of the twenty-first NMOS tube, the drain electrode of the thirteenth PMOS tube, the drain electrode of the twenty-second NMOS tube, the grid electrode of the fourteenth PMOS tube and the grid electrode of the twenty-third NMOS tube are connected, the drain of the eleventh PMOS transistor is connected to the drain of the twentieth NMOS transistor and the connection end thereof is the inverted output end of the two-input nand gate, the gate of the twelfth PMOS transistor, the gate of the twenty-sixth NMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the twenty-seventh NMOS transistor and the gate of the thirty-eighth NMOS transistor are connected and the connection end thereof is the second control end of the two-input nand gate, the gate of the thirteenth PMOS transistor, the gate of the twenty-second NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the twenty-third NMOS transistor, the drain of the fifteenth PMOS transistor, the drain of the twenty-fourth NMOS transistor, the gate of the sixteenth PMOS transistor and the gate of the twenty-fifth NMOS transistor are connected, the drain of the sixteenth PMOS transistor and the drain of the twenty-fifth NMOS transistor are connected and the connection end thereof is the two-input output end of the two-input nand gate, the source electrode of the twenty-first NMOS transistor is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-fifth NMOS transistor, the drain electrode of the thirty-first NMOS transistor and the drain electrode of the thirty-second NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, and the source electrode of the twenty-eighth NMOS transistor is connected with the drain electrode of the thirty-third NMOS transistor, a source of the twenty ninth NMOS transistor is connected to a drain of the thirty fourth NMOS transistor, a gate of the twenty ninth NMOS transistor is connected to a gate of the thirty eleventh NMOS transistor, a connection end of the twenty ninth NMOS transistor is a first inverting input end of the two-input nand gate, a source of the thirty NMOS transistor is connected to a drain of the thirty fifth NMOS transistor, a gate of the thirty NMOS transistor is connected to a gate of the thirty second NMOS transistor, a connection end of the thirty second NMOS transistor is a first input end of the two-input nand gate, a source of the thirty eleventh NMOS transistor is connected to a drain of the thirty sixth NMOS transistor, a source of the thirty second NMOS transistor is connected to a drain of the thirty seventh NMOS transistor, a source of the thirty third NMOS transistor, a source of the thirty fourth NMOS transistor, a source of the thirty fifth NMOS transistor, a source of the thirty sixth NMOS transistor, a source of the thirty seventh NMOS transistor and a drain of the thirty eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor is connected to the gate of the thirty-fifth NMOS transistor, the connection end of the thirty-fourth NMOS transistor is the second inverting input end of the two-input nand gate, the gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, the connection end of the thirty-seventh NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are all high-threshold NMOS transistors, and the threshold voltage is 0.489V;
the four two-input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two-input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first two-input nand gate is the first control end of the multiplication unit circuit and is used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the multiplication unit circuit is the multiplication unit circuit A second control terminal of the first two-input nand gate, a first inverting input terminal of the third two-input nand gate and a first inverting input terminal of the first two-input xor gate are connected, an inverting output terminal of the first two-input nand gate, a first input terminal of the third two-input nand gate and a first input terminal of the first two-input xor gate are connected, a second input terminal of the first two-input xor gate and a second input terminal of the third two-input nand gate and an input terminal of the third inverter are connected, a connection terminal of the first two-input xor gate and the second two-input nand gate is a third input terminal of the multiplication unit circuit and is used for connecting a third multiplier, a second inverting input terminal of the first two-input xor gate, a second inverting input terminal of the third two-input nand gate and an output terminal of the third inverter are connected, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal with low-order output, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting a product signal, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting an inverted signal of the product signal, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit and is used for outputting a carry signal to a high order, and the inverted output end of the carry signal of the multiplication unit circuit is used for outputting an inverted carry signal to a high order.
2. A multiplier using a threshold voltage characteristic, comprising mxn multiplication cell circuits, wherein m has a value equal to the number of bits of a multiplicand, n has a value equal to the number of bits of a multiplier, and the mxn multiplication cell circuits are arranged in n rows and m columns, each of said multiplication cell circuits having a first input terminal, a second input terminal, a third input terminal, a first control terminal, a second control terminal, a low carry signal input terminal, a high carry signal output terminal, and a product output terminal, respectively; the first control terminals of the mxn multiplication unit circuits are connected together, the connection terminal of the M mxn multiplication unit circuits is the first control terminal of the multiplier and is used for accessing a discharge control signal, the second control terminals of the mxn multiplication unit circuits are connected together, the connection terminal of the M mxn multiplication unit circuits is the second control terminal of the multiplier and is used for accessing an evaluation control signal, the first input terminals of the M multiplication unit circuits positioned in the Nth row are respectively accessed to the Nth data of the multiplier, N =1,2, 8230, N, the second input terminals of the N multiplication unit circuits positioned in the Mth column are respectively accessed to the M- (M-1) th data, M =1,2, 8230, M, the third input terminals of the M multiplication unit circuits positioned in the 1 st row are respectively accessed to a signal 0, the low-order carry signal input ends of N multiplication unit circuits positioned in the mth column are respectively connected with a signal 0, the high-order carry signal output ends of the multiplication unit circuits positioned in the nth row and the kth column are connected with the low-order carry signal input ends of the multiplication unit circuits positioned in the nth row and the kth column, K =2,3, \\ 8230;. M, the high-order carry signal output ends of the multiplication unit circuits positioned in the jth row and the 1 st column are connected with the third input ends of the multiplication unit circuits positioned in the jth +1 row and the 1 st column, j =1,2, \\ 8230;. N-1, the product output ends of the multiplication unit circuits positioned in the nth row and the kth column are connected with the third input ends of the multiplication unit circuits positioned in the nth row and the kth +1 column, K =1,2, \\ 8230, M-1, the product output end of the multiplication unit circuit positioned in the jth row and the mth column is the jth output end of the multiplier, the product output end of the multiplication unit circuit positioned in the nth row and the mth column is the (n-1 + M- (M-1) th output end of the multiplier and outputs the (n-1 + M- (M-1) th bit of the product, and the high-order carry signal output end of the multiplication unit circuit positioned in the nth row and the 1 st column is the (n + M) th output end of the multiplier and outputs the (n + M) th bit of the product;
each multiplication unit circuit comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input XOR gates with the same structure, each two-input NAND gate is provided with a first input end, a first inverting input end, a second inverting input end, a first control end, a second control end, an output end and an inverting output end, and each two-input XOR gate is provided with a first input end, a first inverting input end, a second inverting input end, a first control end, a second control end, an output end and an inverting output end; each of the two-input exclusive-OR gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS, a source of the eighth PMOS, a source of the ninth PMOS, and a gate of the fourteenth are all connected to a power supply of the fourteenth transistor, the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connection end of the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input XOR gate, the drain electrode of the first PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, the connecting end of the third PMOS tube is the inverted output end of the two-input exclusive-OR gate, and the grid electrode of the fourth PMOS tube, the grid electrode of the seventh NMOS transistor, the grid electrode of the seventh PMOS transistor, the grid electrode of the eighth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input xor gate, the grid electrode of the fifth PMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the sixth PMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the seventh PMOS transistor, the drain electrode of the fifth NMOS transistor, the grid electrode of the eighth PMOS transistor and the grid electrode of the sixth NMOS transistor are connected, the drain electrode of the eighth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input xor gate, the source electrode of the first NMOS transistor is grounded, the source electrode of the second NMOS transistor and the drain electrode of the seventh NMOS transistor are connected, the source electrode of the seventh NMOS transistor is grounded, the source electrode of the third NMOS transistor and the drain electrode of the ninth NMOS transistor are connected, the source of the fourth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor, the drain of the twelfth NMOS transistor, the drain of the thirteenth NMOS transistor, the source of the fifth NMOS transistor and the drain of the eighth NMOS transistor, the source of the eighth NMOS transistor is grounded, the source of the sixth NMOS transistor is grounded, the source of the ninth NMOS transistor and the drain of the fourteenth NMOS transistor are connected, the source of the tenth NMOS transistor and the drain of the fifteenth NMOS transistor are connected, the gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected and the connection end is the first inverting input end of the two-input xor gate, the source of the eleventh NMOS transistor and the drain of the sixteenth NMOS transistor are connected, the gate of the eleventh NMOS transistor and the gate of the thirteenth NMOS transistor are connected and the connection end is the two-input xor gate A first input end of an exclusive-or gate, a source electrode of the twelfth NMOS transistor is connected with a drain electrode of the seventeenth NMOS transistor, a source electrode of the thirteenth NMOS transistor is connected with a drain electrode of the eighteenth NMOS transistor, a source electrode of the fourteenth NMOS transistor, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor, a source electrode of the seventeenth NMOS transistor, a source electrode of the eighteenth NMOS transistor and a drain electrode of the nineteenth NMOS transistor are connected, a source electrode of the nineteenth NMOS transistor is grounded, a gate electrode of the fifteenth NMOS transistor is connected with a gate electrode of the sixteenth NMOS transistor and a connection end thereof is a second inverting input end of the two-input exclusive-or gate, a gate electrode of the seventeenth NMOS transistor is connected with a gate electrode of the eighteenth NMOS transistor and a connection end thereof is a second input end of the two-input exclusive-or gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold transistors, a threshold voltage of the fourteenth NMOS transistor is 0.243, a voltage of the fourteenth NMOS transistor and a voltage of the nineteenth NMOS transistor is a sub-threshold voltage of the eighteenth NMOS transistor, a sub-NMOS, a sub-threshold voltage of the nineteenth NMOS transistor is 0.489; each of the two-input NAND gates comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-eleventh NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube and a thirty-eighth NMOS tube respectively, wherein the source electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube, the source electrode of the eleventh PMOS tube, the source electrode of the twelfth PMOS tube, the source electrode of the fifteenth tube, the source electrode of the sixteenth PMOS tube, the twenty-eighth NMOS tube and the thirty-eighth NMOS tubes are all connected to the grid electrodes of the NMOS tubes, the grid electrode of the ninth PMOS tube, the grid electrode of the tenth PMOS tube, the grid electrode of the twenty-first NMOS tube and the grid electrode of the twenty-fourth NMOS tube are connected, the connecting end of the grid electrode of the twenty-first NMOS tube and the grid electrode of the twenty-fourth NMOS tube is the first control end of the two-input NAND gate, the drain electrode of the ninth PMOS tube is connected with the source electrode of the thirteenth PMOS tube, the drain electrode of the tenth PMOS tube is connected with the source electrode of the fourteenth PMOS tube, the grid electrode of the eleventh PMOS tube, the grid electrode of the twentieth NMOS tube, the drain electrode of the twelfth PMOS tube, the drain electrode of the twenty-first NMOS tube, the drain electrode of the thirteenth PMOS tube, the drain electrode of the twenty-second NMOS tube, the grid electrode of the fourteenth PMOS tube and the grid electrode of the twenty-third NMOS tube are connected, the drain of the eleventh PMOS transistor is connected to the drain of the twentieth NMOS transistor and the connection end thereof is the inverted output end of the two-input nand gate, the gate of the twelfth PMOS transistor, the gate of the twenty-sixth NMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the twenty-seventh NMOS transistor and the gate of the thirty-eighth NMOS transistor are connected and the connection end thereof is the second control end of the two-input nand gate, the gate of the thirteenth PMOS transistor, the gate of the twenty-second NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the twenty-third NMOS transistor, the drain of the fifteenth PMOS transistor, the drain of the twenty-fourth NMOS transistor, the gate of the sixteenth PMOS transistor and the gate of the twenty-fifth NMOS transistor are connected, the drain of the sixteenth PMOS transistor and the drain of the twenty-fifth NMOS transistor are connected and the connection end thereof is the two-input output end of the two-input nand gate, the source electrode of the twenty-first NMOS transistor is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-fifth NMOS transistor, the drain electrode of the thirty-first NMOS transistor and the drain electrode of the thirty-second NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, and the source electrode of the twenty-eighth NMOS transistor is connected with the drain electrode of the thirty-third NMOS transistor, the source of the twenty-ninth NMOS transistor is connected to the drain of the thirty-fourth NMOS transistor, the gate of the twenty-ninth NMOS transistor is connected to the gate of the thirty-eleventh NMOS transistor, and the connection end thereof is the first inverting input end of the two-input nand gate, the source of the thirty-ninth NMOS transistor is connected to the drain of the thirty-fifth NMOS transistor, the gate of the thirty-ninth NMOS transistor is connected to the gate of the thirty-second NMOS transistor, and the connection end thereof is the first input end of the two-input nand gate, the source of the thirty-eleventh NMOS transistor is connected to the drain of the thirty-sixth NMOS transistor, the source of the thirty-second NMOS transistor is connected to the drain of the thirty-seventh NMOS transistor, the source of the thirty-third NMOS transistor, the source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor and the drain of the thirty-eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor is connected to the gate of the thirty-fifth NMOS transistor, the connection end of the thirty-fourth NMOS transistor is the second inverting input end of the two-input nand gate, the gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, the connection end of the thirty-seventh NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are all high-threshold NMOS transistors, and the threshold voltage is 0.489V; the four two-input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two-input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first two-input nand gate is the first control end of the multiplication unit circuit and is used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the multiplication unit circuit is the multiplication unit circuit A second control terminal of the first two-input nand gate, a first inverting input terminal of the third two-input nand gate and a first inverting input terminal of the first two-input xor gate are connected, an inverting output terminal of the first two-input nand gate, a first input terminal of the third two-input xor gate and a first input terminal of the first two-input xor gate are connected, a second input terminal of the first two-input xor gate and a second input terminal of the third two-input nand gate and an input terminal of the third inverter are connected, a connection terminal of the first two-input xor gate and the second two-input xor gate is a third input terminal of the multiplication unit circuit and is used for connecting a third multiplier, a second inverting input terminal of the first two-input xor gate, a second inverting input terminal of the third two-input nand gate and an output terminal of the third inverter are connected, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal output at a low order, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting a product signal, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting an inverted signal of the product signal, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit and is used for outputting a carry signal to a high order, and the inverted output end of the carry signal of the multiplication unit circuit is used for outputting an inverted carry signal to a high order.
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