CN111045643A - Multiplication unit circuit and multiplier utilizing threshold voltage characteristics - Google Patents

Multiplication unit circuit and multiplier utilizing threshold voltage characteristics Download PDF

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CN111045643A
CN111045643A CN201911134935.8A CN201911134935A CN111045643A CN 111045643 A CN111045643 A CN 111045643A CN 201911134935 A CN201911134935 A CN 201911134935A CN 111045643 A CN111045643 A CN 111045643A
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nmos transistor
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gate
transistor
thirty
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CN111045643B (en
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吴秋丰
张跃军
李憬
张会红
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Ningbo University
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Ningbo University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

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  • Theoretical Computer Science (AREA)
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Abstract

The invention discloses a multiplication unit circuit and a multiplier utilizing threshold voltage characteristics, wherein the multiplication unit circuit is composed of two exclusive-OR gates, four NAND gates and four inverters, the multiplier is composed of a plurality of multiplication unit circuits, the exclusive-OR gates and the NAND gates are used as two basic units of the multiplication unit circuit, the exclusive-OR gates and the NAND gates are realized by adopting the same circuit structure, the circuit structure can respectively realize an exclusive-OR logic function and a NAND logic function when the threshold voltage characteristics of MOS (metal oxide semiconductor) tubes in the same circuit structure are configured, the multiplication unit circuit realizes one-time evaluation operation in one period, the multiplication unit circuit is divided into three stages in one period, the three stages are respectively a pre-charging stage, an evaluation operation stage and a discharging stage, and differential pull-down networks of the exclusive-OR gates and the NAND gates adopt; the method has the advantages of small area and power consumption overhead, capability of simultaneously defending reverse engineering and DPA attack, and high safety.

Description

Multiplication unit circuit and multiplier utilizing threshold voltage characteristics
Technical Field
The present invention relates to a multiplier cell circuit, and more particularly, to a multiplier cell circuit and a multiplier using threshold voltage characteristics.
Background
With the development of very large scale integrated circuits and information security technologies, protection of Intellectual Property (IP) is receiving more and more attention. Meanwhile, the attack mode developed for the chip IP core is also infinite. Reverse engineering is one of the ways that attackers currently have a quick mastery of the chip core technology of designers. An attacker analyzes the internal structure of the chip through reverse engineering, extracts the circuit netlist, masters the actual functions of the chip, seriously influences the legal interests of the designer, and seriously infringes the intellectual property of the designer through behaviors such as chip cloning. For an encryption chip, an attacker bypasses a cryptographic algorithm, collects physical information leaked out in different round function encryption processes, and uses a statistical method to estimate a secret key, and the attack mode is called a side channel attack, wherein Differential Power Analysis (DPA) is an efficient and practical attack mode in the side channel attack, and defense against the DPA attack also becomes a hotspot studied at present. Therefore, the cipher device resisting reverse engineering and DPA has wide application prospect.
Addition is the most common operation, and theoretically, multiplication, subtraction and division can be converted into addition. The multiplier is a main component constituting an arithmetic operator, and is widely applied to processing data of different word lengths in various digital encryption systems. In the aspect of multiplier implementation, a multiplier implemented based on adiabatic dynamic differential logic has certain defects in safety, is easily attacked by reverse engineering and DPA, is complex in time sequence control, needs to design a complex interface circuit when interacting with a CMOS circuit, and is complex in circuit structure and large in area and power consumption overhead; although the multiplier realized by the differential logic based on the lookup table has good DPA attack resistance, reverse engineering cannot defend, a large number of transistors are needed, and the area and power consumption overhead are also large; multiplier output load capacitances based on sensitive amplification type logic implementations are not exactly uniform and still may serve as a breakthrough point for reverse engineering and DPA attacks.
Disclosure of Invention
One of the technical problems to be solved by the invention is to provide a multiplication unit circuit which has small area and power consumption overhead, can simultaneously defend reverse engineering and DPA attack, and has high safety and threshold voltage characteristic.
The technical scheme adopted by the invention for solving one of the technical problems is as follows: a multiplication unit circuit utilizing threshold voltage characteristics comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, wherein each two-input NAND gate is respectively provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end; each of the two-input exclusive-or gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a source of the ninth NMOS transistor, and a fourteenth NMOS transistor, and a gate of the first PMOS transistor is connected to a gate of the fourteenth NMOS transistor, The grid electrode of the second PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connecting end of the grid electrode of the second PMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input exclusive-OR gate, the drain electrode of the first PMOS tube and the source electrode of the fifth PMOS tube are connected, the drain electrode of the second PMOS tube and the source electrode of the sixth PMOS tube are connected, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube are connected, the connecting end of the third PMOS tube and the connecting end of the third PMOS tube are the inverted output end of the two-input exclusive-OR gate, the grid electrode of the fourth PMOS tube, the grid electrode of the seventh NMOS tube, the drain electrode of the fifth NMOS tube, The grid electrode of the seventh PMOS transistor, the grid electrode of the eighth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input exclusive or gate, the grid electrode of the fifth PMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the sixth PMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the seventh PMOS transistor, the drain electrode of the fifth NMOS transistor, the grid electrode of the eighth PMOS transistor and the grid electrode of the sixth NMOS transistor are connected, the drain electrode of the eighth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input exclusive or gate, the source electrode of the first NMOS transistor is grounded, the source electrode of the second NMOS transistor and the drain electrode of the seventh NMOS transistor are connected, the source electrode of the seventh NMOS transistor is grounded, and the source electrode of the third NMOS transistor and the drain electrode of the ninth NMOS transistor are connected, a source of the fourth NMOS transistor, a drain of the tenth NMOS transistor, a drain of the eleventh NMOS transistor, a drain of the twelfth NMOS transistor and a drain of the thirteenth NMOS transistor, a source of the fifth NMOS transistor and a drain of the eighth NMOS transistor are connected, a source of the eighth NMOS transistor is grounded, a source of the sixth NMOS transistor is grounded, a source of the ninth NMOS transistor and a drain of the fourteenth NMOS transistor are connected, a source of the tenth NMOS transistor and a drain of the fifteenth NMOS transistor are connected, a gate of the tenth NMOS transistor and a gate of the twelfth NMOS transistor are connected and a connection end thereof is a first inverting input end of the two-input xor gate, a source of the eleventh NMOS transistor and a drain of the sixteenth NMOS transistor are connected, a gate of the eleventh NMOS transistor and a connection end thereof is a first input end of the two-input xor gate, a source electrode of the twelfth NMOS transistor is connected with a drain electrode of the seventeenth NMOS transistor, a source electrode of the thirteenth NMOS transistor is connected with a drain electrode of the eighteenth NMOS transistor, a source electrode of the fourteenth NMOS transistor, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor, a source electrode of the seventeenth NMOS transistor, a source electrode of the eighteenth NMOS transistor and a drain electrode of the nineteenth NMOS transistor are connected, a source electrode of the nineteenth NMOS transistor is grounded, a gate electrode of the fifteenth NMOS transistor is connected with a gate electrode of the sixteenth NMOS transistor, and a connection end thereof is a second inverting input end of the two-input XOR gate, a gate electrode of the seventeenth NMOS transistor is connected with a gate electrode of the eighteenth NMOS transistor, and a connection end thereof is a second input end of the two-input XOR gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold NMOS transistors, the threshold voltage is 0.243V, the ninth NMOS transistor and the fourteenth NMOS transistor are sub-threshold transistors, and the threshold voltage is 0.367V, the tenth NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor and the eighteenth NMOS transistor are high-threshold NMOS transistors, and the threshold voltage is 0.489V; each of the two-input nand gates respectively comprises a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty-eleventh NMOS transistor, a thirty-second NMOS transistor, a thirty-third NMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor and a thirty-eighth NMOS transistor, wherein the source electrode of the ninth PMOS transistor, the source electrode of the tenth PMOS transistor, the source electrode of the eleventh PMOS transistor, the source electrode of the twelfth PMOS transistor, the fifteenth PMOS transistor, the source electrode of the sixteenth PMOS transistor, the sixteenth NMOS transistor, The gate of the twenty-eighth NMOS transistor and the gate of the thirty-third NMOS transistor are both connected to a power supply, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the twenty-first NMOS transistor and the gate of the twenty-fourth NMOS transistor are connected, and the connection end thereof is the first control end of the two-input nand gate, the drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor, the drain of the tenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the gate of the eleventh PMOS transistor, the gate of the twentieth NMOS transistor, the drain of the twelfth PMOS transistor, the drain of the twenty-first NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the twenty-second NMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the twenty-third NMOS transistor are connected, the drain of the eleventh PMOS transistor and the drain of the twenty-NMOS transistor are connected, and the connection end thereof is the second input nand gate, the drain of the twelfth PMOS transistor and the drain of the twenty-first NMOS transistor are connected The grid of the twelfth PMOS tube, the grid of the twenty-sixth NMOS tube, the grid of the fifteenth PMOS tube, the grid of the twenty-seventh NMOS tube and the grid of the thirty-eighth NMOS tube are connected, the connecting end of the second control end of the two-input NAND gate is the second control end of the two-input NAND gate, the grid of the thirteenth PMOS tube, the grid of the twenty-second NMOS tube, the drain of the fourteenth PMOS tube, the drain of the twenty-third NMOS tube, the drain of the fifteenth PMOS tube, the drain of the twenty-fourth NMOS tube, the grid of the sixteenth PMOS tube and the grid of the twenty-fifth NMOS tube are connected, the drain of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube are connected, the connecting end of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube is the output end of the two-input NAND gate, and the source of the twenty-NMOS tube is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-eleventh NMOS transistor and the drain electrode of the thirty-second NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, the source electrode of the twenty-eighth NMOS transistor and the drain electrode of the thirty-third NMOS transistor are connected, the source electrode of the twenty-ninth NMOS transistor is connected with the drain electrode of the thirty-fourth NMOS transistor, the gate electrode of the twenty-ninth NMOS transistor and the thirty-eleventh NMOS transistor are connected, and the connecting end of the twenty-sixth NMOS transistor is connected with the drain end of the twenty-ninth NMOS transistor The source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the drain of the thirty-fifth NMOS transistor, the gate of the thirty-second NMOS transistor, the connection end of the thirty-fifth NMOS transistor and the gate of the thirty-second NMOS transistor are connected, the source of the thirty-eleventh NMOS transistor and the drain of the thirty-sixth NMOS transistor are connected, the source of the thirty-second NMOS transistor and the drain of the thirty-seventh NMOS transistor are connected, the source of the thirty-third NMOS transistor, the source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor and the drain of the thirty-eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor and the gate of the thirty-fifth NMOS transistor are connected, and the connection end of the thirty-fourth NMOS transistor and the drain of the thirty-fifth NMOS transistor is the second inverting input end of the two-input NAND gate The gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, and the connection end of the thirty-sixth NMOS transistor and the gate of the thirty-seventh NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are all high-threshold NMOS transistors, and the threshold voltage is 0.489V. The four two-input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two-input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first control end of the first two-input nand gate and the connection end of the first control end of the second two-input xor gate are the first control end of the multiplication unit circuit and are used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the second control end of the multiplication unit circuit is the second control end of the multiplication unit circuit, the output end of the first two-input NAND gate, the first inverting input end of the third two-input NAND gate and the first inverting input end of the first two-input XOR gate are connected, the inverting output end of the first two-input NAND gate and the first input end of the third two-input NAND gate are connected with the first input end of the first two-input XOR gate, the second input end of the first two-input XOR gate and the second input end of the third two-input NAND gate and the input end of the third inverter are connected, the connection end of the first two-input XOR gate and the second input end of the third two-input NAND gate is the third input end of the multiplication unit circuit and is used for connecting a third multiplier, the second inverting input end of the first two-input XOR gate and the second inverting input end of the third two-input NAND gate are connected with the output end of the third inverter, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal output at a low order, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting product signals, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting inverted signals of the product signals, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, and the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit, and the inverted output end of the fourth two-input NAND gate is the inverted carry signal output end of the multiplication unit circuit and is used for outputting the inverted signal of the carry signal to the high order.
Compared with the prior art, the multiplication unit circuit has the advantages that the multiplication unit circuit is formed by two exclusive-OR gates, four NAND gates and four phase inverters, the multiplication unit circuit realizes one-time evaluation operation in one period, the multiplication unit circuit is divided into three stages in one period, namely a pre-charging stage, an evaluation operation stage and a discharging stage, the exclusive-OR gate and the NAND gate are used as two basic units of the multiplication unit circuit, the exclusive-OR gate and the NAND gate are realized by adopting the same circuit structure, the circuit structure can realize an exclusive-OR logic function and a NAND logic function respectively when the threshold voltage characteristics of MOS (metal oxide semiconductor) transistors in the same circuit structure are configured, the exclusive-OR gate is formed by a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor and an eighteenth NMOS transistor, and the differential pull-down network is formed by a ninth NMOS transistor, The differential pull-down network formed by the twenty-ninth NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-third NMOS transistor, the thirty-fourth NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor adopts a single-ended structure, and has smaller area overhead compared with a double-ended structure.
The second technical problem to be solved by the invention is to provide a multiplier which has small area and power consumption overhead, can simultaneously defend reverse engineering and DPA attack, and has high safety and threshold voltage characteristic.
The second technical solution adopted by the present invention to solve the above technical problems is: a multiplier utilizing threshold voltage characteristics comprises mxn multiplication unit circuits, wherein the value of m is equal to the number of digits of a multiplicand, the value of n is equal to the number of digits of the multiplicand, the mxn multiplication unit circuits are arranged according to n rows and m columns, and each multiplication unit circuit is respectively provided with a first input end, a second input end, a third input end, a first control end, a second control end, a low-order carry signal input end, a high-order carry signal output end and a product output end; the first control terminals of the mxn multiplication unit circuits are connected together, the connection terminal thereof is the first control terminal of the multiplier, and the second control terminals of the mxn multiplication unit circuits are connected together, the connection terminal thereof is the second control terminal of the multiplier, and the evaluation control signal is connected thereto, the first input terminals of the M multiplication unit circuits in the nth row are respectively connected to the nth data of the multiplier, N is 1, 2, …, N, the second input terminals of the N multiplication unit circuits in the mth column are respectively connected to the mth (M-1) th data of the multiplier, M is 1, 2, …, M, the third input terminals of the M multiplication unit circuits in the 1 st row are respectively connected to the signal 0, and the low carry signal input terminals of the N multiplication unit circuits in the mth column are respectively connected to the signal 0, the high carry signal output end of the multiplying unit circuit positioned in the N-th row and the K-th column is connected with the low carry signal input end of the multiplying unit circuit positioned in the N-th row and the K-1-th column, K is 2, 3, …, M, the high carry signal output end of the multiplying unit circuit positioned in the j-th row and the 1-th column is connected with the third input end of the multiplying unit circuit positioned in the j + 1-th row and the 1-th column, j is 1, 2, …, N-1, the product output end of the multiplying unit circuit positioned in the N-th row and the K-th column is connected with the third input end of the multiplying unit circuit positioned in the N-th row and the K + 1-th column, K is 1, 2, …, M-1, the product output end of the multiplying unit circuit positioned in the j-th row and the M-th column is the j-th output end of the multiplier, the j-th bit of the product is output end, the product output end of the multiplying unit circuit positioned in the N-th row and the M-th column is the N-1-th output end, outputting the (n-1 + M- (M-1) th bit of the product, wherein the high-order carry signal output end of the multiplication unit circuit positioned in the (n) th row and the (1) th column is the (n + M) th output end of the multiplier and outputs the (n + M) th bit of the product; each multiplication unit circuit comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, each two-input NOR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end, and each two-input exclusive-OR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end; each of the two-input exclusive-or gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a source of the ninth NMOS transistor, and a fourteenth NMOS transistor, and a gate of the first PMOS transistor is connected to a gate of the fourteenth NMOS transistor, The grid electrode of the second PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connecting end of the grid electrode of the second PMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input exclusive-OR gate, the drain electrode of the first PMOS tube and the source electrode of the fifth PMOS tube are connected, the drain electrode of the second PMOS tube and the source electrode of the sixth PMOS tube are connected, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube are connected, the connecting end of the third PMOS tube and the connecting end of the third PMOS tube are the inverted output end of the two-input exclusive-OR gate, the grid electrode of the fourth PMOS tube, the grid electrode of the seventh NMOS tube, the drain electrode of the fifth NMOS tube, The grid electrode of the seventh PMOS transistor, the grid electrode of the eighth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input exclusive or gate, the grid electrode of the fifth PMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the sixth PMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the seventh PMOS transistor, the drain electrode of the fifth NMOS transistor, the grid electrode of the eighth PMOS transistor and the grid electrode of the sixth NMOS transistor are connected, the drain electrode of the eighth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input exclusive or gate, the source electrode of the first NMOS transistor is grounded, the source electrode of the second NMOS transistor and the drain electrode of the seventh NMOS transistor are connected, the source electrode of the seventh NMOS transistor is grounded, and the source electrode of the third NMOS transistor and the drain electrode of the ninth NMOS transistor are connected, a source of the fourth NMOS transistor, a drain of the tenth NMOS transistor, a drain of the eleventh NMOS transistor, a drain of the twelfth NMOS transistor and a drain of the thirteenth NMOS transistor, a source of the fifth NMOS transistor and a drain of the eighth NMOS transistor are connected, a source of the eighth NMOS transistor is grounded, a source of the sixth NMOS transistor is grounded, a source of the ninth NMOS transistor and a drain of the fourteenth NMOS transistor are connected, a source of the tenth NMOS transistor and a drain of the fifteenth NMOS transistor are connected, a gate of the tenth NMOS transistor and a gate of the twelfth NMOS transistor are connected and a connection end thereof is a first inverting input end of the two-input xor gate, a source of the eleventh NMOS transistor and a drain of the sixteenth NMOS transistor are connected, a gate of the eleventh NMOS transistor and a connection end thereof is a first input end of the two-input xor gate, a source electrode of the twelfth NMOS transistor is connected with a drain electrode of the seventeenth NMOS transistor, a source electrode of the thirteenth NMOS transistor is connected with a drain electrode of the eighteenth NMOS transistor, a source electrode of the fourteenth NMOS transistor, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor, a source electrode of the seventeenth NMOS transistor, a source electrode of the eighteenth NMOS transistor and a drain electrode of the nineteenth NMOS transistor are connected, a source electrode of the nineteenth NMOS transistor is grounded, a gate electrode of the fifteenth NMOS transistor is connected with a gate electrode of the sixteenth NMOS transistor, and a connection end thereof is a second inverting input end of the two-input XOR gate, a gate electrode of the seventeenth NMOS transistor is connected with a gate electrode of the eighteenth NMOS transistor, and a connection end thereof is a second input end of the two-input XOR gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold NMOS transistors, the threshold voltage is 0.243V, the ninth NMOS transistor and the fourteenth NMOS transistor are sub-threshold transistors, and the threshold voltage is 0.367V, the tenth NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor and the eighteenth NMOS transistor are high-threshold NMOS transistors, and the threshold voltage is 0.489V; each of the two-input nand gates respectively comprises a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty-eleventh NMOS transistor, a thirty-second NMOS transistor, a thirty-third NMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor and a thirty-eighth NMOS transistor, wherein the source electrode of the ninth PMOS transistor, the source electrode of the tenth PMOS transistor, the source electrode of the eleventh PMOS transistor, the source electrode of the twelfth PMOS transistor, the fifteenth PMOS transistor, the source electrode of the sixteenth PMOS transistor, the sixteenth NMOS transistor, The gate of the twenty-eighth NMOS transistor and the gate of the thirty-third NMOS transistor are both connected to a power supply, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the twenty-first NMOS transistor and the gate of the twenty-fourth NMOS transistor are connected, and the connection end thereof is the first control end of the two-input nand gate, the drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor, the drain of the tenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the gate of the eleventh PMOS transistor, the gate of the twentieth NMOS transistor, the drain of the twelfth PMOS transistor, the drain of the twenty-first NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the twenty-second NMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the twenty-third NMOS transistor are connected, the drain of the eleventh PMOS transistor and the drain of the twenty-NMOS transistor are connected, and the connection end thereof is the second input nand gate, the drain of the twelfth PMOS transistor and the drain of the twenty-first NMOS transistor are connected The grid of the twelfth PMOS tube, the grid of the twenty-sixth NMOS tube, the grid of the fifteenth PMOS tube, the grid of the twenty-seventh NMOS tube and the grid of the thirty-eighth NMOS tube are connected, the connecting end of the second control end of the two-input NAND gate is the second control end of the two-input NAND gate, the grid of the thirteenth PMOS tube, the grid of the twenty-second NMOS tube, the drain of the fourteenth PMOS tube, the drain of the twenty-third NMOS tube, the drain of the fifteenth PMOS tube, the drain of the twenty-fourth NMOS tube, the grid of the sixteenth PMOS tube and the grid of the twenty-fifth NMOS tube are connected, the drain of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube are connected, the connecting end of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube is the output end of the two-input NAND gate, and the source of the twenty-NMOS tube is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-eleventh NMOS transistor and the drain electrode of the thirty-second NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, the source electrode of the twenty-eighth NMOS transistor and the drain electrode of the thirty-third NMOS transistor are connected, the source electrode of the twenty-ninth NMOS transistor is connected with the drain electrode of the thirty-fourth NMOS transistor, the gate electrode of the twenty-ninth NMOS transistor and the thirty-eleventh NMOS transistor are connected, and the connecting end of the twenty-sixth NMOS transistor is connected with the drain end of the twenty-ninth NMOS transistor The source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the drain of the thirty-fifth NMOS transistor, the gate of the thirty-second NMOS transistor, the connection end of the thirty-fifth NMOS transistor and the gate of the thirty-second NMOS transistor are connected, the source of the thirty-eleventh NMOS transistor and the drain of the thirty-sixth NMOS transistor are connected, the source of the thirty-second NMOS transistor and the drain of the thirty-seventh NMOS transistor are connected, the source of the thirty-third NMOS transistor, the source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor and the drain of the thirty-eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor and the gate of the thirty-fifth NMOS transistor are connected, and the connection end of the thirty-fourth NMOS transistor and the drain of the thirty-fifth NMOS transistor is the second inverting input end of the two-input NAND gate The gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, and the connection end of the thirty-sixth NMOS transistor and the gate of the thirty-seventh NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are all high-threshold NMOS transistors, and the threshold voltage is 0.489V. The four two-input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two-input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first control end of the first two-input nand gate and the connection end of the first control end of the second two-input xor gate are the first control end of the multiplication unit circuit and are used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the second control end of the multiplication unit circuit is the second control end of the multiplication unit circuit, the output end of the first two-input NAND gate, the first inverting input end of the third two-input NAND gate and the first inverting input end of the first two-input XOR gate are connected, the inverting output end of the first two-input NAND gate and the first input end of the third two-input NAND gate are connected with the first input end of the first two-input XOR gate, the second input end of the first two-input XOR gate and the second input end of the third two-input NAND gate and the input end of the third inverter are connected, the connection end of the first two-input XOR gate and the second input end of the third two-input NAND gate is the third input end of the multiplication unit circuit and is used for connecting a third multiplier, the second inverting input end of the first two-input XOR gate and the second inverting input end of the third two-input NAND gate are connected with the output end of the third inverter, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal output at a low order, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting product signals, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting inverted signals of the product signals, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, and the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit, and the inverted output end of the fourth two-input NAND gate is the inverted carry signal output end of the multiplication unit circuit and is used for outputting the inverted signal of the carry signal to the high order.
Compared with the prior art, the multiplier of the invention has the advantages that the integral framework is realized by adopting a grid-type laminated strip array structure, the structure is simple, the realization is easy, in addition, the regular layout structure can be realized, the VLSI realization is particularly suitable, in addition, the multiplication unit circuit forming the multiplier of the invention realizes one-time evaluation operation in one period, and the one period is divided into three stages, namely a pre-charging stage, an evaluation operation stage and a discharging stage, an XOR gate and an NAND gate are taken as two basic units of the multiplication unit circuit, the XOR gate and the NAND gate are realized by adopting the same circuit structure, the circuit structure can respectively realize an XOR logic function and an NAND logic function by configuring the threshold voltage characteristics of MOS tubes in the same circuit structure, and the XOR gate comprises a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube, The differential pull-down network formed by a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube and an eighteenth NMOS tube and the differential pull-down network formed by a NAND gate formed by a twenty eighth NMOS tube, a twenty ninth NMOS tube, a thirty eleventh NMOS tube, a thirty second NMOS tube, a thirty third NMOS tube, a thirty fourth NMOS tube, a thirty fifth NMOS tube, a thirty sixth NMOS tube and a thirty seventh NMOS tube all adopt a single-ended structure.
Drawings
FIG. 1 is a block diagram of a multiplication cell circuit using threshold voltage characteristics according to the present invention;
FIG. 2 is a circuit diagram of an XOR gate of the multiplier cell circuit/multiplier using threshold voltage characteristics according to the present invention;
FIG. 3 is a circuit diagram of the NAND gate of the multiplier/multiplier circuit using the threshold voltage characteristic according to the present invention;
FIG. 4 is a block diagram of a multiplier utilizing threshold voltage characteristics according to the present invention;
FIG. 5 is a timing diagram illustrating the operation of the XOR gate of the multiplier unit/multiplier using the threshold voltage characteristic according to the present invention;
FIG. 6 is a graph of a functional simulation of an XOR gate of a multiplier cell circuit/multiplier utilizing threshold voltage characteristics according to the present invention;
FIG. 7 is a simulated graph of power consumption of the XOR gate of the multiplier cell circuit/multiplier using threshold voltage characteristics according to the present invention;
FIG. 8 is a graph of a functional simulation of the NAND gate of the multiplier unit circuit/multiplier using threshold voltage characteristics according to the present invention;
FIG. 9 is a functional verification diagram of the multiplier utilizing threshold voltage characteristics according to the present invention;
fig. 10 is a power consumption simulation graph of the multiplier using the threshold voltage characteristic of the present invention.
Detailed Description
The invention discloses a multiplication unit circuit utilizing threshold voltage characteristics, which is described in further detail below with reference to the embodiment of the attached drawings.
Example (b): as shown in fig. 1, 2 and3, a multiplication unit circuit using threshold voltage characteristics includes a first inverter F1, a second inverter F2, a third inverter F3, a fourth inverter F4, four two-input nand gates with the same structure and two-input xor gates with the same structure, each two-input nor gate has a first input terminal, a first inverting input terminal, a second inverting input terminal, a first control terminal, a second control terminal, an output terminal and an inverting output terminal, and each two-input xor gate has a first input terminal, a first inverting input terminal, a second inverting input terminal, a first control terminal, a second control terminal, an output terminal and an inverting output terminal; each two-input exclusive-OR gate comprises a first PMOS tube P, a second PMOS tube P, a third PMOS tube P, a fourth PMOS tube P, a fifth PMOS tube P, a sixth PMOS tube P, a seventh PMOS tube P, an eighth PMOS tube P, a first NMOS tube N, a second NMOS tube N, a third NMOS tube N, a fourth NMOS tube N, a fifth NMOS tube N, a sixth NMOS tube N, a seventh NMOS tube N, an eighth NMOS tube N, a ninth NMOS tube N, a tenth NMOS tube N, an eleventh NMOS tube N, a twelfth NMOS tube N, a thirteenth NMOS tube N, a fourteenth NMOS tube N, a fifteenth NMOS tube N, a sixteenth NMOS tube N, a seventeenth NMOS tube N, an eighteenth NMOS tube N and a nineteenth NMOS tube N, a source electrode of the first PMOS tube P, a source electrode of the second PMOS tube P, a source electrode of the third PMOS tube P, a source electrode of the fourth PMOS tube P, a source electrode of the seventh PMOS tube P, a source electrode of the eighth PMOS tube P, a power supply of the fourteenth NMOS tube N and a grid electrode of the fourteenth NMOS tube N are all connected with a grid electrode of the fourth PMOS tube P, the grid of the first PMOS pipe P1, the grid of the second PMOS pipe P2, the grid of the second NMOS pipe N2 and the grid of the fifth NMOS pipe N5 are connected, the connection end of the grid of the second PMOS pipe P588 and the grid of the fifth NMOS pipe N5 is the first control end of the two-input exclusive-OR gate, the drain of the first PMOS pipe P1 is connected with the source of the fifth PMOS pipe P5, the drain of the second PMOS pipe P2 is connected with the source of the sixth PMOS pipe P6, the grid of the third PMOS pipe P3, the grid of the first NMOS pipe N1, the drain of the fourth PMOS pipe P4, the drain of the second NMOS pipe N2, the drain of the fifth PMOS pipe P5, the drain of the third NMOS pipe N3, the grid of the sixth PMOS pipe P6 and the grid of the fourth NMOS pipe N4 are connected, the drain of the third PMOS pipe P3 is connected with the drain of the first NMOS pipe N1, the connection end of the drain of the fourth PMOS pipe P24 and the grid of the seventh NMOS pipe N599 and the connection end of the grid of the eighth NMOS pipe N599 and the ninth input exclusive-or gate of the ninth NMOS pipe N19, the grid electrode of the fifth PMOS transistor P5, the grid electrode of the third NMOS transistor N3, the drain electrode of the sixth PMOS transistor P6, the drain electrode of the fourth NMOS transistor N4, the drain electrode of the seventh PMOS transistor P7, the drain electrode of the fifth NMOS transistor N5, the grid electrode of the eighth PMOS transistor P8 and the grid electrode of the sixth NMOS transistor N6 are connected, the drain electrode of the eighth PMOS transistor P8 and the drain electrode of the sixth NMOS transistor N6 are connected and the connection end is the output end of the two-input XOR gate, the source electrode of the first NMOS transistor N1 is grounded, the source electrode of the second NMOS transistor N2 and the drain electrode of the seventh NMOS transistor N7 are connected, the source electrode of the seventh NMOS transistor N7 is grounded, the source electrode of the third NMOS transistor N3 and the drain electrode of the ninth NMOS transistor N9 are connected, the source electrode of the fourth NMOS transistor N4, the drain electrode of the tenth NMOS transistor N10, the drain electrode of the eleventh NMOS transistor N56, the drain electrode of the twelfth transistor N53 and the thirteenth transistor N13 are connected, the drain electrode of the fifth NMOS transistor N13 and the drain electrode of the eighth NMOS transistor N867 are connected, a source of a ninth NMOS transistor N9 and a drain of a fourteenth NMOS transistor N14 are connected, a source of a tenth NMOS transistor N10 and a drain of a fifteenth NMOS transistor N15 are connected, a gate of a tenth NMOS transistor N10 and a gate of a twelfth NMOS transistor N12 are connected and a connection end thereof is a first inverting input end of a two-input xor gate, a source of an eleventh NMOS transistor N11 and a drain of a sixteenth NMOS transistor N16 are connected, a gate of an eleventh NMOS transistor N11 and a gate of a thirteenth NMOS transistor N13 are connected and a connection end thereof is a first input end of a two-input xor gate, a source of a twelfth NMOS transistor N12 and a drain of a seventeenth NMOS transistor N17 are connected, a source of a thirteenth NMOS transistor N13 and a drain of an eighteenth NMOS transistor N18 are connected, a source of a fourteenth NMOS transistor N14, a source of a fifteenth NMOS transistor, a source of a sixteenth NMOS transistor N16, a drain of a seventeenth NMOS transistor N17, a source of an eighteenth NMOS transistor N18 and a drain of the ninth NMOS transistor N19 are connected to ground, a ninth NMOS transistor N19, the grid electrode of the fifteenth NMOS transistor N15 is connected to the grid electrode of the sixteenth NMOS transistor, the connection end of the fifteenth NMOS transistor N15 is the second inverting input end of the two-input xor gate, the grid electrode of the seventeenth NMOS transistor N17 is connected to the grid electrode of the eighteenth NMOS transistor N18, the connection end of the seventeenth NMOS transistor N17 is the second input end of the two-input xor gate, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, the sixteenth NMOS transistor N16 and the seventeenth NMOS transistor N17 are all low-threshold NMOS transistors, the threshold voltage is 0.243V, the ninth NMOS transistor N9 and the fourteenth NMOS transistor N14 are all sub-threshold transistors, the threshold voltage is 0.367V, the tenth NMOS transistor N10, the thirteenth NMOS transistor N13, the fifteenth NMOS transistor N15 and the eighteenth NMOS transistor N18 are all high-threshold NMOS transistors, and the threshold voltage is 0.489V; each two-input nand gate comprises a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P12, a fourteenth PMOS transistor P12, a fifteenth PMOS transistor P12, a sixteenth PMOS transistor P12, a twentieth NMOS transistor N12, a twenty-first NMOS transistor N12, a twenty-second NMOS transistor N12, a twenty-third NMOS transistor N12, a twenty-fourth NMOS transistor N12, a twenty-fifth NMOS transistor N12, a twenty-sixth NMOS transistor N12, a twenty-seventh NMOS transistor N12, a twenty-eighth NMOS transistor N12, a twenty-ninth NMOS transistor N12, a thirty-eleventh NMOS transistor N12, a thirty-second NMOS transistor N12, a thirty-third NMOS transistor N12, a thirty-fourth NMOS transistor N12, a thirty-fifth NMOS transistor N12, a sixth NMOS transistor P12, a fifteenth NMOS transistor P12, a source P12, a twelfth NMOS transistor P12, a source P12, a thirty source P12, a source P of the ninth NMOS transistor P12, a thirty, The source of the sixteenth PMOS tube P16, the gate of the twenty-eighth NMOS tube N28 and the gate of the thirty-third NMOS tube N33 are all connected to a power supply, the gate of the ninth PMOS tube P9, the gate of the tenth PMOS tube P10, the gate of the twenty-first NMOS tube N21 and the gate of the twenty-fourth NMOS tube N24 are connected and the connection end is the first control end of a two-input NAND gate, the drain of the ninth PMOS tube P9 is connected with the source of the thirteenth PMOS tube P13, the drain of the tenth PMOS tube P10 is connected with the source of the fourteenth PMOS tube P14, the gate of the eleventh PMOS tube P11, the gate of the twentieth NMOS tube N20, the drain of the twelfth PMOS tube P12, the drain of the twenty-first NMOS tube N21, the drain of the thirteenth PMOS tube P13, the drain of the twenty-second NMOS tube N22, the gate of the fourteenth PMOS tube P14 and the gate of the twenty-third NMOS tube N23, the drain of the eleventh PMOS tube N20 is connected with the drain of the opposite-phase NMOS tube N11 and the connection end is connected with the input NAND gate of the twenty-input NAND gate, the grid of a twelfth PMOS tube P12, the grid of a twenty-sixth NMOS tube N26, the grid of a fifteenth PMOS tube P15, the grid of a twenty-seventh NMOS tube N27 and the grid of a thirty-eighth NMOS tube N38 are connected, the connection ends of the grid of the thirteenth PMOS tube P13, the grid of a twenty-second NMOS tube N22, the drain of a fourteenth PMOS tube P14, the drain of a twenty-third NMOS tube N23, the drain of a fifteenth PMOS tube P15, the drain of a twenty-fourth NMOS tube N24, the grid of a sixteenth PMOS tube P16 and the grid of a twenty-fifth NMOS tube N25 are connected, the drain of a sixteenth PMOS tube P16 and the drain of a twenty-fifth NMOS tube N25 are connected, the connection ends of the two-input NAND gates are connected, the source of the twentieth NMOS tube N20 is grounded, the source of the twenty-first NMOS tube N21 and the drain of the twenty-sixth NMOS tube N26 are connected, the source of the twenty-eighth NMOS tube N4642 is connected to the source of the twenty-eighth NMOS tube N28, a source of a twenty-third NMOS transistor N23, a drain of a twenty-ninth NMOS transistor N29, a drain of a thirty-second NMOS transistor N30, a drain of a thirty-first NMOS transistor N31 and a drain of a thirty-second NMOS transistor N32, a source of a twenty-fourth NMOS transistor N24 and a drain of a twenty-seventh NMOS transistor N27, a source of a twenty-seventh NMOS transistor N27 is grounded, a source of a twenty-fifth NMOS transistor N25 is grounded, a source of a twenty-eighth NMOS transistor N28 and a drain of a thirty-third NMOS transistor N33 are connected, a source of a twenty-ninth NMOS transistor N29 and a drain of a thirty-fourth NMOS transistor N34 are connected, a gate of the twenty-ninth NMOS transistor N29 and a gate of a thirty-first NMOS transistor N31 are connected and a connection end thereof is a first inverting input terminal of a two-input nand gate, a source of a thirty-NMOS transistor N30 and a drain of a thirty-fifth NMOS transistor N35 are connected and a gate connection end thereof is a first inverting input terminal of a thirty-second nand gate of a thirty-second NMOS transistor N32, a source electrode of a thirty-first NMOS transistor N31 is connected with a drain electrode of a thirty-sixth NMOS transistor N36, a source electrode of a thirty-second NMOS transistor N32 is connected with a drain electrode of a thirty-seventh NMOS transistor N37, a source electrode of a thirty-third NMOS transistor N33, a source electrode of a thirty-fourth NMOS transistor N34, a source electrode of a thirty-fifth NMOS transistor N35, a source electrode of a thirty-sixth NMOS transistor N36, a source electrode of a thirty-seventh NMOS transistor N37 and a drain electrode of a thirty-eighth NMOS transistor N38 are connected, a source electrode of a thirty-eighth NMOS transistor N38 is grounded, a gate electrode of a thirty-fourth NMOS transistor N34 and a gate electrode of a thirty-fifth NMOS transistor N35 are connected and a connection end of the second inverting input end of a two-input NAND gate, a gate electrode of a thirty-sixth NMOS transistor N36 and a gate electrode of a thirty-seventh NMOS transistor N37 are connected and a connection end of a second input NAND gate, a twenty-ninth NMOS transistor N29 and a thirty-fourth NMOS transistor N34 are both low threshold value NMOS transistors, a voltage threshold value is low, a twenty-threshold value V92 and a twenty-eighth NMOS transistor N, and the threshold voltage is 0.367V, the thirty-first NMOS transistor N30, the thirty-first NMOS transistor N31, the thirty-second NMOS transistor N32, the thirty-fifth NMOS transistor N35, the thirty-sixth NMOS transistor N36 and the thirty-seventh NMOS transistor N37 are all high-threshold NMOS transistors, and the threshold voltage is 0.489V. Four two-input NAND gates are respectively called a first two-input NAND gate NAND1, a second two-input NAND gate NAND2, a third two-input NAND gate NAND3 and a fourth two-input NAND gate NAND4, two-input XOR gates are respectively called a first two-input XOR1 and a second two-input XOR2, a first input terminal of the first two-input NAND gate NAND1 is connected with an input terminal of a first inverter F1, a connection terminal thereof is a first input terminal of the multiplying unit circuit for accessing a first multiplier a, a first inverting input terminal of the first two-input NAND gate NAND1 is connected with an output terminal of the first inverter F1, a second input terminal of the first two-input NAND gate 1 is connected with an input terminal of a second inverter F2, a connection terminal thereof is a second input terminal of the multiplying unit circuit for accessing a second multiplier B, a second inverting input terminal of the first two-input NAND gate 1 is connected with an output terminal of the second inverter F2, a first control end of a first two-input NAND gate NAND1, a first control end of a second two-input NAND gate NAND2, a first control end of a third two-input NAND gate NAND3, a first control end of a fourth two-input NAND gate NAND4, a first control end of a first two-input XOR gate XOR1 and a first control end of a second two-input XOR gate XOR2 are connected, and connection ends of the first control end and the first control end are first control ends of a multiplication unit circuit and used for connecting a discharge control signal discharge, a second control end of the first two-input NAND gate 1, a second control end of the second two-input NAND gate 2, a second control end of the third two-input NAND gate 3, a second control end of the fourth two-input NAND gate 4, a second control end of the first two-input XOR gate XOR1 and a second control end of the second two-input XOR gate 2 are connected, and connection ends of the second control end and the multiplication unit circuit are second control ends of the multiplication unit circuit and used for connecting an evaluation control signal NAND gate 1 and the first input NAND gate XOR gate 1 and the, A first inverting input terminal of a third two-input NAND gate NAND3 is connected with a first inverting input terminal of a first two-input exclusive-or gate XOR1, an inverting output terminal of the first two-input NAND gate NAND1, a first input terminal of the third two-input NAND gate NAND3 is connected with a first input terminal of a first two-input exclusive-or gate XOR1, a second input terminal of the first two-input exclusive-or gate XOR1 and a second input terminal of a third two-input NAND gate NAND3 are connected with an input terminal of a third inverter F3, and connection terminals thereof are third input terminals of the multiplication unit circuit for connecting a third multiplier C, a second inverting input terminal of a first two-input exclusive-or gate XOR1, a second inverting input terminal of a third two-input NAND gate 3 and an output terminal of a third inverter F3, an output terminal of the first two-input exclusive-or gate XOR1, a first input terminal of the second two-input exclusive-or gate XOR2 and a first input terminal of the second exclusive-or gate NAND gate 2, the inverting output terminal of the first two-input exclusive or gate XOR1, the first inverting input terminal of the second two-input exclusive or gate XOR2 and the first inverting input terminal of the second two-input NAND gate NAND2 are connected, the second input terminal of the second two-input exclusive or gate XOR2, the second input terminal of the second two-input NAND gate NAND2 and the input terminal of the fourth inverter F4 are connected and their connection terminals are the low-order carry signal input terminal of the multiplication unit circuit for accessing the carry signal CI of the low-order output, the second inverting input terminal of the second two-input exclusive or gate XOR2, the second inverting input terminal of the second two-input NAND gate NAND2 and the output terminal of the fourth inverter F4 are connected, the output terminal of the second two-input exclusive or gate XOR2 is the output terminal of the multiplication unit circuit for outputting the product signal, the inverting output terminal of the second two-input exclusive or gate XOR2 is the inverting output terminal of the multiplication unit circuit for outputting the inverted signal of the product signal, the output end of the second two-input NAND gate NAND2 is connected with the first inverting input end of the fourth two-input NAND gate NAND4, the inverting output end of the second two-input NAND gate NAND2 is connected with the first input end of the fourth two-input NAND gate NAND4, the output end of the third two-input NAND gate NAND3 is connected with the second inverting input end of the fourth two-input NAND gate NAND4, the inverting output end of the third two-input NAND gate NAND3 is connected with the second input end of the fourth two-input NAND gate 4, the output end of the fourth two-input NAND gate 4 is the carry signal output end of the multiplication unit circuit and is used for outputting the carry signal CO to the high bit, and the inverting output end of the fourth two-input NAND gate 4 is the inverting carry signal output end of the multiplication unit circuit and is used for outputting the.
The invention also discloses a multiplier realized by adopting the multiplication unit circuit, and the multiplier utilizing the threshold voltage characteristic of the invention is further described in detail by combining the embodiment of the attached drawings.
Example (b): as shown in fig. 4, 2 and3, a multiplier using threshold voltage characteristics includes m × n multiplication unit circuits, where m is equal to the number of multiplicand bits, and the multiplicand is an m-bit binary number Xm-1Xm-2...X0The value of n is equal to the number of bits of a multiplier, which is n-bit binary number Yn-1Yn-2…Y0The m multiplied by n multiplication unit circuits are arranged according to n rows and m columns, and each multiplication unit circuit is respectively provided with a first input end, a second input end, a third input end, a first control end, a second control end, a low-order carry signal input end, a high-order carry signal output end and a product output end; the first control ends of the m × n multiplication unit circuits are connected together, the connection end of the first control end is the first control end of the multiplier and is used for accessing a discharge control signal discharge, and the second control ends of the m × n multiplication unit circuitsThe first input ends of the m multiplication unit circuits in the Nth row are respectively connected with the Nth data Y of the multiplierN-1N is 1, 2, …, N, and the M- (M-1) th bit data X of multiplicand is connected to the second input end of N multiplication unit circuits in M-th columnm-(M-1)-1M is 1, 2, …, M, the third input terminals of the M multiplication unit circuits in the 1 st row are respectively connected with signal 0, the low carry signal input terminals of the N multiplication unit circuits in the M th column are respectively connected with signal 0, the high carry signal output terminal of the multiplication unit circuit in the N th row and the K th column is connected with the low carry signal input terminal of the multiplication unit circuit in the N th row and the K-1 st column, K is 2, 3, …, M, the high carry signal output terminal of the multiplication unit circuit in the j th row and the 1 st column is connected with the third input terminal of the multiplication unit circuit in the j +1 th row and the 1 st column, j is 1, 2, …, N-1, the product output terminal of the multiplication unit circuit in the N th column in the N th row is connected with the third input terminal of the multiplication unit circuit in the N th row and the K +1 st column, K is 1, 2, … m-1, the product output end of the multiplication unit circuit positioned at the jth row and mth column is the jth output end of the multiplier, and the jth bit Z of the product is outputj-1The product output end of the multiplication unit circuit positioned in the nth row and the mth column is the (n-1 + M- (M-1) th) output end of the multiplier, and outputs the (n-1 + M- (M-1) th bit Z of the productn-1+m-(M-1)-1The high-order carry signal output end of the multiplication unit circuit positioned in the n-th row and the 1 st column is the n + m output ends of the multiplier and outputs the n + m Z bits of the productn+m-1(ii) a Each multiplication unit circuit comprises a first phase inverter F1, a second phase inverter F2, a third phase inverter F3, a fourth phase inverter F4, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, each two-input NOR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end, and each two-input exclusive-OR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end; each twoThe input XOR gate comprises a first PMOS transistor P, a second PMOS transistor P, a third PMOS transistor P, a fourth PMOS transistor P, a fifth PMOS transistor P, a sixth PMOS transistor P, a seventh PMOS transistor P, an eighth PMOS transistor P, a first NMOS transistor N, a second NMOS transistor N, a third NMOS transistor N, a fourth NMOS transistor N, a fifth NMOS transistor N, a sixth NMOS transistor N, a seventh NMOS transistor N, an eighth NMOS transistor N, a ninth NMOS transistor N, a tenth NMOS transistor N, an eleventh NMOS transistor N, a twelfth NMOS transistor N, a thirteenth NMOS transistor N, a fourteenth NMOS transistor N, a fifteenth NMOS transistor N, a sixteenth NMOS transistor N, a seventeenth NMOS transistor N, an eighteenth NMOS transistor N and a nineteenth NMOS transistor N, respectively, the source of the first PMOS transistor P, the source of the second PMOS transistor P, the source of the third PMOS transistor P, the source of the fourth PMOS transistor P, the source of the seventh PMOS transistor P, the source of the eighth PMOS transistor P, the source of the ninth NMOS power supply N and the fourteenth NMOS power supply N are connected to the gate of the fourth PMOS transistor N, the grid of the first PMOS pipe P1, the grid of the second PMOS pipe P2, the grid of the second NMOS pipe N2 and the grid of the fifth NMOS pipe N5 are connected, the connection end of the grid of the second PMOS pipe P588 and the grid of the fifth NMOS pipe N5 is the first control end of the two-input exclusive-OR gate, the drain of the first PMOS pipe P1 is connected with the source of the fifth PMOS pipe P5, the drain of the second PMOS pipe P2 is connected with the source of the sixth PMOS pipe P6, the grid of the third PMOS pipe P3, the grid of the first NMOS pipe N1, the drain of the fourth PMOS pipe P4, the drain of the second NMOS pipe N2, the drain of the fifth PMOS pipe P5, the drain of the third NMOS pipe N3, the grid of the sixth PMOS pipe P6 and the grid of the fourth NMOS pipe N4 are connected, the drain of the third PMOS pipe P3 is connected with the drain of the first NMOS pipe N1, the connection end of the drain of the fourth PMOS pipe P24 and the grid of the seventh NMOS pipe N599 and the connection end of the grid of the eighth NMOS pipe N599 and the ninth input exclusive-or gate of the ninth NMOS pipe N19, the grid electrode of a fifth PMOS tube P5, the grid electrode of a third NMOS tube N3, the drain electrode of a sixth PMOS tube P6, the drain electrode of a fourth NMOS tube N4, the drain electrode of a seventh PMOS tube P7, the drain electrode of a fifth NMOS tube N5, the grid electrode of an eighth PMOS tube P8 and the grid electrode of a sixth NMOS tube N6 are connected, the drain electrode of an eighth PMOS tube P8 and the drain electrode of a sixth NMOS tube N6 are connected, the connection end of the eighth PMOS tube P8 and the drain electrode of the sixth NMOS tube N6 is the output end of a two-input exclusive-OR gate, the source electrode of the first NMOS tube N1 is grounded, the source electrode of the second NMOS tube N2 and the drain electrode of the seventh NMOS tube N7, and the drain electrode ofA source electrode is grounded, a source electrode of a third NMOS transistor N3 is connected with a drain electrode of a ninth NMOS transistor N9, a source electrode of a fourth NMOS transistor N4, a drain electrode of a tenth NMOS transistor N10, a drain electrode of an eleventh NMOS transistor N11, a drain electrode of a twelfth NMOS transistor N12 is connected with a drain electrode of a thirteenth NMOS transistor N13, a source electrode of a fifth NMOS transistor N5 is connected with a drain electrode of an eighth NMOS transistor N8, a source electrode of an eighth NMOS transistor N8 is grounded, a source electrode of a sixth NMOS transistor N6 is grounded, a source electrode of a ninth NMOS transistor N9 is connected with a drain electrode of a fourteenth NMOS transistor N14, a source electrode of a tenth NMOS transistor N10 is connected with a drain electrode of a fifteenth NMOS transistor N15, a gate electrode of a tenth NMOS transistor N10 is connected with a gate electrode of the twelfth NMOS transistor N12, a connection end of the tenth NMOS transistor N10 is a first inverting input end of a two-input exclusive OR gate, a source electrode of an eleventh NMOS transistor N11 is connected with a sixteenth NMOS transistor N16, a thirteenth gate electrode of the eleventh NMOS transistor N11 is connected with a second input end of a thirteenth NMOS gate input terminal, a source of a twelfth NMOS transistor N12 is connected with a drain of a seventeenth NMOS transistor N17, a source of a thirteenth NMOS transistor N13 is connected with a drain of an eighteenth NMOS transistor N18, a source of a fourteenth NMOS transistor N14, a source of a fifteenth NMOS transistor, a source of a sixteenth NMOS transistor N16, a source of a seventeenth NMOS transistor N17, a source of an eighteenth NMOS transistor N18 and a drain of a nineteenth NMOS transistor N19 are connected, a source of a nineteenth NMOS transistor N19 is grounded, a gate of the fifteenth NMOS transistor N15 is connected with a gate of a sixteenth NMOS and a connection end thereof is a second inverting input end of a two-input XOR gate, a gate of the seventeenth NMOS transistor N17 is connected with a gate of the eighteenth NMOS transistor N18 and a connection end thereof is a second input end of the two-input XOR gate, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a sixteenth NMOS transistor N16 and a seventeenth NMOS transistor N17 are all low-threshold voltage transistors, and a fourteenth NMOS transistor N14 and a fourteenth NMOS 9, the threshold voltage is 0.367V, the tenth NMOS transistor N10, the thirteenth NMOS transistor N13, the fifteenth NMOS transistor N15 and the eighteenth NMOS transistor N18 are all high-threshold NMOS transistors, and the threshold voltage is 0.489V; each two-input nand gate comprises a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a twentieth NMOS tube N20, a twenty-first NMOS tube N21, a twenty-second NMOS tube N22, a twenty-second NMOS tube N10A third NMOS transistor N23, a twenty-fourth NMOS transistor N24, a twenty-fifth NMOS transistor N25, a twenty-sixth NMOS transistor N26, a twenty-seventh NMOS transistor N27, a twenty-eighth NMOS transistor N28, a twenty-ninth NMOS transistor N29, a thirty-NMOS transistor N30, a thirty-eleventh NMOS transistor N31, a thirty-second NMOS transistor N32, a thirty-third NMOS transistor N33, a thirty-fourth NMOS transistor N34, a thirty-fifth NMOS transistor N35, a thirty-sixth NMOS transistor N36, a thirty-seventh NMOS transistor N37 and a thirty-eighth NMOS transistor N38, a source of a ninth PMOS transistor P38, a source of a tenth PMOS transistor P38, a source of an eleventh PMOS transistor P38, a source of a twelfth PMOS transistor P38, a source of a fifteenth PMOS transistor P38, a source of a sixteenth PMOS transistor P38, a source of a twenty-eighth gate NMOS transistor N38 and a thirty-gate power supply N38 of the third NMOS transistor N38, a twenty-gate control input terminal of the twenty-NMOS transistor N38 and a twenty-gate control input terminal of the NMOS transistor P38, the drain of a ninth PMOS tube P9 is connected with the source of a thirteenth PMOS tube P13, the drain of a tenth PMOS tube P10 is connected with the source of a fourteenth PMOS tube P14, the gate of the eleventh PMOS tube P11, the gate of a twentieth NMOS tube N20, the drain of a twelfth PMOS tube P12, the drain of a twenty-first NMOS tube N21, the drain of the thirteenth PMOS tube P13, the drain of a twenty-second NMOS tube N22, the gate of the fourteenth PMOS tube P14 and the gate of a twenty-third NMOS tube N23, the drain of the eleventh PMOS tube P11 is connected with the drain of the twentieth NMOS tube N20, the connection end of the eleventh PMOS tube P12, the gate of the twenty-sixth NMOS tube N26, the gate of the fifteenth PMOS tube P15, the gate of the twenty-seventh NMOS tube N27 and the gate of the thirty-eighth NMOS tube N38 are connected, the connection end of the thirteenth NMOS tube P11, the gate of the twenty-second NMOS tube N22 and the gate of the twenty-third NMOS tube N13, The drain of a fourteenth PMOS tube P14, the drain of a twenty-third NMOS tube N23, the drain of a fifteenth PMOS tube P15, the drain of a twenty-fourth NMOS tube N24, the gate of a sixteenth PMOS tube P16 and the gate of a twenty-fifth NMOS tube N25 are connected, the drain of a sixteenth PMOS tube P16 and the drain of a twenty-fifth NMOS tube N25 are connected, the connecting end of the sixteenth PMOS tube P16 and the drain of the twenty-fifth NMOS tube N25 is the output end of a two-input NAND gate, the source of a twentieth NMOS tube N20 is grounded, the source of a twenty-first NMOS tube N21 and the twenty-sixth NMOS tube N26, the source of a twenty-sixth NMOS transistor N26 is grounded, the source of a twenty-second NMOS transistor N22 is connected to the drain of a twenty-eighth NMOS transistor N28, the source of a twenty-third NMOS transistor N23, the drain of a twenty-ninth NMOS transistor N29, the drain of a thirty-second NMOS transistor N30, the drain of a thirty-eleventh NMOS transistor N31 is connected to the drain of a thirty-second NMOS transistor N32, the source of a twenty-fourth NMOS transistor N24 is connected to the drain of a twenty-seventh NMOS transistor N27, the source of a twenty-seventh NMOS transistor N27 is grounded, the source of a twenty-fifth NMOS transistor N25 is grounded, the source of a twenty-eighth NMOS transistor N28 is connected to the drain of a thirty-third NMOS transistor N33, the source of a twenty-ninth NMOS transistor N29 is connected to the drain of a thirty-fourth NMOS transistor N34, the gate of the twenty-ninth NMOS transistor N6 is connected to the drain of a thirty-first NMOS transistor N31, and the connecting terminal of the thirty-second NMOS transistor N30 is connected to the negative input terminal of a thirty-fifth NMOS transistor N35, the gate of the thirty-second NMOS transistor N30 is connected with the gate of the thirty-second NMOS transistor N32, the connection end of the thirty-second NMOS transistor N32 is the first input end of a two-input NAND gate, the source of the thirty-first NMOS transistor N31 is connected with the drain of the thirty-sixth NMOS transistor N36, the source of the thirty-second NMOS transistor N32 is connected with the drain of the thirty-seventh NMOS transistor N37, the source of the thirty-third NMOS transistor N33, the source of the thirty-fourth NMOS transistor N34, the source of the thirty-fifth NMOS transistor N35, the source of the thirty-sixth NMOS transistor N36, the source of the thirty-seventh NMOS transistor N37 and the drain of the thirty-eighth NMOS transistor N38 are connected, the source of the thirty-eighth NMOS transistor N38 is grounded, the gate of the thirty-fourth NMOS transistor N34 is connected with the gate of the thirty-fifth NMOS transistor N35, the connection end of the thirty-second input NAND gate is the second inverted input NAND gate, the thirty-sixth NMOS transistor N36 and the thirty-second NMOS transistor N37 are both connected with the second input end of the thirty-low NMOS transistor N68692, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor N28 and the thirty-third NMOS transistor N33 are sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-fifth NMOS transistor N30, the thirty-eleventh NMOS transistor N31, the thirty-second NMOS transistor N32, the thirty-fifth NMOS transistor N35, the thirty-sixth NMOS transistor N36 and the thirty-seventh NMOS transistor N37 are high-threshold NMOS transistors, and the threshold voltage is 0.489V. The four two-input NAND gates are respectively called as a first two-input NAND gateThe two-input exclusive-or gates are respectively called a first two-input exclusive-or gate XOR1 and a second two-input exclusive-or gate XOR2, a first input end of the first two-input NAND gate NAND1 is connected with an input end of a first inverter F1, a connecting end of the first two-input NAND gate XOR1 is a first input end of the multiplication unit circuit, a first inverting input end of the first two-input NAND gate 1 is connected with an output end of the first inverter F1, a second input end of the first two-input NAND gate 1 is connected with an input end of a second inverter F2, a connecting end of the first two-input NAND gate F2 is a second input end of the multiplication unit circuit, a second inverting input end of the first two-input NAND gate 1 is connected with an output end of the second inverter F2, a first control NAND end of the first two-input NAND gate 1, a first control end of the second NAND gate 2, a first control end of the third input NAND gate 3, A first control terminal of a fourth two-input NAND gate NAND4, a first control terminal of a first two-input XOR1 and a first control terminal of a second two-input XOR gate XOR2 are connected and the connection terminals thereof are the first control terminal of the multiplication unit circuit, a second control terminal of the first two-input NAND gate NAND1, a second control terminal of the second two-input NAND gate NAND2, a second control terminal of the third two-input NAND gate NAND3, a second control terminal of the fourth two-input NAND gate NAND4, a second control terminal of the first two-input XOR gate XOR1 and a second control terminal of the second two-input XOR gate 2 are connected and the connection terminals thereof are the second control terminal of the multiplication unit circuit, an output terminal of the first two-input NAND gate NAND1, a first inverting input terminal of the third two-input NAND gate 3 and a first inverting input terminal of the first two-input XOR gate XOR1 are connected, a first inverting output terminal of the first two-input NAND gate 3, a first inverting terminal of the second input NAND gate XOR 3873742 and a first inverting input terminal of the first two-input XOR gate 53984 are connected, a second input end of the first two-input exclusive-or gate XOR1, a second input end of the third two-input NAND gate NAND3 and an input end of the third inverter F3 are connected, and connection ends thereof are a second inversion input end of the first two-input exclusive-or gate XOR1, a second inversion input end of the third two-input NAND gate NAND3 and an output end of the third inverter F3 of the multiplication unit circuit, and the first two-input exclusive-or gate XOR1, the second two-input NAND gate NAND3 and the input end of the third inverter F39An output terminal of the two-input exclusive or gate XOR1, a first input terminal of the second input exclusive or gate XOR2 and a first input terminal of the second input NAND gate NAND2 are connected, an inverting output terminal of the first two-input exclusive or gate XOR1, a first inverting input terminal of the second input exclusive or gate XOR2 and a first inverting input terminal of the second input NAND gate NAND2 are connected, a second input terminal of the second two-input exclusive or gate XOR2, a second input terminal of the second input NAND gate NAND2 and an input terminal of the fourth inverter F4 are connected and a connection terminal thereof is a low carry signal input terminal of the multiplication unit circuit, a second inverting input terminal of the second input exclusive or gate XOR2, a second inverting input terminal of the second input NAND gate 2 and an output terminal of the fourth inverter F4, an output terminal of the second input exclusive or gate 2 is an output terminal of the multiplication unit circuit for outputting a product signal, an inverting output terminal of the second input exclusive or gate XOR gate 2 is an inverting output terminal of the multiplication unit, the output end of the second two-input NAND gate NAND2 is connected with the first inverting input end of the fourth two-input NAND gate NAND4, the inverting output end of the second two-input NAND gate NAND2 is connected with the first input end of the fourth two-input NAND gate NAND4, the output end of the third two-input NAND gate NAND3 is connected with the second inverting input end of the fourth two-input NAND gate NAND4, the inverting output end of the third two-input NAND gate NAND3 is connected with the second input end of the fourth two-input NAND gate 4, the output end of the fourth two-input NAND gate 4 is the carry signal output end of the multiplication unit circuit, and the inverting output end of the fourth two-input NAND gate 4 is the inverting carry signal output end of the multiplication unit circuit.
The multiplier of the invention realizes the multiplication operation of binary number, and the working principle is as follows: the multiplicand X is m bits and is marked as Xm-1Xm-2...X0The multiplier Y is n bits and is marked as Yn-1Yn-2… Y0, the product is m + n bit, and is denoted as Zm+n-1Zm+n-2…Z0The m-bit multiplicand and the n-bit multiplier are each anded to obtain a partial product having n bits m, and an adder array is used (since the multiplication unit circuit is mainly composed of an adder circuit, the multiplication unit circuit array stores the partial productIn an adder array) to add n partial products to obtain products, and the specific implementation of the multiplier is divided into three steps of partial product generation, partial product compression and final addition. Xm-1Xm-2...X0、Yn-1Yn-2… Y0 is an input numerical signal, the evaluation control signal eval and the discharge control signal discharge are input two control signals, Zm+n-1Zm+n-2…Z0Is the output signal. One evaluation operation is realized in one period, the period is divided into three stages, and when the eval and discharge signals are 01 and 00, the circuit enters a pre-charging stage; when the eval and discharge signals are 10, the circuit realizes evaluation operation and realizes the function of the circuit; when the eval and discharge signals are 11, the circuit enters a discharge state and is ready for the next evaluation operation. In the multiplier, two input exclusive-OR gates and a NAND gate have the same circuit structure, different logic functions are realized only by configuring the threshold voltage of an MOS tube, the output is discharged from a pre-charging high level to a low level in each working period, the consumed energy is constant, the characteristic that the energy consumption and the processed data are mutually independent is realized, and the multiplier has the characteristic of resisting DPA attack while defending against reverse engineering attack.
The operation timing diagram of the exclusive or gate of the multiplier unit circuit/multiplier using the threshold voltage characteristic of the present invention is shown in fig. 5. The grid electrode of the third PMOS transistor, the grid electrode of the first NMOS transistor, the drain electrode of the fourth PMOS transistor, the drain electrode of the second NMOS transistor, the drain electrode of the fifth PMOS transistor, the drain electrode of the third NMOS transistor, the connection node of the grid electrode of the sixth PMOS transistor and the grid electrode of the fourth NMOS transistor is X, the connection node of the grid electrode of the fifth PMOS transistor P5, the grid electrode of the third NMOS transistor N3, the drain electrode of the sixth PMOS transistor P6, the drain electrode of the fourth NMOS transistor N4, the drain electrode of the seventh PMOS transistor P7, the drain electrode of the fifth NMOS transistor N5, the grid electrode of the eighth PMOS transistor P7 and the grid electrode of the sixth NMOS transistor N6 is Y, and analyzing fig. 5 shows that the working process of the exclusive or gate is divided into three stages of pre-charging, evaluation and discharging, and when the evaluation control signal eval and the discharge control signal discharge are both low level 0 or the evaluation control signal eval and the discharge control signal is low level 0 and the discharge control signal discharge1, the exclusive or gate enters the third PMOS transistor P4 and the fourth PMOS transistor P1The seven PMOS tubes P7 are all turned on, X, Y is charged to high level, and then the first phase inverter consisting of the third PMOS tube and the first NMOS tube and the second phase inverter consisting of the eighth PMOS tube and the sixth NMOS tube respectively operate and output
Figure BDA0002279334390000231
And OUT are both pulled low; when eval becomes high level and discharge is low level 0, the fourth PMOS transistor P4 and the seventh PMOS transistor P7 are turned off, precharge is finished, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, and the nineteenth NMOS transistor N19 is turned on, the circuit enters the evaluation stage, at this time, a is 1, B is 1, the thirteenth NMOS transistor N13 and the eighteenth NMOS transistor N18 in the pull-down network are turned on, the gate voltages of the third NMOS transistor N3 and the fourth NMOS transistor N4 are precharged to high level before, so that currents I1 and I2 flow through, since the ninth NMOS transistor N9 and the fourteenth NMOS transistor N14 are subthreshold transistors and are in the normally-on state, the sense amplifier composed of the fifth PMOS transistor, the sixth PMOS transistor, the third NMOS transistor and the fourth NMOS transistor amplifies the current difference, X rate is discharged to low level first, and passes through the operational NMOS transistor composed of the third PMOS transistor and the first NMOS transistor,
Figure BDA0002279334390000241
when the voltage is pulled to a high level, the seventh PMOS tube P7 is conducted, Y still keeps the high level, and OUT is a low level; when eval and discharge are simultaneously high level 1, at this time, the second NMOS transistor N2, the fifth NMOS transistor N5, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the circuit enters a discharging stage, X, Y discharges to a low level, and then the first inverter formed by the third PMOS transistor and the first NMOS transistor and the second inverter formed by the eighth PMOS transistor and the sixth NMOS transistor respectively operate, so as to obtain OUT and discharge
Figure BDA0002279334390000242
All are pulled to high level, and one working period is finished, so that the exclusive-or logic function is realized.
The functional simulation graph of the exclusive or gate of the multiplier unit circuit/multiplier using the threshold voltage characteristic of the present invention is shown in fig. 6, and it can be seen from an analysis of fig. 6 that: the exclusive-or gate circuit provided by the invention traverses all input conditions and has a correct logic function.
The simulation graph of the power consumption of the exclusive or gate of the multiplier unit circuit/multiplier using the threshold voltage characteristic of the present invention is shown in fig. 7, and it can be seen from an analysis of fig. 7 that: the exclusive-OR gate circuit has the characteristics that power consumption curves are consistent in different clock periods no matter what input signals are, the power consumption is independent of the input signals, and DPA attacks can be effectively resisted.
The functional simulation graph of the nand gate of the multiplier unit circuit/multiplier using the threshold voltage characteristic of the present invention is shown in fig. 8, and it can be known from an analysis of fig. 8 that: the NAND gate of the invention traverses all input conditions and has correct logic function.
The functional verification diagram of the 4-bit multiplier utilizing the threshold voltage characteristic of the invention is shown in fig. 9, and the analysis of fig. 9 shows that: the multiplier circuit of the present invention has a correct logic function.
The power consumption simulation graph of the multiplier using the threshold voltage characteristic of the present invention is shown in fig. 10, and it can be seen from an analysis of fig. 10 that: the multiplier keeps good power consumption in each clock period, the difference is not large, the tip pulse of each time is mainly caused by a plurality of inverters, compared with the traditional multiplier, the power consumption of the traditional multiplier depends on input signals, different power consumption can be generated by different input signals, and the multiplier of the invention has the characteristics that the power consumption is independent of the input signals, and the DPA attack can be effectively resisted.

Claims (2)

1. A multiplication unit circuit utilizing threshold voltage characteristics is characterized by comprising a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, wherein each two-input NOR gate is respectively provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end;
each of the two-input exclusive-or gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a source of the ninth NMOS transistor, and a fourteenth NMOS transistor, and a gate of the first PMOS transistor is connected to a gate of the fourteenth NMOS transistor, The grid electrode of the second PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connecting end of the grid electrode of the second PMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input exclusive-OR gate, the drain electrode of the first PMOS tube and the source electrode of the fifth PMOS tube are connected, the drain electrode of the second PMOS tube and the source electrode of the sixth PMOS tube are connected, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube are connected, the connecting end of the third PMOS tube and the connecting end of the third PMOS tube are the inverted output end of the two-input exclusive-OR gate, the grid electrode of the fourth PMOS tube, the grid electrode of the seventh NMOS tube, the drain electrode of the fifth NMOS tube, The grid electrode of the seventh PMOS transistor, the grid electrode of the eighth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input exclusive or gate, the grid electrode of the fifth PMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the sixth PMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the seventh PMOS transistor, the drain electrode of the fifth NMOS transistor, the grid electrode of the eighth PMOS transistor and the grid electrode of the sixth NMOS transistor are connected, the drain electrode of the eighth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input exclusive or gate, the source electrode of the first NMOS transistor is grounded, the source electrode of the second NMOS transistor and the drain electrode of the seventh NMOS transistor are connected, the source electrode of the seventh NMOS transistor is grounded, and the source electrode of the third NMOS transistor and the drain electrode of the ninth NMOS transistor are connected, a source of the fourth NMOS transistor, a drain of the tenth NMOS transistor, a drain of the eleventh NMOS transistor, a drain of the twelfth NMOS transistor and a drain of the thirteenth NMOS transistor, a source of the fifth NMOS transistor and a drain of the eighth NMOS transistor are connected, a source of the eighth NMOS transistor is grounded, a source of the sixth NMOS transistor is grounded, a source of the ninth NMOS transistor and a drain of the fourteenth NMOS transistor are connected, a source of the tenth NMOS transistor and a drain of the fifteenth NMOS transistor are connected, a gate of the tenth NMOS transistor and a gate of the twelfth NMOS transistor are connected and a connection end thereof is a first inverting input end of the two-input xor gate, a source of the eleventh NMOS transistor and a drain of the sixteenth NMOS transistor are connected, a gate of the eleventh NMOS transistor and a connection end thereof is a first input end of the two-input xor gate, a source electrode of the twelfth NMOS transistor is connected with a drain electrode of the seventeenth NMOS transistor, a source electrode of the thirteenth NMOS transistor is connected with a drain electrode of the eighteenth NMOS transistor, a source electrode of the fourteenth NMOS transistor, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor, a source electrode of the seventeenth NMOS transistor, a source electrode of the eighteenth NMOS transistor and a drain electrode of the nineteenth NMOS transistor are connected, a source electrode of the nineteenth NMOS transistor is grounded, a gate electrode of the fifteenth NMOS transistor is connected with a gate electrode of the sixteenth NMOS transistor, and a connection end thereof is a second inverting input end of the two-input XOR gate, a gate electrode of the seventeenth NMOS transistor is connected with a gate electrode of the eighteenth NMOS transistor, and a connection end thereof is a second input end of the two-input XOR gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold NMOS transistors, the threshold voltage is 0.243V, the ninth NMOS transistor and the fourteenth NMOS transistor are sub-threshold transistors, and the threshold voltage is 0.367V, the tenth NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor and the eighteenth NMOS transistor are high-threshold NMOS transistors, and the threshold voltage is 0.489V;
each of the two-input nand gates respectively comprises a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty-eleventh NMOS transistor, a thirty-second NMOS transistor, a thirty-third NMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor and a thirty-eighth NMOS transistor, wherein the source electrode of the ninth PMOS transistor, the source electrode of the tenth PMOS transistor, the source electrode of the eleventh PMOS transistor, the source electrode of the twelfth PMOS transistor, the fifteenth PMOS transistor, the source electrode of the sixteenth PMOS transistor, the sixteenth NMOS transistor, The gate of the twenty-eighth NMOS transistor and the gate of the thirty-third NMOS transistor are both connected to a power supply, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the twenty-first NMOS transistor and the gate of the twenty-fourth NMOS transistor are connected, and the connection end thereof is the first control end of the two-input nand gate, the drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor, the drain of the tenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the gate of the eleventh PMOS transistor, the gate of the twentieth NMOS transistor, the drain of the twelfth PMOS transistor, the drain of the twenty-first NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the twenty-second NMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the twenty-third NMOS transistor are connected, the drain of the eleventh PMOS transistor and the drain of the twenty-NMOS transistor are connected, and the connection end thereof is the second input nand gate, the drain of the twelfth PMOS transistor and the drain of the twenty-first NMOS transistor are connected The grid of the twelfth PMOS tube, the grid of the twenty-sixth NMOS tube, the grid of the fifteenth PMOS tube, the grid of the twenty-seventh NMOS tube and the grid of the thirty-eighth NMOS tube are connected, the connecting end of the second control end of the two-input NAND gate is the second control end of the two-input NAND gate, the grid of the thirteenth PMOS tube, the grid of the twenty-second NMOS tube, the drain of the fourteenth PMOS tube, the drain of the twenty-third NMOS tube, the drain of the fifteenth PMOS tube, the drain of the twenty-fourth NMOS tube, the grid of the sixteenth PMOS tube and the grid of the twenty-fifth NMOS tube are connected, the drain of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube are connected, the connecting end of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube is the output end of the two-input NAND gate, and the source of the twenty-NMOS tube is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-eleventh NMOS transistor and the drain electrode of the thirty-second NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, the source electrode of the twenty-eighth NMOS transistor and the drain electrode of the thirty-third NMOS transistor are connected, the source electrode of the twenty-ninth NMOS transistor is connected with the drain electrode of the thirty-fourth NMOS transistor, the gate electrode of the twenty-ninth NMOS transistor and the thirty-eleventh NMOS transistor are connected, and the connecting end of the twenty-sixth NMOS transistor is connected with the drain end of the twenty-ninth NMOS transistor The source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the drain of the thirty-fifth NMOS transistor, the gate of the thirty-second NMOS transistor, the connection end of the thirty-fifth NMOS transistor and the gate of the thirty-second NMOS transistor are connected, the source of the thirty-eleventh NMOS transistor and the drain of the thirty-sixth NMOS transistor are connected, the source of the thirty-second NMOS transistor and the drain of the thirty-seventh NMOS transistor are connected, the source of the thirty-third NMOS transistor, the source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor and the drain of the thirty-eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor and the gate of the thirty-fifth NMOS transistor are connected, and the connection end of the thirty-fourth NMOS transistor and the drain of the thirty-fifth NMOS transistor is the second inverting input end of the two-input NAND gate The gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, and the connection end of the thirty-sixth NMOS transistor and the gate of the thirty-seventh NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are all high-threshold NMOS transistors, and the threshold voltage is 0.489V.
The four two-input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two-input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first control end of the first two-input nand gate and the connection end of the first control end of the second two-input xor gate are the first control end of the multiplication unit circuit and are used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the second control end of the multiplication unit circuit is the second control end of the multiplication unit circuit, the output end of the first two-input NAND gate, the first inverting input end of the third two-input NAND gate and the first inverting input end of the first two-input XOR gate are connected, the inverting output end of the first two-input NAND gate and the first input end of the third two-input NAND gate are connected with the first input end of the first two-input XOR gate, the second input end of the first two-input XOR gate and the second input end of the third two-input NAND gate and the input end of the third inverter are connected, the connection end of the first two-input XOR gate and the second input end of the third two-input NAND gate is the third input end of the multiplication unit circuit and is used for connecting a third multiplier, the second inverting input end of the first two-input XOR gate and the second inverting input end of the third two-input NAND gate are connected with the output end of the third inverter, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal output at a low order, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting product signals, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting inverted signals of the product signals, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, and the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit, and the inverted output end of the fourth two-input NAND gate is the inverted carry signal output end of the multiplication unit circuit and is used for outputting the inverted signal of the carry signal to the high order.
2. A multiplier utilizing threshold voltage characteristics is characterized by comprising mxn multiplication unit circuits, wherein the value of m is equal to the number of digits of a multiplicand, the value of n is equal to the number of digits of a multiplier, the mxn multiplication unit circuits are arranged according to n rows and m columns, and each multiplication unit circuit is respectively provided with a first input end, a second input end, a third input end, a first control end, a second control end, a low carry signal input end, a high carry signal output end and a product output end; the first control terminals of the mxn multiplication unit circuits are connected together, the connection terminal thereof is the first control terminal of the multiplier, and the second control terminals of the mxn multiplication unit circuits are connected together, the connection terminal thereof is the second control terminal of the multiplier, and the evaluation control signal is connected thereto, the first input terminals of the M multiplication unit circuits in the nth row are respectively connected to the nth data of the multiplier, N is 1, 2, …, N, the second input terminals of the N multiplication unit circuits in the mth column are respectively connected to the mth (M-1) th data of the multiplier, M is 1, 2, …, M, the third input terminals of the M multiplication unit circuits in the 1 st row are respectively connected to the signal 0, and the low carry signal input terminals of the N multiplication unit circuits in the mth column are respectively connected to the signal 0, the high carry signal output end of the multiplying unit circuit positioned in the N-th row and the K-th column is connected with the low carry signal input end of the multiplying unit circuit positioned in the N-th row and the K-1-th column, K is 2, 3, …, M, the high carry signal output end of the multiplying unit circuit positioned in the j-th row and the 1-th column is connected with the third input end of the multiplying unit circuit positioned in the j + 1-th row and the 1-th column, j is 1, 2, …, N-1, the product output end of the multiplying unit circuit positioned in the N-th row and the K-th column is connected with the third input end of the multiplying unit circuit positioned in the N-th row and the K + 1-th column, K is 1, 2, …, M-1, the product output end of the multiplying unit circuit positioned in the j-th row and the M-th column is the j-th output end of the multiplier, the j-th bit of the product is output end, the product output end of the multiplying unit circuit positioned in the N-th row and the M-th column is the N-1-th output end, outputting the (n-1 + M- (M-1) th bit of the product, wherein the high-order carry signal output end of the multiplication unit circuit positioned in the (n) th row and the (1) th column is the (n + M) th output end of the multiplier and outputs the (n + M) th bit of the product;
each multiplication unit circuit comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, four two-input NAND gates with the same structure and two-input exclusive-OR gates with the same structure, each two-input NOR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end, and each two-input exclusive-OR gate is provided with a first input end, a first inverted input end, a second inverted input end, a first control end, a second control end, an output end and an inverted output end; each of the two-input exclusive-or gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth NMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a source of the ninth NMOS transistor, and a fourteenth NMOS transistor, and a gate of the first PMOS transistor is connected to a gate of the fourteenth NMOS transistor, The grid electrode of the second PMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube are connected, the connecting end of the grid electrode of the second PMOS tube and the grid electrode of the fifth NMOS tube is the first control end of the two-input exclusive-OR gate, the drain electrode of the first PMOS tube and the source electrode of the fifth PMOS tube are connected, the drain electrode of the second PMOS tube and the source electrode of the sixth PMOS tube are connected, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the fourth NMOS tube are connected, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube are connected, the connecting end of the third PMOS tube and the connecting end of the third PMOS tube are the inverted output end of the two-input exclusive-OR gate, the grid electrode of the fourth PMOS tube, the grid electrode of the seventh NMOS tube, the drain electrode of the fifth NMOS tube, The grid electrode of the seventh PMOS transistor, the grid electrode of the eighth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected, and the connection end thereof is the second control end of the two-input exclusive or gate, the grid electrode of the fifth PMOS transistor, the grid electrode of the third NMOS transistor, the drain electrode of the sixth PMOS transistor, the drain electrode of the fourth NMOS transistor, the drain electrode of the seventh PMOS transistor, the drain electrode of the fifth NMOS transistor, the grid electrode of the eighth PMOS transistor and the grid electrode of the sixth NMOS transistor are connected, the drain electrode of the eighth PMOS transistor and the drain electrode of the sixth NMOS transistor are connected, and the connection end thereof is the output end of the two-input exclusive or gate, the source electrode of the first NMOS transistor is grounded, the source electrode of the second NMOS transistor and the drain electrode of the seventh NMOS transistor are connected, the source electrode of the seventh NMOS transistor is grounded, and the source electrode of the third NMOS transistor and the drain electrode of the ninth NMOS transistor are connected, a source of the fourth NMOS transistor, a drain of the tenth NMOS transistor, a drain of the eleventh NMOS transistor, a drain of the twelfth NMOS transistor and a drain of the thirteenth NMOS transistor, a source of the fifth NMOS transistor and a drain of the eighth NMOS transistor are connected, a source of the eighth NMOS transistor is grounded, a source of the sixth NMOS transistor is grounded, a source of the ninth NMOS transistor and a drain of the fourteenth NMOS transistor are connected, a source of the tenth NMOS transistor and a drain of the fifteenth NMOS transistor are connected, a gate of the tenth NMOS transistor and a gate of the twelfth NMOS transistor are connected and a connection end thereof is a first inverting input end of the two-input xor gate, a source of the eleventh NMOS transistor and a drain of the sixteenth NMOS transistor are connected, a gate of the eleventh NMOS transistor and a connection end thereof is a first input end of the two-input xor gate, a source electrode of the twelfth NMOS transistor is connected with a drain electrode of the seventeenth NMOS transistor, a source electrode of the thirteenth NMOS transistor is connected with a drain electrode of the eighteenth NMOS transistor, a source electrode of the fourteenth NMOS transistor, a source electrode of the fifteenth NMOS transistor, a source electrode of the sixteenth NMOS transistor, a source electrode of the seventeenth NMOS transistor, a source electrode of the eighteenth NMOS transistor and a drain electrode of the nineteenth NMOS transistor are connected, a source electrode of the nineteenth NMOS transistor is grounded, a gate electrode of the fifteenth NMOS transistor is connected with a gate electrode of the sixteenth NMOS transistor, and a connection end thereof is a second inverting input end of the two-input XOR gate, a gate electrode of the seventeenth NMOS transistor is connected with a gate electrode of the eighteenth NMOS transistor, and a connection end thereof is a second input end of the two-input XOR gate, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor are all low-threshold NMOS transistors, the threshold voltage is 0.243V, the ninth NMOS transistor and the fourteenth NMOS transistor are sub-threshold transistors, and the threshold voltage is 0.367V, the tenth NMOS transistor, the thirteenth NMOS transistor, the fifteenth NMOS transistor and the eighteenth NMOS transistor are high-threshold NMOS transistors, and the threshold voltage is 0.489V; each of the two-input nand gates respectively comprises a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty-eleventh NMOS transistor, a thirty-second NMOS transistor, a thirty-third NMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor and a thirty-eighth NMOS transistor, wherein the source electrode of the ninth PMOS transistor, the source electrode of the tenth PMOS transistor, the source electrode of the eleventh PMOS transistor, the source electrode of the twelfth PMOS transistor, the fifteenth PMOS transistor, the source electrode of the sixteenth PMOS transistor, the sixteenth NMOS transistor, The gate of the twenty-eighth NMOS transistor and the gate of the thirty-third NMOS transistor are both connected to a power supply, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the twenty-first NMOS transistor and the gate of the twenty-fourth NMOS transistor are connected, and the connection end thereof is the first control end of the two-input nand gate, the drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor, the drain of the tenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the gate of the eleventh PMOS transistor, the gate of the twentieth NMOS transistor, the drain of the twelfth PMOS transistor, the drain of the twenty-first NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the twenty-second NMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the twenty-third NMOS transistor are connected, the drain of the eleventh PMOS transistor and the drain of the twenty-NMOS transistor are connected, and the connection end thereof is the second input nand gate, the drain of the twelfth PMOS transistor and the drain of the twenty-first NMOS transistor are connected The grid of the twelfth PMOS tube, the grid of the twenty-sixth NMOS tube, the grid of the fifteenth PMOS tube, the grid of the twenty-seventh NMOS tube and the grid of the thirty-eighth NMOS tube are connected, the connecting end of the second control end of the two-input NAND gate is the second control end of the two-input NAND gate, the grid of the thirteenth PMOS tube, the grid of the twenty-second NMOS tube, the drain of the fourteenth PMOS tube, the drain of the twenty-third NMOS tube, the drain of the fifteenth PMOS tube, the drain of the twenty-fourth NMOS tube, the grid of the sixteenth PMOS tube and the grid of the twenty-fifth NMOS tube are connected, the drain of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube are connected, the connecting end of the sixteenth PMOS tube and the drain of the twenty-fifth NMOS tube is the output end of the two-input NAND gate, and the source of the twenty-NMOS tube is grounded, the source electrode of the twenty-first NMOS transistor is connected with the drain electrode of the twenty-sixth NMOS transistor, the source electrode of the twenty-sixth NMOS transistor is grounded, the source electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-eighth NMOS transistor, the source electrode of the twenty-third NMOS transistor, the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-eleventh NMOS transistor and the drain electrode of the thirty-second NMOS transistor are connected, the source electrode of the twenty-fourth NMOS transistor is connected with the drain electrode of the twenty-seventh NMOS transistor, the source electrode of the twenty-seventh NMOS transistor is grounded, the source electrode of the twenty-fifth NMOS transistor is grounded, the source electrode of the twenty-eighth NMOS transistor and the drain electrode of the thirty-third NMOS transistor are connected, the source electrode of the twenty-ninth NMOS transistor is connected with the drain electrode of the thirty-fourth NMOS transistor, the gate electrode of the twenty-ninth NMOS transistor and the thirty-eleventh NMOS transistor are connected, and the connecting end of the twenty-sixth NMOS transistor is connected with the drain end of the twenty-ninth NMOS transistor The source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the drain of the thirty-fifth NMOS transistor, the gate of the thirty-second NMOS transistor, the connection end of the thirty-fifth NMOS transistor and the gate of the thirty-second NMOS transistor are connected, the source of the thirty-eleventh NMOS transistor and the drain of the thirty-sixth NMOS transistor are connected, the source of the thirty-second NMOS transistor and the drain of the thirty-seventh NMOS transistor are connected, the source of the thirty-third NMOS transistor, the source of the thirty-fourth NMOS transistor, the source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor and the drain of the thirty-eighth NMOS transistor are connected, the source of the thirty-eighth NMOS transistor is grounded, the gate of the thirty-fourth NMOS transistor and the gate of the thirty-fifth NMOS transistor are connected, and the connection end of the thirty-fourth NMOS transistor and the drain of the thirty-fifth NMOS transistor is the second inverting input end of the two-input NAND gate The gate of the thirty-sixth NMOS transistor is connected to the gate of the thirty-seventh NMOS transistor, and the connection end of the thirty-sixth NMOS transistor and the gate of the thirty-seventh NMOS transistor is the second input end of the two-input nand gate, the twenty-ninth NMOS transistor and the thirty-fourth NMOS transistor are both low-threshold NMOS transistors, the threshold voltage is 0.243V, the twenty-eighth NMOS transistor and the thirty-third NMOS transistor are both sub-threshold transistors, and the threshold voltage is 0.367V, the thirty-NMOS transistor, the thirty-eleventh NMOS transistor, the thirty-second NMOS transistor, the thirty-fifth NMOS transistor, the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are all high-threshold NMOS transistors, and the threshold voltage is 0.489V. The four two-input NAND gates are respectively called a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a fourth two-input NAND gate, the two-input XOR gates are respectively called a first two-input XOR gate and a second two-input XOR gate, the first input end of the first two-input NAND gate is connected with the input end of the first inverter, the connection end of the first two-input NAND gate is the first input end of the multiplication unit circuit and is used for accessing a first multiplier, the first inverting input end of the first two-input NAND gate is connected with the output end of the first inverter, the second input end of the first two-input NAND gate is connected with the input end of the second inverter, the connection end of the first two-input NAND gate is the second input end of the multiplication unit circuit and is used for accessing a second multiplier, and the second inverting input end of the first two-input NAND gate is connected with the output end of the second inverter, the first control end of the first two-input nand gate, the first control end of the second two-input nand gate, the first control end of the third two-input nand gate, the first control end of the fourth two-input nand gate, the first control end of the first two-input xor gate and the first control end of the second two-input xor gate are connected, the connection end of the first control end of the first two-input nand gate and the connection end of the first control end of the second two-input xor gate are the first control end of the multiplication unit circuit and are used for accessing a discharge control signal, the second control end of the first two-input nand gate, the second control end of the second two-input nand gate, the second control end of the third two-input nand gate, the second control end of the fourth two-input nand gate, the second control end of the first two-input xor gate and the second control end of the second two-input xor gate are connected, and the connection end of the second control end of the multiplication unit circuit is the second control end of the multiplication unit circuit, the output end of the first two-input NAND gate, the first inverting input end of the third two-input NAND gate and the first inverting input end of the first two-input XOR gate are connected, the inverting output end of the first two-input NAND gate and the first input end of the third two-input NAND gate are connected with the first input end of the first two-input XOR gate, the second input end of the first two-input XOR gate and the second input end of the third two-input NAND gate and the input end of the third inverter are connected, the connection end of the first two-input XOR gate and the second input end of the third two-input NAND gate is the third input end of the multiplication unit circuit and is used for connecting a third multiplier, the second inverting input end of the first two-input XOR gate and the second inverting input end of the third two-input NAND gate are connected with the output end of the third inverter, the output end of the first two-input exclusive-or gate, the first input end of the second two-input exclusive-or gate and the first input end of the second two-input nand gate are connected, the inverted output end of the first two-input exclusive-or gate, the first inverted input end of the second two-input exclusive-or gate and the first inverted input end of the second two-input nand gate are connected, the second input end of the second two-input exclusive-or gate, the second input end of the second two-input nand gate and the input end of the fourth inverter are connected, the connection end of the connection end is the low-order carry signal input end of the multiplication unit circuit and is used for accessing a carry signal output at a low order, the second inverted input end of the second two-input exclusive-or gate, the second inverted input end of the second two-input nand gate and the output end of the fourth inverter are connected, the output end of the second input exclusive-or gate is the output end of the multiplication unit circuit and is used for outputting product signals, the inverted output end of the second input exclusive-or gate is the inverted output end of the multiplication unit circuit and is used for outputting inverted signals of the product signals, the output end of the second input nand gate is connected with the first inverted input end of the fourth two input nand gate, the inverted output end of the second input nand gate is connected with the first input end of the fourth two input nand gate, the output end of the third two input nand gate is connected with the second inverted input end of the fourth two input nand gate, the inverted output end of the third two input nand gate is connected with the second input end of the fourth two input nand gate, and the output end of the fourth two input nand gate is the carry signal output end of the multiplication unit circuit, and the inverted output end of the fourth two-input NAND gate is the inverted carry signal output end of the multiplication unit circuit and is used for outputting the inverted signal of the carry signal to the high order.
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