CN107634750B - Multi-bit multi-valued adiabatic multiplier with transmission gate structure - Google Patents

Multi-bit multi-valued adiabatic multiplier with transmission gate structure Download PDF

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CN107634750B
CN107634750B CN201710654770.1A CN201710654770A CN107634750B CN 107634750 B CN107634750 B CN 107634750B CN 201710654770 A CN201710654770 A CN 201710654770A CN 107634750 B CN107634750 B CN 107634750B
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CN107634750A (en
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张跃军
汪鹏君
丁代鲁
王佳伟
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Ningbo University
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Ningbo University
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Abstract

The invention discloses a multi-bit multi-value adiabatic multiplier based on a transmission gate structure, which comprises an n-bit multi-value adiabatic multiplier unit, wherein a clock control clock signal input end of the n-bit multi-value adiabatic multiplier unit is connected with an inverted high-order carry signal output end of an nth-bit multi-value adiabatic multiplier unit, a first clock control clock signal input end of the n-bit multi-value adiabatic multiplier unit is connected, second clock control clock signal input ends of all multi-value adiabatic multiplier units positioned at odd bits in the n-bit multi-value adiabatic multiplier unit are connected, second clock control clock signal input ends of all multi-value adiabatic multiplier units positioned at even bits in the n-bit multi-value adiabatic multiplier unit are connected, and a high-order carry signal output end of a k-bit multi-value adiabatic multiplier unit is connected with a low-order carry signal input end of a k + 1-bit multi-value; its advantages are small area, low power consumption and short operation period.

Description

Multi-bit multi-valued adiabatic multiplier with transmission gate structure
Technical Field
The invention relates to a multi-bit multi-value adiabatic multiplier, in particular to a multi-bit multi-value adiabatic multiplier based on a transmission gate structure.
Background
In the development of very large scale integrated circuits, multipliers are the core of real-time image processing and digital signal processing and are often the key paths for data processing in microprocessors. The period in which the multiplier completes one operation substantially determines the dominant frequency of the microprocessor. Therefore, the research and implementation of high performance multipliers is very important for microprocessors, and the improvement of the performance of the multipliers plays an important role in improving the overall performance of the microprocessors. The multiplication operation of the multiplier is based on a large number of addition operations, and the basic step for completing one multiplication operation is to generate a partial product and sum the partial products.
With the development of integrated circuit technology, the requirement on the multiplier is higher and higher, the multi-bit multi-valued adiabatic multiplier realized by the traditional CMOS device is more and more difficult to meet the requirements in the aspects of area, power consumption, operation period and the like, and the design and realization of the high-performance multi-bit multi-valued adiabatic multiplier are still the current hot topic due to the continuously improved high-performance operation requirement.
Therefore, the design of the multi-bit multi-valued adiabatic multiplier based on the transmission gate structure, which has the advantages of small area, low power consumption and short operation period, has important significance for the development of integrated circuits.
Disclosure of Invention
The invention aims to solve the technical problem of providing a multi-bit multi-valued adiabatic multiplier based on a transmission gate structure, which has small area, low power consumption and short operation period.
The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-bit multi-valued adiabatic multiplier based on transmission gate structure comprises an n-bit multi-valued adiabatic multiplier unit, wherein n is an integer greater than or equal to 2, the multi-valued adiabatic multiplier unit is provided with a first input end, a second input end, a low-order carry signal input end, a clock-controlled clock signal input end, a first power clock signal input end, a second power clock signal input end, a product output end, an inverted product output end, a high-order carry signal output end and an inverted high-order carry signal output end, the multi-valued adiabatic multiplier unit comprises a gate control circuit, a product circuit and a carry circuit, and the gate control circuit is provided with a first input end, a second input end, a third input end, a first output end, a second output end, a third output end, a fourth output end, a fifth output end, a sixth output end, a seventh output end and an eighth output end, A ninth output terminal, a first inverted output terminal, a second inverted output terminal, a third inverted output terminal, a fourth inverted output terminal, a fifth inverted output terminal, a sixth inverted output terminal, a seventh inverted output terminal, an eighth inverted output terminal, a ninth inverted output terminal, a clock-controlled clock signal input terminal and a power clock signal input terminal; the local product circuit is provided with a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a sixth input end, a first inverted input end, a second inverted input end, a third inverted input end, a fourth inverted input end, a fifth inverted input end, a sixth inverted input end, a clock-controlled clock signal input end, a first power clock signal input end, a second power clock signal input end, an output end and an inverted output end; the carry circuit is provided with a clock-controlled clock signal input end, a power clock signal input end, a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a sixth input end, a seventh input end, a first inverted input end, a second inverted input end, a third inverted input end, a fourth inverted input end, a fifth inverted input end, a sixth inverted input end, a seventh inverted input end, an output end and an inverted output end; the first input end of the gate control circuit is the first input end of the multiple-valued adiabatic multiplier unit, the second input end of the gate control circuit is the second input end of the multiple-valued adiabatic multiplier unit, the third input end of the gate control circuit is the low-order carry signal input end of the multiple-valued adiabatic multiplier unit, the clock signal input end of the gate control circuit, the clock signal input end of the local product circuit and the clock signal input end of the carry circuit are connected, the connection end of the gate control circuit, the clock signal input end of the local product circuit and the clock signal input end of the carry circuit is the clock signal input end of the multiple-valued adiabatic multiplier unit, the power clock signal input end of the gate control circuit, the first power clock signal input end of the local product circuit and the power clock signal input end of the carry circuit are connected, and the connection end of the gate control circuit is the first power clock signal input end of the multiple-valued adiabatic multiplier unit, the second power clock signal input end of the local product circuit is the second power clock signal input end of the multivalued adiabatic multiplier unit, the first output end of the gate control circuit is respectively connected with the first input end of the local product circuit and the first input end of the carry circuit, the second output end of the gate control circuit is respectively connected with the second input end of the local product circuit and the second input end of the carry circuit, the third output end of the gate control circuit is respectively connected with the third input end of the local product circuit and the third input end of the carry circuit, the fourth output end of the gate control circuit is respectively connected with the fourth input end of the local product circuit and the fourth input end of the carry circuit, the fifth output end of the gate control circuit is respectively connected with the fifth input end of the local product circuit and the fifth input end of the carry circuit, the sixth output end of the gate control circuit is respectively connected with the sixth input end of the local product circuit and the sixth input end of the carry circuit, the seventh output end of the gate control circuit is connected with the seventh input end of the carry circuit, the first inverting output end of the gate control circuit is respectively connected with the first inverting input end of the local product circuit and the first inverting input end of the carry circuit, the second inverting output end of the gate control circuit is respectively connected with the second inverting input end of the local product circuit and the second inverting input end of the carry circuit, the third inverting output end of the gate control circuit is respectively connected with the third inverting input end of the local product circuit and the third inverting input end of the carry circuit, and the fourth inverting output end of the gate control circuit is respectively connected with the fourth inverting input end of the local product circuit and the fourth inverting input end of the carry circuit, the fifth inverse output end of the gate control circuit is connected with the fifth inverse input end of the local product circuit and the fifth inverse input end of the carry circuit, the sixth inverse output end of the gate control circuit is connected with the sixth inverse input end of the local product circuit and the sixth inverse input end of the carry circuit, the seventh inverse output end of the gate control circuit is connected with the seventh inverse input end of the carry circuit, the output end of the local product circuit is the local product output end of the multiple-valued adiabatic multiplier unit, the inverse output end of the local product circuit is the inverse local product output end of the multiple-valued adiabatic multiplier unit, the output end of the carry circuit is the high-order carry signal output end of the multiple-valued adiabatic multiplier unit, and the inverse output end of the carry circuit is the inverse high-order carry signal output end of the multiple-valued adiabatic multiplier unit, the input end of the clock control clock signal of the n-bit multi-valued adiabatic multiplier unit is connected with the output end of the inverted high-order carry signal of the nth multi-valued adiabatic multiplier unit, the connection end of the input end is the input end of the clock control clock signal of the multi-bit multi-valued adiabatic multiplier unit and is used for accessing the clock control clock signal, the first power clock signal input end of the n-bit multi-valued adiabatic multiplier unit is connected with the first clock control clock signal input end of the multi-bit multi-valued adiabatic multiplier unit, the connection end of the first power clock signal input end of the multi-valued adiabatic multiplier unit is used for accessing the first power clock signal, the second power clock signal input ends of all the even-numbered multi-valued adiabatic multiplier units in the n-bit multi-valued adiabatic multiplier unit are connected, the connection end of the second clock signal input end of the multi-bit multi-valued adiabatic multiplier unit is used for accessing the second power clock signal, and all the odd-numbered The input end of the second power clock signal is connected, the connection end of the second power clock signal is a third clock control clock signal input end of the multi-bit multivalued adiabatic multiplier and used for accessing a third power clock signal, the amplitude levels of the clock control clock signal and the first power clock signal are the same, the phase difference between the clock control clock signal and the first power clock signal is 180 degrees, the phases of the first power clock signal and the second power clock signal are the same, the amplitude level of the first power clock signal is 2 times of the amplitude level of the second power clock signal, the amplitude levels of the third power clock signal and the second power clock signal are the same, and the phase difference between the third power clock signal and the second power clock signal is 180 degrees; the high-order carry signal output end of the multivalued adiabatic multiplier unit at the kth position is connected with the low-order carry signal input end of the multivalued adiabatic multiplier unit at the (k + 1) th position, and k is 1, 2, …, n-1; the first input end of the multiple-valued adiabatic multiplier unit at the j position is used for accessing the j position signal of the first multiplier, the second input end of the multiple-valued adiabatic multiplier unit at the j position is used for accessing the j position signal of the second multiplier, and j is 1, 2, …, n.
The gate control circuit comprises three gate control units and nine binary inverters, wherein each gate control unit is provided with an input end, a clock control clock signal input end, a power clock signal input end, a first output end, a second output end and a third output end, the three gate control units are respectively a first gate control unit, a second gate control unit and a third gate control unit, and the nine binary inverters are respectively a first binary inverter, a second binary inverter, a third binary inverter, a fourth binary inverter, a fifth binary inverter, a sixth binary inverter, a seventh binary inverter, an eighth binary inverter and a ninth binary inverter; the first output of first gate control unit with the input of first binary phase inverter connect and its link do gate circuit's first output, first binary phase inverter's output do gate circuit's first reverse phase output, first gate control unit's second output with second binary phase inverter's input connect and its link do gate circuit's second output, second binary phase inverter's output do gate circuit's second reverse phase output, first gate control unit's third output with third binary phase inverter's input connect and its link do gate circuit's third output, third binary phase inverter's output do gate circuit's third reverse phase output, second gate control unit's first output with fourth binary phase inverter's input connect and its link do gate circuit's third output The output end of the second binary phase inverter is the fourth inverting output end of the gate control circuit, the second output end of the second gate control unit is connected with the input end of the fifth binary phase inverter, the connection end of the second gate control unit is the fifth output end of the gate control circuit, the output end of the fifth binary phase inverter is the fifth inverting output end of the gate control circuit, the third output end of the second gate control unit is connected with the input end of the sixth binary phase inverter, the connection end of the third gate control unit is the sixth output end of the gate control circuit, the output end of the sixth binary phase inverter is the sixth inverting output end of the gate control circuit, the first output end of the third gate control unit is connected with the input end of the seventh binary phase inverter, and the connection end of the first output end of the third gate control unit is the seventh output end of the gate control circuit, the output end of the seventh binary inverter is the seventh inverted output end of the gate control circuit, the second output end of the third gate control unit is connected with the input end of the eighth binary inverter, the connection end of the second binary inverter is the eighth output end of the gate control circuit, the output end of the eighth binary inverter is the eighth inverted output end of the gate control circuit, the third output end of the third gate control unit is connected with the input end of the ninth binary inverter, the connection end of the third binary inverter is the ninth output end of the gate control circuit, the output end of the ninth binary inverter is the ninth inverted output end of the gate control circuit, the clock signal input end of the first gate control unit, the clock signal input end of the second gate control unit and the clock signal input end of the third gate control unit are connected, and the connection end of the ninth binary inverter is the clock signal input end of the gate control circuit, the power clock signal input end of the first gating unit, the power clock signal input end of the second gating unit and the power clock signal input end of the third gating unit are connected, the connection end of the power clock signal input end of the third gating unit is the power clock signal input end of the gating circuit, the input end of the first gating unit is the first input end of the gating circuit, the input end of the second gating unit is the second input end of the gating circuit, and the input end of the third gating unit is the third input end of the gating circuit. The circuit has the function of converting a binary circuit into a multi-value character circuit under the traditional CMOS process, the logic level of an output signal is 0 or a power supply VDD, the stability is good, and the reliability is high.
The first gate control unit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a second input AND gate, wherein the second input AND gate is provided with a first input end, a second input end and an output end, the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the connecting end of the first PMOS tube is the power clock signal input end of the first gate control unit, the source electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, and the connecting end of the third PMOS tube is the clock control clock signal input end of the first gate control unit; the gate of the first PMOS transistor, the gate of the first NMOS transistor, the gate of the third PMOS transistor and the gate of the third NMOS transistor are connected, and the connection end thereof is the input end of the first gate control unit, the drain of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the first NMOS transistor and the gate of the second NMOS transistor are connected, the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are all grounded, the drain of the third NMOS transistor, the gate of the fourth NMOS transistor, the drain of the third PMOS transistor and the gate of the fourth PMOS transistor are connected, the drain of the second PMOS transistor, the drain of the second NMOS transistor and the first input end of the second input and gate are connected, and the connection end thereof is the first output end of the first gate control unit, the drain electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the second input end of the two-input AND gate are connected, the connection end of the two-input AND gate is the third output end of the first gate control unit, and the output end of the two-input AND gate is the second output end of the first gate control unit; the circuit structures of the second gate control unit and the third gate control unit are the same as the circuit structure of the first gate control unit. The circuit is realized by matching threshold voltages of a first PMOS tube, a first NMOS tube, a third NMOS tube and a third PMOS tube with threshold voltages of the first PMOS tube, the second PMOS tube, the third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a second input AND gate, can convert a multi-valued signal into a binary control signal under a CMOS (complementary metal oxide semiconductor) process, and ensures the realization of a logic function of the circuit.
The threshold voltage of the first PMOS tube is-0.6126V, the threshold voltage of the first NMOS tube is-0.2457V, the threshold voltage of the third NMOS tube is 0.243V, and the threshold voltage of the third PMOS tube is 0.4891V. The circuit can realize maximum interval inverter threshold value discrimination under the traditional CMOS process.
The local displacement circuit comprises a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube and a twentieth NMOS tube; a source of the fifth PMOS transistor, a source of the sixth PMOS transistor, a drain of the fifth NMOS transistor, a drain of the sixth NMOS transistor, a source of the tenth PMOS transistor, a source of the eleventh PMOS transistor, a drain of the tenth NMOS transistor and a drain of the eleventh NMOS transistor are connected and a connection end thereof is a second power clock signal input end of the product local circuit, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a drain of the seventh NMOS transistor, a drain of the eighth NMOS transistor, a source of the ninth PMOS transistor, a source of the sixteenth PMOS transistor, a drain of the ninth NMOS transistor, a source of the nineteenth PMOS transistor and a source of the twentieth PMOS transistor are connected and a connection end thereof is a first power clock signal input end of the product local circuit, the drain of the nineteenth NMOS transistor is connected with the drain of the twentieth NMOS transistor, and the connection end of the nineteenth NMOS transistor is the clock control clock signal input end of the local product circuit, the grid of the fifth NMOS transistor, the grid of the seventh PMOS transistor and the grid of the tenth NMOS transistor are connected, and the connection end of the fifth NMOS transistor and the grid of the seventh PMOS transistor is the second input end of the local product circuit, the grid of the fifth PMOS transistor and the grid of the seventh NMOS transistor are connected with the grid of the tenth PMOS transistor, and the connection end of the fifth PMOS transistor and the grid of the seventh NMOS transistor is the local product circuitA gate of the sixth NMOS transistor, a gate of the eighth PMOS transistor, and a gate of the eleventh NMOS transistor are connected, and their connection ends are the third input end of the local product circuit, a gate of the sixth PMOS transistor, a gate of the eighth PMOS transistor, and a gate of the eleventh PMOS transistor are connected, and their connection ends are the third inverse input end of the local product circuit, a gate of the sixteenth NMOS transistor is the first input end of the local product circuit, a gate of the sixteenth PMOS transistor is the first inverse input end of the local product circuit, a gate of the ninth NMOS transistor is the fourth input end of the local product circuit, a gate of the ninth PMOS transistor is the fourth inverse input end of the local product circuit, a gate of the twelfth NMOS transistor, a gate of the fifteenth PMOS transistor, and a gate of the seventeenth NMOS transistor are connected, and their connection ends are the fifth input end of the local product circuit A gate of the twelfth PMOS transistor, a gate of the fifteenth NMOS transistor, and a gate of the seventeenth PMOS transistor are connected, and a connection end thereof is a fifth inverting input end of the local product circuit, a gate of the thirteenth NMOS transistor, a gate of the fourteenth PMOS transistor, and a gate of the eighteenth NMOS transistor are connected, and a connection end thereof is a sixth input end of the local product circuit, a gate of the thirteenth PMOS transistor, a gate of the fourteenth NMOS transistor, and a gate of the eighteenth PMOS transistor are connected, and a connection end thereof is a sixth inverting input end of the local product circuit, a drain of the fifth PMOS transistor, a source of the fifth NMOS transistor, a source of the twelfth NMOS transistor, and a drain of the twelfth NMOS transistor are connected, a drain of the sixth PMOS transistor, a source of the sixth NMOS transistor, a source of the thirteenth PMOS transistor, and a drain of the thirteenth NMOS transistor are connected, the drain electrode of the seventh PMOS tube, the source electrode of the seventh NMOS tube, the source electrode of the fourteenth PMOS tube and the drain electrode of the fourteenth NMOS tube are connected, the drain electrode of the eighth PMOS tube, the source electrode of the eighth NMOS tube, the source electrode of the fifteenth PMOS tube and the drain electrode of the fifteenth NMOS tube are connected, and the drain electrode of the tenth PMOS tubeA source of the tenth NMOS transistor, a source of the seventeenth PMOS transistor and a drain of the seventeenth NMOS transistor are connected, a drain of the eleventh PMOS transistor, a source of the eleventh NMOS transistor, a source of the eighteenth PMOS transistor and a drain of the eighteenth NMOS transistor are connected, a drain of the twelfth PMOS transistor, a source of the twelfth NMOS transistor, a drain of the thirteenth PMOS transistor, a source of the thirteenth NMOS transistor, a drain of the fourteenth PMOS transistor, a source of the fourteenth NMOS transistor, a drain of the fifteenth PMOS transistor, a source of the fifteenth NMOS transistor, a drain of the nineteenth PMOS transistor, a source of the nineteenth NMOS transistor, a gate of the twentieth PMOS transistor and a gate of the twentieth NMOS transistor are connected, and a connection end thereof is an output end of the local product circuit, a drain of the nineteenth PMOS transistor, a drain of the nineteenth NMOS transistor, a source of the nineteenth NMOS transistor, a gate of the twentieth PMOS transistor and a gate of the twentieth NMOS transistor are connected, and a connection end thereof is an output end of the local product, The source electrode of the ninth NMOS transistor, the drain electrode of the sixteenth PMOS transistor, the source electrode of the sixteenth NMOS transistor, the drain electrode of the seventeenth PMOS transistor, the source electrode of the seventeenth NMOS transistor, the drain electrode of the eighteenth PMOS transistor, the source electrode of the eighteenth NMOS transistor, the drain electrode of the twentieth PMOS transistor, the source electrode of the twentieth NMOS transistor, the gate electrode of the nineteenth PMOS transistor and the gate electrode of the nineteenth NMOS transistor are connected, and the connecting end of the source electrode of the ninth NMOS transistor and the drain electrode of the eighteenth NMOS transistor is the inverted output end of the local product circuit. The circuit is designed by adopting a transmission gate structure, and in a data recovery stage, the circuit comprises a transmission gate consisting of a fifth NMOS (N-channel metal oxide semiconductor) tube and a fifth PMOS (P-channel metal oxide semiconductor) tube, a transmission gate consisting of a sixth NMOS tube and a sixth PMOS tube, a transmission gate consisting of a tenth NMOS tube and a tenth PMOS tube, a transmission gate consisting of an eleventh NMOS tube and an eleventh PMOS tube, a transmission gate consisting of a twelfth NMOS tube and a twelfth PMOS tube, a transmission gate consisting of a thirteenth NMOS tube and a thirteenth PMOS tube, a transmission gate consisting of a seventeenth NMOS tube and a seventeenth PMOS tube, a transmission gate consisting of an eighteenth NMOS tube and an eighteenth PMOS tube, a transmission gate consisting of a seventh NMOS tube and a seventh PMOS tube, a transmission gate consisting of an eighth NMOS tube and an eighth PMOS tube, a transmission gate consisting of a ninth NMOS tube and a ninth PMOS tube, a transmission gate consisting of a fourteenth NMOS tube and a fourteenth PMOS tube, a transmission gate consisting of a fifteenth NMOS tube and a fifteenth PMOS tube, and a transmission gate consisting of a fifteenth PMOS tube and aThe signal voltage is reduced to 0V by a transmission gate consisting of sixteen NMOS tubes and sixteenth PMOS tubes, charges are transmitted to a second power clock signal input end of the local product circuit from an output end (node P) of the local product circuit through the transmission gate consisting of the fifth NMOS tube and the fifth PMOS tube, the transmission gate consisting of the sixth NMOS tube and the sixth PMOS tube, the transmission gate consisting of the twelfth NMOS tube and the twelfth PMOS tube and the transmission gate consisting of the thirteenth NMOS tube and the thirteenth PMOS tube in a completely adiabatic recovery mode, the charges are transmitted to a first power clock signal input end of the local product circuit from the node P through the transmission gate consisting of the seventh NMOS tube and the seventh PMOS tube, the transmission gate consisting of the eighth NMOS tube and the eighth PMOS tube, the transmission gate consisting of the fourteenth NMOS tube and the fourteenth PMOS tube and the transmission gate consisting of the fifteenth NMOS tube and the fifteenth PMOS tube, and the charges are transmitted to a first power clock signal input end of the local product circuit from the node P
Figure GDA0002441975720000081
The transmission gate formed by the ninth NMOS tube and the ninth PMOS tube and the transmission gate formed by the sixteenth NMOS tube and the sixteenth PMOS tube are transmitted to the first power clock signal input end of the local product circuit, and the slave node
Figure GDA0002441975720000082
The transmission gate formed by the tenth NMOS tube and the tenth PMOS tube, the transmission gate formed by the eleventh NMOS tube and the eleventh PMOS tube, the transmission gate formed by the seventeenth NMOS tube and the seventeenth PMOS tube, and the transmission gate formed by the eighteenth NMOS tube and the eighteenth PMOS tube are transmitted to the second power clock signal input end of the local product circuit, and no threshold value loss exists.
The carry circuit comprises a twenty-first PMOS (P-channel metal oxide semiconductor) tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a twenty-ninth PMOS tube, a thirty-fourth PMOS tube, a thirty-eleventh PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-eleventh NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube and a thirty-sixth NMOS tube, a source electrode of the twenty-first PMOS tube, a drain electrode of the twenty-second PMOS tube, a twenty-fifth NMOS tube, The drain of the twenty-second NMOS transistor, the source of the twenty-third PMOS transistor, the drain of the twenty-third NMOS transistor, the source of the twenty-fourth PMOS transistor, the drain of the twenty-fourth NMOS transistor, the source of the twenty-fifth PMOS transistor, the drain of the twenty-fifth NMOS transistor, the source of the twenty-ninth PMOS transistor, the drain of the twenty-ninth NMOS transistor, the source of the thirty-fifth PMOS transistor and the source of the thirty-sixth PMOS transistor are connected and their connection ends are the power clock signal input end of the carry circuit, the drain of the thirty-fifth NMOS transistor and the drain of the thirty-sixth NMOS transistor are connected and their connection ends are the clock signal input end of the carry circuit, the gate of the twenty-first NMOS transistor, the gate of the twenty-sixth NMOS transistor and the gate of the thirty-second NMOS transistor are connected and their connection ends are the third input end of the carry circuit, the gate of the twenty-first PMOS transistor, the gate of the twenty-sixth PMOS transistor and the gate of the thirty-second PMOS transistor are connected and the connection end thereof is the third inverting input end of the carry circuit, the gate of the twenty-second NMOS transistor and the gate of the twenty-third PMOS transistor are connected and the connection end thereof is the seventh input end of the carry circuit, the gate of the twenty-second PMOS transistor and the gate of the twenty-third NMOS transistor are connected and the connection end thereof is the seventh inverting input end of the carry circuit, the gate of the twenty-fourth NMOS transistor, the gate of the twenty-seventh NMOS transistor and the gate of the thirty-third NMOS transistor are connected and the connection end thereof is the second input end of the carry circuit, the gate of the twenty-fourth PMOS transistor, the gate of the twenty-seventh PMOS transistor and the gate of the thirty-third PMOS transistor are connected and the connection end thereof is the second inverting input end of the carry circuit, the gate of the twenty-fifth NMOS transistor is the first input end of the carry circuit, the gate of the twenty-fifth PMOS transistor is the first inverting input end of the carry circuit, the gate of the twenty-eighth NMOS transistor, the gate of the thirty-first NMOS transistor, and the gate of the thirty-fourth NMOS transistor are connected, and the connection end thereof is the fifth input end of the carry circuit, the gate of the twenty-eighth PMOS transistor, the gate of the thirty-eleventh PMOS transistor, and the gate of the thirty-fourth PMOS transistor are connected, and the connection end thereof is the fifth inverting input end of the carry circuit, the gate of the twenty-ninth NMOS transistor is the fourth input end of the carry circuit, the gate of the twenty-ninth PMOS transistor is the fourth inverting input end of the carry circuit, and the gate of the thirty-NMOS transistor is the sixth input end of the carry circuit, the gate of the thirtieth PMOS transistor is the sixth inverting input terminal of the carry circuit, the drain of the twenty-first PMOS transistor, the source of the twenty-first NMOS transistor, the source of the thirty-first PMOS transistor and the drain of the thirty-second NMOS transistor are connected, the drain of the twenty-second PMOS transistor, the source of the twenty-second NMOS transistor, the source of the twenty-sixth PMOS transistor, the drain of the twenty-sixth NMOS transistor, the source of the twenty-seventh PMOS transistor and the drain of the twenty-seventh NMOS transistor are connected, the drain of the twenty-sixth PMOS transistor, the source of the twenty-sixth NMOS transistor, the drain of the thirty-seventh PMOS transistor and the source of the thirty-eleventh PMOS transistor are connected, the drain of the twenty-seventh PMOS transistor, the source of the twenty-seventh NMOS transistor, the drain of the thirty-second NMOS transistor and the source of the thirty-second NMOS transistor are connected, the drain of the twenty-third PMOS transistor, the source of the twenty-third NMOS transistor, the source of the thirty-third PMOS transistor, the drain of the thirty-third NMOS transistor, the source of the twenty-eighth PMOS transistor and the drain of the twenty-eighth NMOS transistor are connected, the drain of the twenty-fourth PMOS transistor, the source of the twenty-fourth NMOS transistor, the source of the thirty-fourth PMOS transistor and the drain of the thirty-fourth NMOS transistor are connected, the drain of the thirty-fourth PMOS transistor, the source of the thirty-fifth NMOS transistor, the drain of the thirty-eleventh PMOS transistor, the source of the thirty-eleventh NMOS transistor, the drain of the thirty-second PMOS transistor, the source of the thirty-second NMOS transistor, the drain of the thirty-fifth PMOS transistor, the source of the thirty-fifth NMOS transistor, the gate of the thirty-sixth PMOS transistor and the gate of the thirty-sixth NMOS transistor are connected, and the connection end thereof is the output end of the carry circuit, the drain electrode of the twenty-fifth PMOS transistor, the source electrode of the twenty-fifth NMOS transistor, the drain electrode of the twenty-eighth PMOS transistor, the source electrode of the twenty-eighth NMOS transistor, the drain electrode of the twenty-ninth PMOS transistor, the source electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-third PMOS transistor, the source electrode of the thirty-third NMOS transistor, the drain electrode of the thirty-fourth PMOS transistor, the source electrode of the thirty-fourth NMOS transistor, the drain electrode of the thirty-sixth PMOS transistor, the source electrode of the thirty-sixth NMOS transistor, the gate electrode of the thirty-fifth PMOS transistor, and the gate electrode of the thirty-fifth NMOS transistor are connected, and the connection end thereof is the inverted output end of the carry circuit. The circuit is designed by adopting a transmission gate structure, and in a data recovery stage, the circuit comprises a transmission gate consisting of a twenty-first NMOS (N-channel metal oxide semiconductor) tube and a twenty-first PMOS (P-channel metal oxide semiconductor) tube, a transmission gate consisting of a twenty-second NMOS tube and a twenty-second PMOS tube, a transmission gate consisting of a twenty-third NMOS tube and a twenty-third PMOS tube, a transmission gate consisting of a twenty-fourth NMOS tube and a twenty-fourth PMOS tube, a transmission gate consisting of a twenty-fifth NMOS tube and a twenty-fifth PMOS tube, a transmission gate consisting of a twenty-sixth NMOS tube and a twenty-sixth PMOS tube, a transmission gate consisting of a twenty-seventh NMOS tube and a twenty-seventh PMOS tube, a transmission gate consisting of a twenty-eighth NMOS tube and a twenty-eighth PMOS tube, a transmission gate consisting of a twenty-ninth NMOS tube and a twenty-ninth PMOS tube, a transmission gate consisting of a thirty NMOS tube and a thirty PMOS tube, a transmission gate consisting of a thirty-eleventh NMOS tube and a thirty-second PMOS tube, a transmission gate consisting of a thirty-second PMOS tube and a, The transfer gate composed of a thirty-third NMOS transistor and a thirty-third PMOS transistor, the transfer gate composed of a thirty-fourth NMOS transistor and a thirty-fourth PMOS transistor, the signal voltage is reduced to 0V, and the charge passes through the transfer gate composed of the twenty-first NMOS transistor and the twenty-first PMOS transistor, the transfer gate composed of the twenty-second NMOS transistor and the twenty-second PMOS transistor, the transfer gate composed of the twenty-third NMOS transistor and the twenty-third PMOS transistor, the transfer gate composed of the twenty-fourth NMOS transistor and the twenty-fourth PMOS transistor, the transfer gate composed of the twenty-fifth NMOS transistor and the twenty-fifth PMOS transistor, the transfer gate composed of the twenty-sixth NMOS transistor and the twenty-sixth PMOS transistor, the transfer gate composed of the twenty-seventh NMOS transistor and the twenty-seventh PMOS transistor, the transfer gate composed of the twenty-eighth NMOS transistor and the twenty-eighth PMOS transistor, the transfer gate composed of the twenty-ninth NMOS transistor and the twenty-ninth PMOS transistor, and the transfer gate composed of the twenty-ninth PMOS transistor, The transmission gate formed by the thirty-second NMOS transistor and the thirty-third PMOS transistor, the transmission gate formed by the thirty-first NMOS transistor and the thirty-first PMOS transistor, the transmission gate formed by the thirty-second NMOS transistor and the thirty-second PMOS transistor, the transmission gate formed by the thirty-third NMOS transistor and the thirty-third PMOS transistor, and the transmission gate formed by the thirty-fourth NMOS transistor and the thirty-fourth PMOS transistor are transmitted to the power clock input end of the carry circuit, and threshold loss does not exist.
The two-input and gate comprises a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a thirty-seventh NMOS tube, a thirty-eighth NMOS tube and a thirty-ninth NMOS tube, wherein the source electrode of the thirty-seventh PMOS tube, the source electrode of the thirty-eighth PMOS tube and the source electrode of the thirty-ninth PMOS tube are all connected with a power supply, the grid electrode of the thirty-seventh PMOS tube is connected with the grid electrode of the thirty-seventh NMOS tube, the connection end of the thirty-seventh PMOS tube is the first input end of the two-input and gate, the grid electrode of the thirty-eighth PMOS tube is connected with the grid electrode of the thirty-eighth NMOS tube, the connection end of the thirty-eighth PMOS tube is the second input end of the two-input and gate, the drain electrode of the thirty-seventh PMOS tube, the drain electrode of the thirty-seventh NMOS tube, the drain electrode of the thirty-eighth PMOS tube, the grid electrode of the thirty-ninth PMOS tube and the gate of the thirty-ninth NMOS tube are connected, the source electrode of the thirty-seventh NMOS transistor and the second NMOS transistorThe drain electrodes of the thirty-eight NMOS tubes are connected, the drain electrodes of the thirty-ninth PMOS tube and the thirty-ninth NMOS tube are connected, the connection end of the drain electrode of the thirty-ninth PMOS tube and the drain electrode of the thirty-ninth NMOS tube is the output end of the two-input AND gate, and the source electrodes of the thirty-eighth NMOS tube and the thirty-ninth NMOS tube are respectively grounded. The circuit is composed of text signals under the traditional CMOS process0x0And2x2direct generation of1x1The function of (2) reduces the generation circuit of the multi-valued signal and the hardware expense of the circuit.
Compared with the prior art, the invention has the advantages that the multi-bit multi-value adiabatic multiplier based on the transmission gate structure is constructed by the n-bit multi-value adiabatic multiplier unit, wherein n is an integer greater than or equal to 2, the multi-value adiabatic multiplier unit is provided with a first input end, a second input end, a low carry signal input end, a clock control clock signal input end, a first power clock signal input end, a second power clock signal input end, a local product output end, an inverted local product output end, a high carry signal output end and an inverted high carry signal output end, the multi-value adiabatic multiplier unit comprises a gate control circuit, a local product circuit and a carry circuit, and the gate control circuit is provided with a first input end, a second input end, a third input end, a first output end, a second output end, a third output end, a fourth output end, a fifth output end, a sixth output end, a seventh, An eighth output terminal, a ninth output terminal, a first inverted output terminal, a second inverted output terminal, a third inverted output terminal, a fourth inverted output terminal, a fifth inverted output terminal, a sixth inverted output terminal, a seventh inverted output terminal, an eighth inverted output terminal, a ninth inverted output terminal, a clock-controlled clock signal input terminal and a power clock signal input terminal; the local bit product circuit is provided with a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a sixth input end, a first inverted input end, a second inverted input end, a third inverted input end, a fourth inverted input end, a fifth inverted input end, a sixth inverted input end, a clock control clock signal input end, a first power clock signal input end, a second power clock signal input end, an output end and an inverted output end; the carry circuit is provided with a clock-controlled clock signal input end, a power clock signal input end, a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a sixth input end, a seventh input end, a first inverted input end, a second inverted input end, a third inverted input end, a fourth inverted input end, a fifth inverted input end, a sixth inverted input end, a seventh inverted input end, an output end and an inverted output end; the first input end of the gate control circuit is the first input end of the multi-valued adiabatic multiplier unit, the second input end of the gate control circuit is the second input end of the multi-valued adiabatic multiplier unit, the third input end of the gate control circuit is the low-order carry signal input end of the multi-valued adiabatic multiplier unit, the clock control clock signal input end of the gate control circuit, the clock control clock signal input end of the local product circuit and the clock control clock signal input end of the carry circuit are connected, the connection end of the gate control circuit and the local product circuit is the clock control clock signal input end of the multi-valued adiabatic multiplier unit, the connection end of the gate control circuit and the local product circuit is the first power clock signal input end of the carry circuit, the second power clock signal input end of the local product circuit is the second power clock signal input end of the multi-valued adiabatic multiplier unit, the first output end of the gate control circuit is respectively connected with the first input end of the local product circuit and the first input end of the carry circuit, the second output end of the gate control circuit is respectively connected with the second input end of the local product circuit and the second input end of the carry circuit, the third output end of the gate control circuit is respectively connected with the third input end of the local product circuit and the third input end of the carry circuit, the fourth output end of the gate control circuit is respectively connected with the fourth input end of the local product circuit and the fourth input end of the carry circuit, the fifth output end of the gate control circuit is respectively connected with the fifth input end of the local product circuit and the fifth input end of the carry circuit, the sixth output end of the gate control circuit is respectively connected with the sixth input end of the local product circuit and the sixth input end of the carry circuit, the seventh output end of the gate control circuit is connected with the seventh input end of the carry circuit, and the first inverting output end of the gate control circuit is respectively connected with the first inverting input end of the local product circuit and the first inverting input The phase input ends are connected, the second inverted output end of the gate control circuit is respectively connected with the second inverted input end of the local product circuit and the second inverted input end of the carry circuit, the third inverted output end of the gate control circuit is respectively connected with the third inverted input end of the local product circuit and the third inverted input end of the carry circuit, the fourth inverted output end of the gate control circuit is respectively connected with the fourth inverted input end of the local product circuit and the fourth inverted input end of the carry circuit, the fifth inverted output end of the gate control circuit is respectively connected with the fifth inverted input end of the local product circuit and the fifth inverted input end of the carry circuit, the sixth inverted output end of the gate control circuit is respectively connected with the sixth inverted input end of the local product circuit and the sixth inverted input end of the carry circuit, the seventh inverted output end of the gate control circuit is connected with the seventh inverted input end of the carry circuit, and the output end of the local product circuit is the local product output end of the multi-valued adiabatic multiplier unit, the reverse phase output end of the local product circuit is the reverse phase local product output end of the multi-valued adiabatic multiplier unit, the output end of the carry circuit is the high-order carry signal output end of the multi-valued adiabatic multiplier unit, the reverse phase output end of the carry circuit is the reverse phase high-order carry signal output end of the multi-valued adiabatic multiplier unit, the clock control clock signal input end of the n-valued multi-valued adiabatic multiplier unit is connected with the reverse phase high-order carry signal output end of the n-valued multi-valued adiabatic multiplier unit, the connecting end of the clock control clock signal input end of the n-valued multi-valued adiabatic multiplier unit is the clock control clock signal input end of the multi-valued adiabatic multiplier unit and used for accessing the first power clock signal, the second power clock signal input ends of all the multi-valued adiabatic multiplier units which are located at even number in the n-valued multi-valued adiabatic multiplier unit are connected, and the connecting end of the second power The connecting end is a second clock control clock signal input end of the multi-bit multi-valued adiabatic multiplier and is used for accessing a second power clock signal, the second power clock signal input ends of all multi-valued adiabatic multiplier units positioned at odd bits in the n-bit multi-valued adiabatic multiplier unit are connected, the connecting end is a third clock control clock signal input end of the multi-bit multi-valued adiabatic multiplier and is used for accessing a third power clock signal, the amplitude levels of the clock control clock signal and the first power clock signal are the same, the phase difference between the clock control clock signal and the first power clock signal is 180 degrees, the phases of the first power clock signal and the second power clock signal are the same, the amplitude level of the first power clock signal is 2 times that of the amplitude level of the second power clock signal, the amplitude levels of the third power clock signal and the second power clock signal are the same, and the phase difference between the third power clock; the high-order carry signal output end of the kth multi-value adiabatic multiplier unit is connected with the low-order carry signal input end of the (k + 1) th multi-value adiabatic multiplier unit, and k is 1, 2, … and n-1; the first input end of the jth multivalue adiabatic multiplier unit is used for accessing the jth bit signal of a first multiplier, the second input end of the jth multivalue adiabatic multiplier unit is used for accessing the jth bit signal of a second multiplier, j is 1, 2, …, n, the product circuit and the carry circuit are both realized by adopting a fully adiabatic mode, charges in the product circuit are recovered in a fully adiabatic recovery mode, the power consumption of the circuit is reduced, and meanwhile, the multivalue signals in the product circuit are realized by adopting a binary mode of gate control circuit switch control, so that the working speed of the circuit can be improved, the operation period can be shortened, the hardware expense of the circuit is reduced, and the area of the product circuit is smaller.
Drawings
FIG. 1(a) is a block diagram of a multi-bit multivalued adiabatic multiplier of the present invention;
FIG. 1(b) is a block diagram of a multiple-valued adiabatic multiplier cell of the present invention;
FIG. 2(a) is a symbol diagram of a gate control circuit of the multivalued adiabatic multiplier cell circuit of the present invention;
FIG. 2(b) is a block diagram of a gating circuit of the multivalued adiabatic multiplier cell circuit of the present invention;
FIG. 2(c) is a symbolic diagram of a first gate control unit of the multi-valued adiabatic multiplier cell circuit of the present invention;
FIG. 3 is a circuit diagram of a first gate control cell of the multi-valued adiabatic multiplier cell circuit of the present invention;
FIG. 4 is a circuit diagram of a local product circuit of the multi-valued adiabatic multiplier cell circuit of the present invention;
FIG. 5 is a circuit diagram of a carry circuit of the multi-valued adiabatic multiplier cell circuit of the present invention;
FIG. 6 is a waveform diagram of a clock signal of a multi-valued adiabatic multiplier cell circuit of the present invention;
FIG. 7 is a circuit diagram of a two-input AND gate of the multi-valued adiabatic multiplier cell circuit of the present invention;
FIG. 8 is a simulation diagram of the operation of the multi-bit multivalued adiabatic multiplier of the present invention;
FIG. 9 is a simulation diagram of the static noise margin of the multi-bit multivalued adiabatic multiplier of the present invention;
FIG. 10 is a test waveform for power consumption and leakage power for a multi-bit multivalued adiabatic multiplier of the present invention;
FIG. 11 is a power consumption delay product waveform of the multi-bit multi-valued adiabatic multiplier of the present invention under voltage fluctuation;
fig. 12 is a diagram comparing power consumption of the multi-bit multi-valued adiabatic multiplier of the present invention with that of a conventional multiplier.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The first embodiment is as follows: as shown in FIGS. 1(a), 1(b) and 2(a), a multi-bit multi-valued adiabatic multiplier based on transmission gate structure comprises an n-bit multi-valued adiabatic multiplier unit, wherein n is an integer greater than or equal to 2, the multi-valued adiabatic multiplier unit has a first input terminal, a second input terminal, a low carry signal input terminal, a clock control clock signal input terminal, a first power clock signal input terminal, a second power clock signal input terminal, a local product output terminal, an inverted local product output terminal, a high carry signal output terminal and an inverted high carry signal output terminal, the multi-valued adiabatic multiplier unit comprises a gate control circuit 1, a local product circuit 2 and a carry circuit 3, the gate control circuit 1 has a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal and a sixth output terminal, A seventh output terminal, an eighth output terminal, a ninth output terminal, a first inverting output terminal, a second inverting output terminal, a third inverting output terminal, a fourth inverting output terminal, a fifth inverting output terminal,A sixth inverted output terminal, a seventh inverted output terminal, an eighth inverted output terminal, a ninth inverted output terminal, a clock-controlled clock signal input terminal, and a power clock signal input terminal; the local product circuit 2 has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a sixth input terminal, a first inverted input terminal, a second inverted input terminal, a third inverted input terminal, a fourth inverted input terminal, a fifth inverted input terminal, a sixth inverted input terminal, a clock-controlled clock signal input terminal, a first power clock signal input terminal, a second power clock signal input terminal, an output terminal, and an inverted output terminal; the carry circuit 3 has a clocked clock signal input terminal, a power clock signal input terminal, a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a sixth input terminal, a seventh input terminal, a first inverting input terminal, a second inverting input terminal, a third inverting input terminal, a fourth inverting input terminal, a fifth inverting input terminal, a sixth inverting input terminal, a seventh inverting input terminal, an output terminal, and an inverting output terminal; the first input end of the gate control circuit 1 is the first input end of the multi-valued adiabatic multiplier unit, the second input end of the gate control circuit 1 is the second input end of the multi-valued adiabatic multiplier unit, the third input end of the gate control circuit 1 is the low-order carry signal input end of the multi-valued adiabatic multiplier unit, the clock control clock signal input end of the gate control circuit 1, the clock control clock signal input end of the local integrating circuit 2 and the clock control clock signal input end of the carry circuit 3 are connected, the connection end of the input ends is the clock control clock signal input end of the multi-valued adiabatic multiplier unit, the power clock signal input end of the gate control circuit 1, the first power clock signal input end of the local integrating circuit 2 and the power clock signal input end of the carry circuit 3 are connected, the connection end of the input ends is the first power clock signal input end of the multi-valued adiabatic multiplier unit, the second power clock signal input end of the local integrating circuit 2 is the second power, the first output end of the gate control circuit 1 is respectively connected with the first input end of the local bit-product circuit 2 and the first input end of the carry circuit 3, and the second output end of the gate control circuit 1 is respectively connected with the second input end of the local bit-product circuit 2 and the second input end of the carry circuit 3The second input end of the gate control circuit 1 is connected, the third output end of the gate control circuit 1 is respectively connected with the third input end of the local product circuit 2 and the third input end of the carry circuit 3, the fourth output end of the gate control circuit 1 is respectively connected with the fourth input end of the local product circuit 2 and the fourth input end of the carry circuit 3, the fifth output end of the gate control circuit 1 is respectively connected with the fifth input end of the local product circuit 2 and the fifth input end of the carry circuit 3, the sixth output end of the gate control circuit 1 is respectively connected with the sixth input end of the local product circuit 2 and the sixth input end of the carry circuit 3, the seventh output end of the gate control circuit 1 is connected with the seventh input end of the carry circuit 3, the first inverting output end of the gate control circuit 1 is respectively connected with the first inverting input end of the local product circuit 2 and the first inverting input end of the carry circuit 3, and the second inverting output end of the gate control circuit 1 is respectively connected with the second inverting input end of the local product circuit 2 and the second inverting input end of the carry circuit Then, the third inverted output terminal of the gate control circuit 1 is connected to the third inverted input terminal of the local product circuit 2 and the third inverted input terminal of the carry circuit 3, the fourth inverted output terminal of the gate control circuit 1 is connected to the fourth inverted input terminal of the local product circuit 2 and the fourth inverted input terminal of the carry circuit 3, the fifth inverted output terminal of the gate control circuit 1 is connected to the fifth inverted input terminal of the local product circuit 2 and the fifth inverted input terminal of the carry circuit 3, the sixth inverted output terminal of the gate control circuit 1 is connected to the sixth inverted input terminal of the local product circuit 2 and the sixth inverted input terminal of the carry circuit 3, the seventh inverted output terminal of the gate control circuit 1 is connected to the seventh inverted input terminal of the carry circuit 3, the output terminal of the local product circuit 2 is the local product output terminal of the multi-valued adiabatic multiplier unit, the inverted output terminal of the local product circuit 2 is the inverted local product output terminal of the multi-valued adiabatic multiplier unit, the output end of the carry circuit 3 is a high-order carry signal output end of the multi-valued adiabatic multiplier unit, the reverse-phase output end of the carry circuit 3 is a reverse-phase high-order carry signal output end of the multi-valued adiabatic multiplier unit, the clock control clock signal input end of the n-th multi-valued adiabatic multiplier unit is connected with the reverse-phase high-order carry signal output end of the nth multi-valued adiabatic multiplier unit, the connecting end of the n-th multi-valued adiabatic multiplier unit is a clock control clock signal input end of the multi-valued adiabatic multiplier unit and isClocked clock signal
Figure GDA0002441975720000161
The first power clock signal input ends of the n-bit multi-valued adiabatic multiplier units are connected, the connection ends of the n-bit multi-valued adiabatic multiplier units are first clock control clock signal input ends of the multi-valued adiabatic multiplier units, the first clock control clock signal input ends are used for accessing a first power clock signal phi, the second power clock signal input ends of all the even-numbered multi-valued adiabatic multiplier units in the n-bit multi-valued adiabatic multiplier units are connected, the connection ends of the n-bit multi-valued adiabatic multiplier units are second clock control clock signal input ends of the multi-valued adiabatic multiplier units, the second power clock signal input ends of all the odd-numbered multi-valued adiabatic multiplier units in the n-bit multi-valued adiabatic multiplier units are connected, the connection ends of the n-bit multi-valued adiabatic multiplier units are third clock
Figure GDA0002441975720000162
The clock control clock signal and the first power clock signal phi have the same amplitude level and have a phase difference of 180 degrees, the first power clock signal phi and the second power clock signal phi 1 have the same phase, the amplitude level of the first power clock signal phi is 2 times of that of the second power clock signal phi 1, and the third power clock signal phi
Figure GDA0002441975720000163
The amplitude level of the second power clock signal phi 1 is the same as that of the second power clock signal phi 1, and the phase difference between the two is 180 degrees; the high-order carry signal output end of the kth multi-value adiabatic multiplier unit is connected with the low-order carry signal input end of the (k + 1) th multi-value adiabatic multiplier unit, and k is 1, 2, … and n-1; the first input end of the j-th multivalued adiabatic multiplier unit is used for accessing the j-th bit signal of the first multiplier, the second input end of the j-th multivalued adiabatic multiplier unit is used for accessing the j-th bit signal of the second multiplier, and j is 1, 2, …, n.
In this embodiment, as shown in fig. 2(b) and 2(c), the gate control circuit 1 includes three gate control units and nine binary inverters, each gate control unit has an input end, a clock signal input end, a power clock signal input end, a first output end, a second output end, and a third output end, the three gate control units are a first gate control unit T1, a second gate control unit T2, and a third gate control unit T3, and the nine binary inverters are a first binary inverter NOT1, a second binary inverter NOT2, a third binary inverter NOT3, a fourth binary inverter NOT4, a fifth binary inverter NOT5, a sixth binary inverter NOT6, a seventh binary inverter NOT7, an eighth binary inverter NOT8, and a ninth binary inverter NOT 9; a first output end of the first gate control unit T1 is connected to an input end of the first binary inverter NOT1, and a connection end thereof is a first output end of the gate control circuit 1, an output end of the first binary inverter NOT1 is a first inverted output end of the gate control circuit 1, a second output end of the first gate control unit T1 is connected to an input end of the second binary inverter NOT2, and a connection end thereof is a second output end of the gate control circuit 1, an output end of the second binary inverter NOT2 is a second inverted output end of the gate control circuit 1, a third output end of the first gate control unit T1 is connected to an input end of the third binary inverter NOT3, and a connection end thereof is a third output end of the gate control circuit 1, an output end of the third binary inverter NOT3 is a third inverted output end of the gate control circuit 1, a first output end of the second gate control unit T2 is connected to an input end of the fourth binary inverter NOT4, and a connection end thereof is a fourth output end of the gate control circuit 1, the output end of the fourth binary inverter NOT4 is a fourth inverted output end of the gate control circuit 1, the second output end of the second gate control unit T2 is connected with the input end of the fifth binary inverter NOT5, the connection end of the second binary inverter NOT5 is a fifth output end of the gate control circuit 1, the output end of the fifth binary inverter NOT5 is a fifth inverted output end of the gate control circuit 1, the third output end of the second gate control unit T2 is connected with the input end of the sixth binary inverter NOT6, the connection end of the third gate control unit T2 is a sixth output end of the gate control circuit 1, the output end of the sixth binary inverter NOT6 is a sixth inverted output end of the gate control circuit 1, the first output end of the third gate control unit T3 is connected with the input end of the seventh binary inverter NOT7, the connection end of the seventh output end of the gate control circuit 1, the output end of the seventh binary inverter NOT7 is a seventh inverted output end of the gate control circuit 1, the second output end of the third gate control unit T3 is connected with the eighth binary inverter NOT8, the connection end of An output terminal, an output terminal of the eighth binary inverter NOT8 is an eighth inverted output terminal of the gate control circuit 1, a third output terminal of the third gate control unit T3 is connected to an input terminal of the ninth binary inverter NOT9, a connection terminal thereof is a ninth output terminal of the gate control circuit 1, an output terminal of the ninth binary inverter NOT9 is a ninth inverted output terminal of the gate control circuit 1, a clock control clock signal input terminal of the first gate control unit T1, a clock control clock signal input terminal of the second gate control unit T2 and a clock control clock signal input terminal of the third gate control unit T3 are connected, a connection terminal thereof is a clock control clock signal input terminal of the gate control circuit 1, a power clock signal input terminal of the first gate control unit T1, a power clock signal input terminal of the second gate control unit T2 and a power clock signal input terminal of the third gate control unit T3 are connected, and a connection terminal thereof is a power clock signal input terminal of the gate control circuit 1, the input terminal of the first gate unit T1 is the first input terminal of the gate control circuit 1, the input terminal of the second gate unit T2 is the second input terminal of the gate control circuit 1, and the input terminal of the third gate unit T3 is the third input terminal of the gate control circuit 1.
In this embodiment, as shown in fig. 3, the first gate control unit T1 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, AND a second input AND gate 1, where the second input AND gate 1 has a first input terminal, a second input terminal, AND an output terminal, a source of the first PMOS transistor P1 is connected to a source of the second PMOS transistor P2, AND a connection terminal thereof is a power clock signal input terminal of the first gate control unit T1, a source of the third PMOS transistor P3 is connected to a source of the fourth PMOS transistor P4, AND a connection terminal thereof is a clock signal input terminal of the first gate control unit T1; the gate of the first PMOS transistor P1, the gate of the first NMOS transistor N1, the gate of the third PMOS transistor P3 AND the gate of the third NMOS transistor N3 are connected AND their connection terminals are input terminals of the first gate control unit T1, the drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the drain of the first NMOS transistor N1 AND the gate of the second NMOS transistor N2 are connected to ground, the source of the first NMOS transistor N1, the source of the second NMOS transistor N2, the source of the third NMOS transistor N3 AND the source of the fourth NMOS transistor N4 are connected to ground, the drain of the third NMOS transistor N3, the gate of the fourth NMOS transistor N4, the drain of the third PMOS transistor P3 AND the gate of the fourth PMOS transistor P589 are connected, the drain of the second PMOS transistor P2, the drain of the second NMOS transistor N2 AND the first input terminal of the second gate control unit N1 are connected AND the first input terminal of the gate control unit T1 AND the drain of the fourth gate control unit N1 AND the second gate control unit N867 AND the drain of the fourth gate control unit N1 AND the fourth gate control unit N867, the output end of the two-input AND gate AND1 is a second output end of the first gate unit T1; the circuit structures of the second gate-controlling unit T2 and the third gate-controlling unit T3 are the same as the circuit structure of the first gate-controlling unit T1.
In this embodiment, the threshold voltage of the first PMOS transistor P1 is-0.6126V, the threshold voltage of the first NMOS transistor N1 is-0.2457V, the threshold voltage of the third NMOS transistor N3 is 0.243V, and the threshold voltage of the third PMOS transistor P3 is 0.4891V.
In this embodiment, as shown in fig. 4, the local product circuit 2 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P8, a tenth PMOS transistor P8, an eleventh PMOS transistor P8, a twelfth PMOS transistor P8, a thirteenth PMOS transistor P8, a fourteenth PMOS transistor P8, a fifteenth PMOS transistor P8, a sixteenth PMOS transistor P8, a seventeenth PMOS transistor P8, an eighteenth PMOS transistor P8, a nineteenth PMOS transistor P8, a twentieth PMOS transistor P8, a fifth NMOS transistor N8, a sixth NMOS transistor N8, a seventh NMOS transistor N8, an eighth NMOS transistor N8, a ninth NMOS transistor N8, a tenth NMOS transistor N8, an eleventh NMOS transistor N8, a twelfth NMOS transistor N8, a thirteenth NMOS transistor N8, a fourteenth NMOS transistor N8, a fifteenth NMOS transistor N8, a seventeenth NMOS transistor N8, a nineteenth NMOS transistor N8, a seventeenth NMOS transistor N8, a nineteenth NMOS transistor N8; a source electrode of a fifth PMOS tube P5, a source electrode of a sixth PMOS tube P6, a drain electrode of a fifth NMOS tube N5, a drain electrode of a sixth NMOS tube N6, a source electrode of a tenth PMOS tube P10, a source electrode of an eleventh PMOS tube P11, a drain electrode of a tenth NMOS tube N10 and a drain electrode of an eleventh NMOS tube N11 are connected and a connection end thereof is a second power clock signal input end of the product circuit 2, a source electrode of a seventh PMOS tube P7, a source electrode of an eighth PMOS tube P8, a drain electrode of a seventh NMOS tube N7, a drain electrode of an eighth NMOS tube N8, a source electrode of a ninth PMOS tube P9, a source electrode of a sixteenth PMOS tube P16, a drain electrode of a ninth NMOS tube N9, a drain electrode of a sixteenth NMOS tube N16, a source electrode of a nineteenth PMOS tube P19 and a source electrode of a twentieth PMOS tube P20 are connected and a connection end thereof is a first power clock signal input end of the product circuit 2, a nineteenth PMOS tube P19 and a drain electrode of the clock signal input end thereof is a nineteenth clock signal input end 20 and a drain electrode of the product circuit N20 and a, the grid of the fifth NMOS transistor N5, the grid of the seventh PMOS transistor P7 and the grid of the tenth NMOS transistor N10 are connected and the connection end is the second input end of the local product circuit 2, the grid of the fifth PMOS transistor P5, the grid of the seventh NMOS transistor N7 and the grid of the tenth PMOS transistor P10 are connected and the connection end is the second inverting input end of the local product circuit 2, the grid of the sixth NMOS transistor N6, the grid of the eighth PMOS transistor P8 and the grid of the eleventh NMOS transistor N11 are connected and the connection end is the third input end of the local product circuit 2, the grid of the sixth PMOS transistor P6, the grid of the eighth NMOS transistor N8 and the grid of the eleventh PMOS transistor P11 are connected and the connection end is the third inverting input end of the local product circuit 2, the grid of the sixteenth NMOS transistor N16 is the first input end of the local product circuit 2, the grid of the sixteenth PMOS transistor P16 is the ninth inverting input end of the first NMOS transistor N9, the gate of the ninth PMOS transistor P9 is the fourth inverting input terminal of the local product circuit 2, the gates of the twelfth and fifteenth PMOS transistors P15 and N17 are connected and the connection end is the fifth input terminal of the local product circuit 2, the gates of the twelfth and fifteenth PMOS transistors P12 and N15 and P17 are connected and the connection end is the fifth inverting input terminal of the local product circuit 2, the gate of the thirteenth NMOS transistor N13, the gate of the fourteenth PMOS transistor P14 and the gate of the eighteenth NMOS transistor N18 are connected and the connection end is the sixth input terminal of the local product circuit 2, the gate of the thirteenth PMOS transistor P13, the gate of the fourteenth NMOS transistor N14 and the gate of the eighteenth PMOS transistor P18 are connected and the connection end is the sixth inverting input terminal of the local product circuit 2, the drain of the fifth PMOS transistor P5, the source of the fifth NMOS transistor P5 and the source of the twelfth NMOS transistor N12 are connected and the source of the twelfth NMOS transistor N12, a drain of a sixth PMOS transistor P6, a source of a sixth NMOS transistor N6, a source of a thirteenth PMOS transistor P13 and a drain of a thirteenth NMOS transistor N13, a drain of a seventh PMOS transistor P7, a source of a seventh NMOS transistor N7, a source of a fourteenth PMOS transistor P14 and a drain of a fourteenth NMOS transistor N14, a drain of an eighth PMOS transistor P8, a source of an eighth NMOS transistor N8, a source of a fifteenth PMOS transistor P15 and a drain of a fifteenth NMOS transistor N15, a drain of a tenth PMOS transistor P10, a source of a tenth NMOS transistor N10, a source of a seventeenth PMOS transistor P17 and a drain of a seventeenth NMOS transistor N17, a drain of an eleventh PMOS transistor P11, a source of an eleventh NMOS transistor N11, a source of an eighteenth PMOS transistor P18 and a drain of an eighteenth NMOS transistor N18, a drain of a twelfth PMOS transistor P12, a source of a thirteenth NMOS transistor N12, a source of a fourteenth PMOS transistor P12, a fourteenth NMOS transistor N12, a drain of a fourteenth PMOS transistor N12 and a drain of a fourteenth PMOS transistor N12, The drain of the fifteenth PMOS transistor P15, the source of the fifteenth NMOS transistor N15, the drain of the nineteenth PMOS transistor P19, the source of the nineteenth NMOS transistor N19, the gate of the twentieth PMOS transistor P20 and the gate of the twentieth NMOS transistor N20 are connected and their connection terminals are the output terminal of the product circuit 2, the drain of the ninth PMOS transistor P9, the source of the ninth NMOS transistor N9, the drain of the sixteenth PMOS transistor P16, the source of the sixteenth NMOS transistor N16, the drain of the seventeenth PMOS transistor P17, the source of the seventeenth NMOS transistor N17, the drain of the eighteenth PMOS transistor P18, the source of the eighteenth NMOS transistor N18, the drain of the twentieth PMOS transistor P20, the source of the twentieth NMOS transistor N20, the gate of the nineteenth PMOS transistor P19 and the gate of the nineteenth NMOS transistor N19 are connected and their connection terminals are the inverse phase of the product circuit 2.
In this embodiment, as shown in fig. 5, the carry circuit 3 includes a twenty-first PMOS transistor P21, a twenty-second PMOS transistor P22, a twenty-third PMOS transistor P23, a twenty-fourth PMOS transistor P24, a twenty-fifth PMOS transistor P25, a twenty-sixth PMOS transistor P26, a twenty-seventh PMOS transistor P27, a twenty-eighth PMOS transistor P28, a twenty-ninth PMOS transistor P29, a thirty-sixth PMOS transistor P30, a thirty-eleventh PMOS transistor P30, a thirty-second PMOS transistor P30, a thirty-third PMOS transistor P30, a thirty-fourth PMOS transistor P30, a thirty-fifth PMOS transistor P30, a thirty-sixth PMOS transistor P30, a twenty-first NMOS transistor N30, a twenty-second NMOS transistor N30, a twenty-third NMOS transistor N30, a twenty-fourth NMOS transistor N30, a twenty-fifth NMOS transistor N30, a twenty-sixth PMOS transistor N30, a twenty-sixth NMOS transistor N30, a twenty-eighth NMOS transistor N30, a thirty-fourth NMOS transistor N30, a thirty-fifth NMOS transistor N30, a thirty-ninth NMOS transistor N30, a thirty-eighth NMOS transistor N30, a thirty-fifth NMOS transistor N, A thirty-fifth NMOS transistor N35 and a thirty-sixth NMOS transistor N36, a source of a twenty-first PMOS transistor P21, a drain of a twenty-first NMOS transistor N21, a source of a twenty-second PMOS transistor P22, a drain of a twenty-second NMOS transistor N22, a source of a twenty-third PMOS transistor P23, a drain of a twenty-third NMOS transistor N23, a source of a twenty-fourth PMOS transistor P24, a drain of a twenty-fourth NMOS transistor N24, a source of a twenty-fifth PMOS transistor P25, a drain of a twenty-fifth NMOS transistor N25, a source of a twenty-ninth PMOS transistor P29, a drain of a twenty-ninth NMOS transistor N29, a source of a thirty-fifth transistor P35, and a source of a thirty-sixth PMOS transistor P36, which are connected, and a connection terminal of which is a power clock signal input terminal of the carry 3, a thirty-fifth NMOS transistor N35, a drain of a thirty-sixth NMOS transistor N36, a drain of a connection terminal of a thirty-sixth NMOS transistor N463, a gate of a connection terminal of a twenty-fifth NMOS transistor N26, and a gate of a thirty-sixth clock signal input terminal of a twenty-fifth NMOS transistor N463, a gate of a twenty-fifth NMOS transistor N26 A gate of the twenty-first PMOS transistor P21, a gate of the twenty-sixth PMOS transistor P26, and a gate of the thirty-second PMOS transistor P32 are connected and connection terminals thereof are third inverting input terminals of the carry circuit 3, a gate of the twenty-second NMOS transistor N22 and a gate of the twenty-third PMOS transistor P23 are connected and connection terminals thereof are seventh input terminals of the carry circuit 3, a gate of the twenty-second PMOS transistor P22 and a gate of the twenty-third NMOS transistor N23 are connected and connection terminals thereof are seventh inverting input terminals of the carry circuit 3, a gate of the twenty-fourth NMOS transistor N24, a gate of the twenty-seventh NMOS transistor N27, and a gate of the thirty-third NMOS transistor N33 are connected and connection terminals thereof are second input terminals of the carry circuit 3, a gate of the twenty-fourth PMOS transistor P24, a gate of the twenty-seventh PMOS transistor P27, and a gate of the thirty-third PMOS transistor P33 are connected and connection terminals thereof are second inverting input terminals of the carry circuit 3, a gate of the twenty-fifth inverting NMOS transistor N25 is a first inverting input terminal of the carry circuit 3, the grid of the twenty-fifth PMOS tube P25 is the first inverting input end of the carry circuit 3, the grid of the twenty-eighth NMOS tube N28, the grid of the thirty-eleventh NMOS tube N31 and the grid of the thirty-fourth NMOS tube N34 are connected, the connection end of the grid is the fifth input end of the carry circuit 3, the grid of the twenty-eighth PMOS tube P28, the grid of the thirty-eleventh PMOS tube P31 and the grid of the thirty-fourth PMOS tube P34 are connected, the connection end of the grid is the fifth inverting input end of the carry circuit 3, the grid of the twenty-ninth NMOS tube N29 is the fourth input end of the carry circuit 3, the grid of the twenty-ninth PMOS tube P29 is the fourth inverting input end of the carry circuit 3, the grid of the thirty-NMOS tube N30 is the sixth input end of the carry circuit 3, the grid of the thirty-fifth NMOS tube P30 is the sixth inverting input end of the carry circuit 3, the drain of the twenty-first PMOS tube P21, the source of the twenty-first NMOS tube N21, the source of the thirty-fourth PMOS tube P30 and the thirty-NMOS tube N30, a drain electrode of a twenty-second PMOS tube P22, a source electrode of a twenty-second NMOS tube N22, a source electrode of a twenty-sixth PMOS tube P26, a drain electrode of a twenty-sixth NMOS tube N26, a source electrode of a twenty-seventh PMOS tube P27 and a drain electrode of a twenty-seventh NMOS tube N27 are connected, a drain electrode of a twenty-sixth PMOS tube P26, a source electrode of a twenty-sixth NMOS tube N26, a drain electrode of a thirty-eleventh NMOS tube N31 and a source electrode of a thirty-eleventh PMOS tube P31 are connected, a drain electrode of a twenty-seventh PMOS tube P27, a source electrode of a twenty-seventh NMOS tube N27, a drain electrode of a thirty-second PMOS tube N32 and a source electrode of a thirty-second PMOS tube P32 are connected, a drain electrode of a twenty-third PMOS tube P23, a source electrode of a twenty-third NMOS tube N23, a source electrode of a thirty-third PMOS tube P33, a drain electrode of a twenty-eighth PMOS tube P639, a drain electrode of a twenty-fourth PMOS tube P8653 and a fourth NMOS tube P828653 and a fourth PMOS tube N8653 are connected, a drain of the thirty-first PMOS transistor P30, a source of the thirty-second NMOS transistor N30, a drain of the thirty-first PMOS transistor P31, a source of the thirty-first NMOS transistor N31, a drain of the thirty-second PMOS transistor P32, a source of the thirty-second NMOS transistor N32, a drain of the thirty-fifth PMOS transistor P35, a source of the thirty-fifth NMOS transistor N35, a gate of the thirty-sixth PMOS transistor P36, and a gate of the thirty-sixth NMOS transistor N36 are connected and a connection end thereof is an output end of the carry circuit 3, a drain of the twenty-fifth PMOS transistor P25, a source of the twenty-fifth NMOS transistor N25, a drain of the twenty-eighth PMOS transistor P28, a source of the twenty-eighth NMOS transistor N28, a drain of the twenty-ninth PMOS transistor P29, a source of the twenty-ninth NMOS transistor N29, a drain of the thirty-third PMOS transistor P33, a source of the thirty-third NMOS transistor N33, a drain of the thirty-fourth PMOS transistor P34, a source of the thirty-fourth PMOS transistor P585, a source of the thirty-sixth NMOS transistor N36, a thirty-sixth NMOS transistor P57324, a, The gate of the thirty-fifth PMOS transistor P35 is connected to the gate of the thirty-fifth NMOS transistor N35, and the connection terminal is the inverted output terminal of the carry circuit 3.
Example two: the present embodiment is substantially the same as the present embodiment, except that in the present embodiment, as shown in fig. 7, the two-input AND gate AND1 includes a thirty-seventh PMOS transistor P37, a thirty-eighth PMOS transistor P38, a thirty-ninth PMOS transistor P39, a thirty-seventh NMOS transistor N37, a thirty-eighth NMOS transistor N38 AND a thirty-ninth NMOS transistor N39, the source of the thirty-seventh PMOS transistor P37, the source of the thirty-eighth PMOS transistor P38 AND the source of the thirty-ninth PMOS transistor P39 are all connected to the power supply VDD, the gate of the thirty-seventh PMOS transistor P37 AND the gate of the thirty-seventh NMOS transistor N37 are connected AND the connection end thereof is the first input end of the two-input AND gate 8, the gate of the thirty-eighth PMOS transistor P38 AND the gate of the thirty-eighth NMOS transistor N38 are connected AND the connection end thereof is the second input end of the two-input AND gate 1, the drain of the thirty-seventh PMOS transistor P37, the drain 37, the drain of the thirty-eighth PMOS transistor P38 AND the thirty-ninth NMOS transistor P39 are connected, the source of the thirty-seventh NMOS transistor N37 is connected to the drain of the thirty-eighth NMOS transistor N38, the drain of the thirty-ninth PMOS transistor P39 is connected to the drain of the thirty-ninth NMOS transistor N39, AND the connection terminal is the output terminal of the two-input AND gate AND1, AND the source of the thirty-eighth NMOS transistor N38 AND the source of the thirty-ninth NMOS transistor N39 are grounded, respectively.
When the multi-bit multi-valued adiabatic multiplier of the invention consists of 4 multi-valued adiabatic multiplication units, a four-bit multi-valued adiabatic multiplier is obtained, the behavior of the four-bit multi-valued adiabatic multiplier of the invention in three periods is simulated, the effective function of the invention is verified, and the simulation result is shown in figure 8, wherein M is shown in figure 8nd4Mnd3Mnd2Mnd1Is the first multiplier (multiplicand M)nd)，Mer4Mer3Mer2Mer1Is the second multiplier (multiplier M)er) P4P3P2P1 is the product output,
Figure GDA0002441975720000221
is the complement of the product output, Cout is the carry output,
Figure GDA0002441975720000222
is the carry output. As can be seen from analyzing fig. 8, the product output P4P3P2P1 and the carry output Cout satisfy the design requirement of the four-bit multi-valued adiabatic multiplier, thereby verifying the validity of the function of the designed circuit.
The Static Noise Margin (SNM) of the four-bit multivalued adiabatic multiplier of the present invention was simulated under the condition of the standard voltage temperature (PVT) characteristics, and the simulation result is shown in fig. 9.
The four-bit multivalued adiabatic multiplier of the present invention was experimentally tested for power consumption and leakage power, with test waveforms as shown in fig. 10. At a normal voltage of 1.2V, the average delay of the four-bit multivalued adiabatic multiplier is 148ps, the power consumption is 110pW, and the leakage power is 0.22mW at room temperature for the slowest output signal. At a voltage of 1.2V, the worst case power and leakage power were 300mW and 0.58mW, respectively.
The power consumption delay product waveform of the four-bit multivalued adiabatic multiplier under the voltage fluctuation is shown in figure 11. As can be seen from fig. 11, the power consumption delay product increases linearly with increasing voltage.
The four-bit multivalued adiabatic Multiplier (MVAL) of the present invention has a power consumption reduction of more than 400% compared to a conventional CMOS multiplier at the same operating frequency (ref: Radix-4and Radix-8booth encoded multi-modules, IEEE trans.on Circuits system.I: Regul.Pap.2013,60(11): 2940-. As can be seen from the analysis of fig. 12, the four-bit multivalued adiabatic Multiplier (MVAL) of the present invention reduces power consumption by 45% relative to a three-value dynamic circuit.

Claims (7)

1. A multi-bit multi-valued adiabatic multiplier based on a transmission gate structure is characterized by comprising an n-bit multi-valued adiabatic multiplier unit, wherein n is an integer greater than or equal to 2, the multi-valued adiabatic multiplier unit is provided with a first input end, a second input end, a low carry signal input end, a clock control clock signal input end, a first power clock signal input end, a second power clock signal input end, a local product output end, an inverted local product output end, a high carry signal output end and an inverted high carry signal output end, the multi-valued adiabatic multiplier unit comprises a gate control circuit, a local product circuit and a carry circuit, and the gate control circuit is provided with a first input end, a second input end, a third input end, a first output end, a second output end, a third output end, a fourth output end, a fifth output end, a sixth output end, a seventh output end, a first input end, a second input end, An eighth output terminal, a ninth output terminal, a first inverted output terminal, a second inverted output terminal, a third inverted output terminal, a fourth inverted output terminal, a fifth inverted output terminal, a sixth inverted output terminal, a seventh inverted output terminal, an eighth inverted output terminal, a ninth inverted output terminal, a clock-controlled clock signal input terminal and a power clock signal input terminal; the local product circuit is provided with a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a sixth input end, a first inverted input end, a second inverted input end, a third inverted input end, a fourth inverted input end, a fifth inverted input end, a sixth inverted input end, a clock-controlled clock signal input end, a first power clock signal input end, a second power clock signal input end, an output end and an inverted output end; the carry circuit is provided with a clock-controlled clock signal input end, a power clock signal input end, a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a sixth input end, a seventh input end, a first inverted input end, a second inverted input end, a third inverted input end, a fourth inverted input end, a fifth inverted input end, a sixth inverted input end, a seventh inverted input end, an output end and an inverted output end; the first input end of the gate control circuit is the first input end of the multiple-valued adiabatic multiplier unit, the second input end of the gate control circuit is the second input end of the multiple-valued adiabatic multiplier unit, the third input end of the gate control circuit is the low-order carry signal input end of the multiple-valued adiabatic multiplier unit, the clock signal input end of the gate control circuit, the clock signal input end of the local product circuit and the clock signal input end of the carry circuit are connected, the connection end of the gate control circuit, the clock signal input end of the local product circuit and the clock signal input end of the carry circuit is the clock signal input end of the multiple-valued adiabatic multiplier unit, the power clock signal input end of the gate control circuit, the first power clock signal input end of the local product circuit and the power clock signal input end of the carry circuit are connected, and the connection end of the gate control circuit is the first power clock signal input end of the multiple-valued adiabatic multiplier unit, the second power clock signal input end of the local product circuit is the second power clock signal input end of the multivalued adiabatic multiplier unit, the first output end of the gate control circuit is respectively connected with the first input end of the local product circuit and the first input end of the carry circuit, the second output end of the gate control circuit is respectively connected with the second input end of the local product circuit and the second input end of the carry circuit, the third output end of the gate control circuit is respectively connected with the third input end of the local product circuit and the third input end of the carry circuit, the fourth output end of the gate control circuit is respectively connected with the fourth input end of the local product circuit and the fourth input end of the carry circuit, the fifth output end of the gate control circuit is respectively connected with the fifth input end of the local product circuit and the fifth input end of the carry circuit, the sixth output end of the gate control circuit is respectively connected with the sixth input end of the local product circuit and the sixth input end of the carry circuit, the seventh output end of the gate control circuit is connected with the seventh input end of the carry circuit, the first inverting output end of the gate control circuit is respectively connected with the first inverting input end of the local product circuit and the first inverting input end of the carry circuit, the second inverting output end of the gate control circuit is respectively connected with the second inverting input end of the local product circuit and the second inverting input end of the carry circuit, the third inverting output end of the gate control circuit is respectively connected with the third inverting input end of the local product circuit and the third inverting input end of the carry circuit, and the fourth inverting output end of the gate control circuit is respectively connected with the fourth inverting input end of the local product circuit and the fourth inverting input end of the carry circuit, the fifth inverse output end of the gate control circuit is connected with the fifth inverse input end of the local product circuit and the fifth inverse input end of the carry circuit, the sixth inverse output end of the gate control circuit is connected with the sixth inverse input end of the local product circuit and the sixth inverse input end of the carry circuit, the seventh inverse output end of the gate control circuit is connected with the seventh inverse input end of the carry circuit, the output end of the local product circuit is the local product output end of the multiple-valued adiabatic multiplier unit, the inverse output end of the local product circuit is the inverse local product output end of the multiple-valued adiabatic multiplier unit, the output end of the carry circuit is the high-order carry signal output end of the multiple-valued adiabatic multiplier unit, and the inverse output end of the carry circuit is the inverse high-order carry signal output end of the multiple-valued adiabatic multiplier unit, the input end of the clock control clock signal of the n-bit multi-valued adiabatic multiplier unit is connected with the output end of the inverted high-order carry signal of the nth multi-valued adiabatic multiplier unit, the connection end of the input end is the input end of the clock control clock signal of the multi-bit multi-valued adiabatic multiplier unit and is used for accessing the clock control clock signal, the first power clock signal input end of the n-bit multi-valued adiabatic multiplier unit is connected with the first clock control clock signal input end of the multi-bit multi-valued adiabatic multiplier unit, the connection end of the first power clock signal input end of the multi-valued adiabatic multiplier unit is used for accessing the first power clock signal, the second power clock signal input ends of all the even-numbered multi-valued adiabatic multiplier units in the n-bit multi-valued adiabatic multiplier unit are connected, the connection end of the second clock signal input end of the multi-bit multi-valued adiabatic multiplier unit is used for accessing the second power clock signal, and all the odd-numbered The input end of the second power clock signal is connected, the connection end of the second power clock signal is a third clock control clock signal input end of the multi-bit multivalued adiabatic multiplier and used for accessing a third power clock signal, the amplitude levels of the clock control clock signal and the first power clock signal are the same, the phase difference between the clock control clock signal and the first power clock signal is 180 degrees, the phases of the first power clock signal and the second power clock signal are the same, the amplitude level of the first power clock signal is 2 times of the amplitude level of the second power clock signal, the amplitude levels of the third power clock signal and the second power clock signal are the same, and the phase difference between the third power clock signal and the second power clock signal is 180 degrees; the high-order carry signal output end of the multivalued adiabatic multiplier unit at the kth position is connected with the low-order carry signal input end of the multivalued adiabatic multiplier unit at the (k + 1) th position, and k is 1, 2, …, n-1; the first input end of the multiple-valued adiabatic multiplier unit at the j position is used for accessing the j position signal of the first multiplier, the second input end of the multiple-valued adiabatic multiplier unit at the j position is used for accessing the j position signal of the second multiplier, and j is 1, 2, …, n.
2. A transmission gate structure based multi-bit multivalued adiabatic multiplier as claimed in claim 1, wherein said gate control circuit comprises three gate control units and nine binary inverters, said gate control units having an input terminal, a clocked clock signal input terminal, a power clock signal input terminal, a first output terminal, a second output terminal and a third output terminal, said three gate control units being a first gate control unit, a second gate control unit and a third gate control unit, said nine binary inverters being a first binary inverter, a second binary inverter, a third binary inverter, a fourth binary inverter, a fifth binary inverter, a sixth binary inverter, a seventh binary inverter, an eighth binary inverter and a ninth binary inverter, respectively; the first output of first gate control unit with the input of first binary phase inverter connect and its link do gate circuit's first output, first binary phase inverter's output do gate circuit's first reverse phase output, first gate control unit's second output with second binary phase inverter's input connect and its link do gate circuit's second output, second binary phase inverter's output do gate circuit's second reverse phase output, first gate control unit's third output with third binary phase inverter's input connect and its link do gate circuit's third output, third binary phase inverter's output do gate circuit's third reverse phase output, second gate control unit's first output with fourth binary phase inverter's input connect and its link do gate circuit's third output The output end of the second binary phase inverter is the fourth inverting output end of the gate control circuit, the second output end of the second gate control unit is connected with the input end of the fifth binary phase inverter, the connection end of the second gate control unit is the fifth output end of the gate control circuit, the output end of the fifth binary phase inverter is the fifth inverting output end of the gate control circuit, the third output end of the second gate control unit is connected with the input end of the sixth binary phase inverter, the connection end of the third gate control unit is the sixth output end of the gate control circuit, the output end of the sixth binary phase inverter is the sixth inverting output end of the gate control circuit, the first output end of the third gate control unit is connected with the input end of the seventh binary phase inverter, and the connection end of the first output end of the third gate control unit is the seventh output end of the gate control circuit, the output end of the seventh binary inverter is the seventh inverted output end of the gate control circuit, the second output end of the third gate control unit is connected with the input end of the eighth binary inverter, the connection end of the second binary inverter is the eighth output end of the gate control circuit, the output end of the eighth binary inverter is the eighth inverted output end of the gate control circuit, the third output end of the third gate control unit is connected with the input end of the ninth binary inverter, the connection end of the third binary inverter is the ninth output end of the gate control circuit, the output end of the ninth binary inverter is the ninth inverted output end of the gate control circuit, the clock signal input end of the first gate control unit, the clock signal input end of the second gate control unit and the clock signal input end of the third gate control unit are connected, and the connection end of the ninth binary inverter is the clock signal input end of the gate control circuit, the power clock signal input end of the first gating unit, the power clock signal input end of the second gating unit and the power clock signal input end of the third gating unit are connected, the connection end of the power clock signal input end of the third gating unit is the power clock signal input end of the gating circuit, the input end of the first gating unit is the first input end of the gating circuit, the input end of the second gating unit is the second input end of the gating circuit, and the input end of the third gating unit is the third input end of the gating circuit.
3. The multi-bit multivalued adiabatic multiplier based on the transmission gate structure of claim 2, wherein the first gate control unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a two-input and gate, the two-input and gate has a first input terminal, a second input terminal, and an output terminal, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the connection terminal thereof is the power clock signal input terminal of the first gate control unit, the source of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the connection terminal thereof is the clock signal input terminal of the first gate control unit; the gate of the first PMOS transistor, the gate of the first NMOS transistor, the gate of the third PMOS transistor and the gate of the third NMOS transistor are connected, and the connection end thereof is the input end of the first gate control unit, the drain of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the first NMOS transistor and the gate of the second NMOS transistor are connected, the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are all grounded, the drain of the third NMOS transistor, the gate of the fourth NMOS transistor, the drain of the third PMOS transistor and the gate of the fourth PMOS transistor are connected, the drain of the second PMOS transistor, the drain of the second NMOS transistor and the first input end of the second input and gate are connected, and the connection end thereof is the first output end of the first gate control unit, the drain electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the second input end of the two-input AND gate are connected, the connection end of the two-input AND gate is the third output end of the first gate control unit, and the output end of the two-input AND gate is the second output end of the first gate control unit; the circuit structures of the second gate control unit and the third gate control unit are the same as the circuit structure of the first gate control unit.
4. The multi-bit multi-valued adiabatic multiplier based on transmission gate structure of claim 3, wherein the threshold voltage of the first PMOS transistor is-0.6126V, the threshold voltage of the first NMOS transistor is-0.2457V, the threshold voltage of the third NMOS transistor is 0.243V, and the threshold voltage of the third PMOS transistor is 0.4891V.
5. The multi-bit multivalued adiabatic multiplier based on the transmission gate structure of any one of claims 1 to 4, wherein the product circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, and a twentieth NMOS transistor; a source of the fifth PMOS transistor, a source of the sixth PMOS transistor, a drain of the fifth NMOS transistor, a drain of the sixth NMOS transistor, a source of the tenth PMOS transistor, a source of the eleventh PMOS transistor, a drain of the tenth NMOS transistor and a drain of the eleventh NMOS transistor are connected and a connection end thereof is a second power clock signal input end of the product local circuit, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a drain of the seventh NMOS transistor, a drain of the eighth NMOS transistor, a source of the ninth PMOS transistor, a source of the sixteenth PMOS transistor, a drain of the ninth NMOS transistor, a source of the nineteenth PMOS transistor and a source of the twentieth PMOS transistor are connected and a connection end thereof is a first power clock signal input end of the product local circuit, the drain of the nineteenth NMOS transistor is connected to the drain of the twentieth NMOS transistor, and the connection end thereof is the clock signal input end of the local product circuit, the gate of the fifth NMOS transistor, the gate of the seventh PMOS transistor and the gate of the tenth NMOS transistor are connected, and the connection end thereof is the second input end of the local product circuit, the gate of the fifth PMOS transistor, the gate of the seventh NMOS transistor and the gate of the tenth PMOS transistor are connected, and the connection end thereof is the second inverting input end of the local product circuit, the gate of the sixth NMOS transistor, the gate of the eighth PMOS transistor and the gate of the eleventh NMOS transistor are connected, and the connection end thereof is the third input end of the local product circuit, the gate of the sixth PMOS transistor, the gate of the eighth NMOS transistor and the gate of the eleventh PMOS transistor are connected, and the connection end thereof is the third inverting input end of the local product circuit, a gate of the sixteenth NMOS transistor is a first input terminal of the local product circuit, a gate of the sixteenth PMOS transistor is a first inverting input terminal of the local product circuit, a gate of the ninth NMOS transistor is a fourth input terminal of the local product circuit, a gate of the ninth PMOS transistor is a fourth inverting input terminal of the local product circuit, a gate of the twelfth NMOS transistor, a gate of the fifteenth PMOS transistor and a gate of the seventeenth NMOS transistor are connected and a connection end thereof is a fifth inverting input terminal of the local product circuit, a gate of the twelfth PMOS transistor, a gate of the fifteenth NMOS transistor and a gate of the seventeenth PMOS transistor are connected and a connection end thereof is a fifth inverting input terminal of the local product circuit, a gate of the thirteenth NMOS transistor, a gate of the fourteenth PMOS transistor and a gate of the eighteenth NMOS transistor are connected and a connection end thereof is a sixth input terminal of the local product circuit, the gate of the thirteenth PMOS transistor, the gate of the fourteenth NMOS transistor and the gate of the eighteenth PMOS transistor are connected, and the connection end thereof is the sixth inverting input end of the local product circuit, the drain of the fifth PMOS transistor, the source of the fifth NMOS transistor, the source of the twelfth PMOS transistor and the drain of the twelfth NMOS transistor are connected, the drain of the sixth PMOS transistor, the source of the sixth NMOS transistor, the source of the thirteenth PMOS transistor and the drain of the thirteenth NMOS transistor are connected, the drain of the seventh PMOS transistor, the source of the seventh NMOS transistor, the source of the fourteenth PMOS transistor and the drain of the fourteenth NMOS transistor are connected, the drain of the eighth PMOS transistor, the source of the eighth NMOS transistor, the source of the fifteenth PMOS transistor and the drain of the fifteenth NMOS transistor are connected, the drain of the tenth PMOS transistor and the drain of the fourteenth NMOS are connected, The source electrode of the tenth NMOS transistor, the source electrode of the seventeenth PMOS transistor and the drain electrode of the seventeenth NMOS transistor are connected, the drain electrode of the eleventh PMOS transistor, the source electrode of the eleventh NMOS transistor, the source electrode of the eighteenth PMOS transistor and the drain electrode of the eighteenth NMOS transistor are connected, the drain electrode of the twelfth PMOS transistor, the source electrode of the twelfth NMOS transistor, the drain electrode of the thirteenth PMOS transistor, the source electrode of the thirteenth NMOS transistor, the drain electrode of the fourteenth PMOS transistor, the source electrode of the fourteenth NMOS transistor, the drain electrode of the fifteenth PMOS transistor, the source electrode of the fifteenth NMOS transistor, the drain electrode of the nineteenth PMOS transistor, the source electrode of the nineteenth NMOS transistor, the gate electrode of the twentieth PMOS transistor and the gate electrode of the twentieth NMOS transistor are connected, and the connection end thereof is the output end of the local product circuit, the drain electrode of the ninth PMOS transistor, the drain electrode of the seventeenth PMOS transistor and the drain electrode thereof are connected, The source electrode of the ninth NMOS transistor, the drain electrode of the sixteenth PMOS transistor, the source electrode of the sixteenth NMOS transistor, the drain electrode of the seventeenth PMOS transistor, the source electrode of the seventeenth NMOS transistor, the drain electrode of the eighteenth PMOS transistor, the source electrode of the eighteenth NMOS transistor, the drain electrode of the twentieth PMOS transistor, the source electrode of the twentieth NMOS transistor, the gate electrode of the nineteenth PMOS transistor and the gate electrode of the nineteenth NMOS transistor are connected, and the connecting end of the source electrode of the ninth NMOS transistor and the drain electrode of the eighteenth NMOS transistor is the inverted output end of the local product circuit.
6. The multi-bit multivalued adiabatic multiplier based on the transmission gate structure of claim 5, wherein the carry circuit comprises twenty-first PMOS transistor, twenty-second PMOS transistor, twenty-third PMOS transistor, twenty-fourth PMOS transistor, twenty-fifth PMOS transistor, twenty-sixth PMOS transistor, twenty-seventh PMOS transistor, twenty-eighth PMOS transistor, twenty-ninth PMOS transistor, thirty-fifth PMOS transistor, thirty-second PMOS transistor, thirty-third PMOS transistor, thirty-fourth PMOS transistor, thirty-fifth PMOS transistor, thirty-sixth PMOS transistor, twenty-first NMOS transistor, twenty-second NMOS transistor, twenty-third NMOS transistor, twenty-fourth NMOS transistor, twenty-fifth NMOS transistor, twenty-sixth NMOS transistor, twenty-seventh NMOS transistor, twenty-eighth NMOS transistor, twenty-ninth NMOS transistor, thirty-eleventh NMOS transistor, thirty-second NMOS transistor, thirty-third NMOS transistor, thirty-fourth NMOS transistor, A thirty-fifth NMOS transistor and a thirty-sixth NMOS transistor, where the source of the twenty-first PMOS transistor, the drain of the twenty-first NMOS transistor, the source of the twenty-second PMOS transistor, the drain of the twenty-second NMOS transistor, the source of the twenty-third PMOS transistor, the drain of the twenty-third NMOS transistor, the source of the twenty-fourth PMOS transistor, the drain of the twenty-fourth NMOS transistor, the source of the twenty-fifth PMOS transistor, the drain of the twenty-fifth NMOS transistor, the source of the twenty-ninth PMOS transistor, the drain of the twenty-ninth NMOS transistor, the source of the thirty-fifth PMOS transistor and the source of the thirty-sixth PMOS transistor are connected and their connection ends are the power clock signal input end of the carry circuit, the drain of the thirty-fifth NMOS transistor and the drain of the thirty-sixth NMOS transistor are connected and their connection ends are the clock signal input end of the carry circuit, the gate of the twenty-first NMOS transistor, the gate of the twenty-sixth NMOS transistor and the gate of the thirty-second NMOS transistor are connected and the connection end thereof is the third input end of the carry circuit, the gate of the twenty-first PMOS transistor, the gate of the twenty-sixth PMOS transistor and the gate of the thirty-second PMOS transistor are connected and the connection end thereof is the third inverting input end of the carry circuit, the gate of the twenty-second NMOS transistor and the gate of the twenty-third PMOS transistor are connected and the connection end thereof is the seventh input end of the carry circuit, the gate of the twenty-second PMOS transistor and the gate of the twenty-third NMOS transistor are connected and the connection end thereof is the seventh inverting input end of the carry circuit, the gate of the twenty-fourth NMOS transistor, the gate of the twenty-seventh NMOS transistor and the gate of the thirty-third NMOS transistor are connected and the connection end thereof is the second input end of the carry circuit, the gate of the twenty-fourth PMOS transistor, the gate of the twenty-seventh PMOS transistor and the gate of the thirty-third PMOS transistor are connected, and the connection end of the twenty-fifth NMOS transistor is the second inverting input end of the carry circuit, the gate of the twenty-fifth NMOS transistor is the first input end of the carry circuit, the gate of the twenty-fifth PMOS transistor is the first inverting input end of the carry circuit, the gate of the twenty-eighth NMOS transistor, the gate of the thirty-eleventh NMOS transistor and the gate of the thirty-fourth NMOS transistor are connected, and the connection end of the twenty-fourth PMOS transistor is the fifth input end of the carry circuit, the gate of the twenty-eighth PMOS transistor, the gate of the thirty-eleventh PMOS transistor and the gate of the thirty-fourth PMOS transistor are connected, and the connection end of the twenty-ninth NMOS transistor is the fifth inverting input end of the carry circuit, and the gate of the twenty-ninth NMOS transistor is the fourth input end of the carry circuit, the gate of the twenty-ninth PMOS transistor is the fourth inverting input terminal of the carry circuit, the gate of the thirty-first NMOS transistor is the sixth inverting input terminal of the carry circuit, the drain of the twenty-first PMOS transistor, the source of the twenty-first NMOS transistor, the source of the thirty-first PMOS transistor and the drain of the thirty-NMOS transistor are connected, the drain of the twenty-second PMOS transistor, the source of the twenty-second NMOS transistor, the source of the twenty-sixth PMOS transistor, the drain of the twenty-sixth NMOS transistor, the source of the twenty-seventh PMOS transistor and the drain of the twenty-seventh NMOS transistor are connected, the drain of the twenty-sixth PMOS transistor, the source of the twenty-sixth NMOS transistor, the drain of the thirty-eleventh NMOS transistor and the source of the thirty-eleventh PMOS transistor are connected, the drain of the twenty-seventh PMOS transistor, the source of the twenty-seventh NMOS transistor, the drain of the thirty-second NMOS transistor and the source of the thirty-second PMOS transistor are connected, the drain of the twenty-third PMOS transistor, the source of the twenty-third NMOS transistor, the source of the thirty-third PMOS transistor, the drain of the thirty-third NMOS transistor, the source of the twenty-eighth PMOS transistor and the drain of the twenty-eighth NMOS transistor are connected, the drain of the twenty-fourth PMOS transistor, the source of the twenty-fourth NMOS transistor, the source of the thirty-fourth PMOS transistor and the drain of the thirty-fourth NMOS transistor are connected, the drain of the thirty-PMOS transistor, the source of the thirty-NMOS transistor, the drain of the thirty-eleventh PMOS transistor, the source of the thirty-eleventh NMOS transistor, the thirty-second PMOS transistor, the source of the thirty-second NMOS transistor, the drain of the thirty-second PMOS transistor, the drain of the thirty-second NMOS transistor and the drain of the thirty-second PMOS transistor are connected, The drain electrode of the thirty-fifth PMOS tube, the source electrode of the thirty-fifth NMOS tube, the grid electrode of the thirty-sixth PMOS tube and the grid electrode of the thirty-sixth NMOS tube are connected, and the connection end of the drain electrode of the thirty-fifth PMOS tube and the grid electrode of the thirty-sixth NMOS tube is the output end of the carry circuit, the drain electrode of the twenty-fifth PMOS transistor, the source electrode of the twenty-fifth NMOS transistor, the drain electrode of the twenty-eighth PMOS transistor, the source electrode of the twenty-eighth NMOS transistor, the drain electrode of the twenty-ninth PMOS transistor, the source electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-third PMOS transistor, the source electrode of the thirty-third NMOS transistor, the drain electrode of the thirty-fourth PMOS transistor, the source electrode of the thirty-fourth NMOS transistor, the drain electrode of the thirty-sixth PMOS transistor, the source electrode of the thirty-sixth NMOS transistor, the gate electrode of the thirty-fifth PMOS transistor, and the gate electrode of the thirty-fifth NMOS transistor are connected, and the connection end thereof is the inverted output end of the carry circuit.
7. The multi-bit multivalued adiabatic multiplier based on the transmission gate structure as claimed in claim 3 or 4, wherein the two-input AND gate comprises a thirty-seventh PMOS transistor, a thirty-eighth PMOS transistor, a thirty-ninth PMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor and a thirty-ninth NMOS transistor, the source of the thirty-seventh PMOS transistor, the source of the thirty-eighth PMOS transistor and the source of the thirty-ninth PMOS transistor are all connected to a power supply, the gate of the thirty-seventh PMOS transistor is connected to the gate of the thirty-seventh NMOS transistor and the connection end thereof is the first input end of the two-input AND gate, the gate of the thirty-eighth PMOS transistor is connected to the gate of the thirty-eighth NMOS transistor and the connection end thereof is the second input end of the two-input AND gate, the drain of the thirty-seventh PMOS transistor, the drain of the thirty-seventh NMOS transistor, the drain of the thirty-ninth PMOS transistor, the thirty-ninth NMOS transistor and the thirty, The drain of the thirty-eighth PMOS transistor, the gate of the thirty-ninth PMOS transistor and the gate of the thirty-ninth NMOS transistor are connected, the source of the thirty-seventh NMOS transistor and the drain of the thirty-eighth NMOS transistor are connected, the drain of the thirty-ninth PMOS transistor and the drain of the thirty-ninth NMOS transistor are connected, the connection end of the drain of the thirty-ninth PMOS transistor and the drain of the thirty-ninth NMOS transistor is the output end of the two-input and gate, and the source of the thirty-eighth NMOS transistor and the source of the thirty-ninth NMOS transistor are respectively grounded.
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