CN101303641A - Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL - Google Patents
Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL Download PDFInfo
- Publication number
- CN101303641A CN101303641A CNA2008100625411A CN200810062541A CN101303641A CN 101303641 A CN101303641 A CN 101303641A CN A2008100625411 A CNA2008100625411 A CN A2008100625411A CN 200810062541 A CN200810062541 A CN 200810062541A CN 101303641 A CN101303641 A CN 101303641A
- Authority
- CN
- China
- Prior art keywords
- circuit
- ctgal
- adiabatic
- carry signal
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Compressors, Vaccum Pumps And Other Relevant Systems (AREA)
- Complex Calculations (AREA)
Abstract
The invention discloses an adiabatic 4-2 compressor based on CTGAL and a 4*4 multiplier formed by using the adiabatic 4-2 compressor. A carry signal input end Cin of a high adiabatic 4-2 compressor neighboring the standard adiabatic 4-2 compressor is accessed into a high carry signal output end Cout of the standard adiabatic 4-2 compressor; as a two-phase non-overlapping power clock is adopted by the CTGAL, the operation of an adiabatic 4-2 compressing unit circuit is divided into three grades; therefore, the standard Cout and the neighboring high Cin have the same phase position relation and correct logic calculation can be achieved; besides, compared with the traditional 4-2 compressor based on CMOS under the same situation of using an adiabatic circuit to realize, as a selector and an exclusive or gate of the invention have the same circuit structure, the timelag, the links and the area of the circuit are all relatively reduced; the energy consumption can be saved by 90 percent; as the adiabatic circuit has extremely low power consumption, the multiplier of the invention can realize a relatively lower power consumption.
Description
Technical field
The present invention relates to a kind of mlultiplying circuit, especially relate to a kind of adiabatic 4-2 compressor reducer and 4 * 4 multipliers based on CTGAL.
Background technology
In the VLSI (very large scale integrated circuit) of existing deep submicron process, one of target of overriding concern when low-power consumption has become chip design.Low-power Technology research has become field more and more important in the integrated circuit (IC) design.Multiplying is the most basic arithmetical operation, multiplier is the critical component of Modern microprocessor, in a lot of fields, all playing the part of important role, and to a great extent the power consumption of system, for example the multiplier accumulator unit institute power consumed that mainly is made of multiplier accounts for 50% of whole dsp chip power consumption usually.Therefore, the research low-consumption multiplier has great importance.Because the traditional cmos integrated circuit adopts DC power supply, its energy loss mainly is when node capacitor is discharged and recharged, and electric energy does not cause to the irreversible and energy of heat energy recyclable.And the adiabatic cmos circuit adopts the alternating-current pulse power supply to come driving circuit, utilize inductance and the node capacitor in the circuit in the power supply to form the LC oscillation circuit, make energy transform mutually with the form of magnetic energy and electric energy, thereby realize the recycling of energy, and reduce or avoid being converted to energy loss in this irreversible process of heat energy by electric energy because of what dissipative cell-resistance caused with this.
Clock transmission gate adiabatic logic (the clocked transmission gate adiabatic logic of our invention, CTGAL) basic circuit as shown in Figure 1, it is a kind of adiabatic circuits with extremely low power dissipation that adopts two-phase not have the overlapping power clock, the operation of CTGAL is divided into 2 grades, and the first order is managed (N by 2 clock NMOS under the control of clock clock Φ
1, N
2) (in) samples to input signal; The second level is by the NMOS pipe (N of bootstrapping operation
3, N
4) and the P that forms the CMOS-latch structure
1, N
5, P
2, N
6To load charge-discharge, make output waveform complete, greatly reduced the power consumption of circuit.NMOS pipe (the N that replaces the bootstrapping operation of CTGAL basic circuit among Fig. 1 with the NMOS logical block of complementation
3, N
4), can obtain selecting 1 data selector with door, CTGAL or door and CTGAL two as Fig. 2, Fig. 3 and CTGAL shown in Figure 4.
Summary of the invention
Technical matters to be solved by this invention provides a kind of adiabatic 4-2 compressor reducer and 4 * 4 mlultiplying circuits based on CTGAL, adiabatic circuits is applied in the multiplying, realize adiabatic 4-2 compressor reducer of low-power consumption and multiplier, and have correct logic functions and energy recovery characteristics.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of adiabatic 4-2 compressor reducer based on CTGAL, form by at least two 4-2 compression unit serial connections, described 4-2 compression unit comprises that high-order carry signal produces circuit, the next stage carry signal produces circuit and summing signal produces circuit, described high-order carry signal produces circuit and is made up of two CTGAL OR circuit and a CTGAL AND circuit, described next stage carry signal produces circuit by two CTGAL AND circuit, a CTGAL OR circuit and a CTGAL alternative selector switch are formed, described summing signal produces circuit and is made up of four CTGAL NOR gate circuits, the output terminal that described summing signal produces second level CTGAL NOR gate circuit in the circuit is connected with the selection input end of described CTGAL alternative selector switch, the high-order carry signal output terminal that the described high-order carry signal of the described 4-2 compression unit of adjacent low level produces circuit is connected with the low level carry signal input end of the described 4-2 compression unit of an adjacent high position, and described low level carry signal input end is connected to described summing signal and produces an input end of afterbody CTGAL XOR gate in the circuit and the input end that described next stage carry signal produces the CTGAL alternative selector switch in the circuit.
Use 4 * 4 mlultiplying circuits of above-mentioned adiabatic 4-2 compressor reducer, it comprises an adiabatic summation and array, an adiabatic 4-2 compressor reducer and an adiabatic Parallel Prefix Adder, described adiabatic summation comprises 16 independently CTGAL AND circuit with array, described adiabatic 4-2 compressor reducer is formed by four 4-2 compression unit serial connections, described adiabatic Parallel Prefix Adder is 8 Ladner-Fischer totalizers based on CTGAL, described 4-2 compression unit comprises that high-order carry signal produces circuit, the next stage carry signal produces circuit and summing signal produces circuit, described high-order carry signal produces circuit and is made up of two CTGAL OR circuit and a CTGAL AND circuit, described next stage carry signal produces circuit by two CTGAL AND circuit, a CTGAL OR circuit and a CTGAL alternative selector switch are formed, described summing signal produces circuit and is made up of four CTGAL NOR gate circuits, the output terminal that described summing signal produces second level CTGAL NOR gate circuit in the circuit is connected with the selection input end of described CTGAL alternative selector switch, the high-order carry signal output terminal that the described high-order carry signal of the described 4-2 compression unit of adjacent low level produces circuit is connected with the low level carry signal input end of the described 4-2 compression unit of an adjacent high position, and described low level carry signal input end is connected to described summing signal and produces an input end of afterbody CTGAL XOR gate in the circuit and the input end that described next stage carry signal produces the CTGAL alternative selector switch in the circuit.
Compared with prior art, the invention has the advantages that the carry signal output terminal Cout with the high position of the adiabatic 4-2 compressor reducer at one's own department or unit inserts the carry signal input end Cin of adjacent high-order adiabatic 4-2 compressor reducer, to postponing did not influence, because high-order Cin is when being used, the Cout at one's own department or unit just forms, and the CTGAL circuit adopts two-phase not have the overlapping power clock, adiabatic 4-2 compression unit circuit operation divides three grades, so the Cout at one's own department or unit and the Cin of an adjacent high position have identical phase relation, realize correct logical operation.Compare with traditional 4-2 compressor reducer based on CMOS, because selector switch of the present invention has identical circuit structure with XOR gate, thus the time-delay of its circuit, all relative minimizing of line with area.
Multiplier commonly used generally is made up of partial product generative circuit and partial product summing circuit, partial product generative circuit of the present invention is realized that by CTGAL and gate array partial product summing circuit of the present invention is realized by adiabatic 4-2 compressor reducer and Ladner-Fischer totalizer.When the partial product number greater than four the time, adiabatic 4-2 compressor reducer adopts the Wallace tree to link to each other, as Fig. 9 and shown in Figure 10, different with the serial addition array, the Wallace tree is not direct with all partial products addition successively, but adopts the structure that is tending towards walking abreast that partial product is carried out sum operation, to reduce because carry is transmitted the time delay that causes as far as possible, thereby improve the arithmetic speed of the long-pending adder array of entire portion, improve the summation speed of partial product; To the final output of Wallace tree with signal and carry signal, need sue for peace to them with the Ladner-Fischer totalizer, the present invention is owing to have only 4 partial products, so only need an adiabatic 4-2 compression unit and a Ladner-Fischer totalizer just can realize.Simultaneously, because adiabatic circuits has extremely low power consumption, adiabatic circuits is applied in the traditional cmos mlultiplying circuit can realize low-consumption multiplier.
Adopt TSMC 0.25 μ m CMOS technology device parameters, above-mentioned adiabatic 4-2 compressor reducer and 4 * 4 adiabatic multipliers are carried out functional simulation.Figure 13 and Figure 14 provided respectively based on the analog waveform of the adiabatic 4-2 compressor reducer of CTGAL and with based on the 4-2 compressor reducer transient state energy consumption of CMOS relatively, analog result shows that the adiabatic 4-2 compressor reducer based on CTGAL has correct logic functions, and compare with 4-2 compressor reducer, save energy consumption about 90% based on CMOS.
Figure 15 is that multiplicand and multiplier are respectively A=1010, the analog result of 4 * 4 adiabatic multipliers of B=1110, S among the figure
7S
0Be A, the product of B has correct logic functions by visible 4 * 4 the adiabatic multipliers of A * B=10001100.Figure 16 is the transient state energy consumption figure of 4 * 4 adiabatic multipliers, the rising part of transient state energy consumption curve represents that power supply injects energy to circuit, sloping portion shows that power supply recovers energy from circuit, and edging up of concave bottom reflected the energy consumption of circuit, and visible circuit has tangible energy and recovers and the low-power consumption characteristic.
The CTGAL circuit discharges and recharges node capacitance with full adiabatic method, has extremely low power consumption, and She Ji adiabatic multiplier has tangible energy recovery characteristics on this basis.
Description of drawings
Fig. 1 is the schematic configuration diagram and the expression symbol of CTGAL basic circuit;
Fig. 2 is the structural representation and the expression symbol of CTGAL and door;
Fig. 3 is the structural representation and the expression symbol of CTGAL or door;
Fig. 4 selects the structural representation and the expression symbol of 1 data selector for CTGAL 2;
Fig. 5 is the structural representation that the present invention is based on the adiabatic 4-2 compression unit of CTGAL;
Fig. 6 is the structural representation that the present invention is based on the adiabatic 4-2 compressor reducer of CTGAL;
Fig. 7 is the principle schematic of 4 * 4 adiabatic multipliers of the present invention;
Fig. 8 is 4 * 4 adiabatic multiplier architecture synoptic diagram of the present invention;
Fig. 9 is adiabatic serial addition array structure synoptic diagram;
Figure 10 is the adiabatic Wallace tree structure of the present invention synoptic diagram;
Figure 11 is " 0 " computing structural representation;
Figure 12 is a Lardner-Fischer adder structure synoptic diagram;
Figure 13 is the adiabatic 4-2 compressor reducer functional simulation waveform based on CTGAL;
Figure 14 be based on the adiabatic 4-2 compressor reducer of CTGAL with based on the 4-2 compressor reducer transient state energy consumption of CMOS relatively;
Figure 15 is that multiplicand and multiplier are respectively A=1010, the analog result of 4 * 4 adiabatic multipliers of B=1110;
Figure 16 is the transient state energy consumption figure of 4 * 4 adiabatic multipliers.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
Embodiment one: as shown in Figure 5 and Figure 6, a kind of adiabatic 4-2 compressor reducer based on CTGAL, form by four 4-2 compression units, 1 serial connection, the 4-2 compression unit comprises that high-order carry signal produces circuit 11, the next stage carry signal produces circuit 12 and summing signal produces circuit 13, high-order carry signal produces circuit 11 and is made up of two CTGAL OR circuit and a CTGAL AND circuit, the next stage carry signal produces circuit 12 by two CTGAL AND circuit, a CTGAL OR circuit and a CTGAL alternative selector switch are formed, summing signal produces circuit 13 and is made up of four CTGAL NOR gate circuits, the output terminal that summing signal produces second level CTGAL NOR gate circuit in the circuit 13 is connected with the selection input end of CTGAL alternative selector switch, the high-order carry signal output terminal Cout that the high-order carry signal of the 4-2 compression unit 1 of adjacent low level produces circuit 11 is connected with the low level carry signal input end Cin of the 4-2 compression unit 1 of an adjacent high position, and low level carry signal input end Cin is connected to an input end of afterbody CTGAL XOR gate in the summing signal generation circuit 13 and an input end of the CTGAL alternative selector switch in the next stage carry signal generation circuit 12.
According to the number of partial product and mutual displacement, the Cin of the adiabatic 4-2 compression unit of corresponding number linked to each other successively with Cout just can obtain adiabatic 4-2 compressor reducer shown in Figure 6, and it has realized to four n positions and displacement being 1 partial product P
0[0 ... n-1], P
1[0 ... n-1], P
2[0 ... n-1], P
3[0 ... n-1] operation of suing for peace.Should be when partial product is sued for peace earlier with the partial product displacement, so that have several additions of equal weight, remaining input termination 0.
Embodiment two: as shown in Figure 7 and Figure 8, use 4 * 4 multipliers of the adiabatic 4-2 compressor reducer identical with embodiment one, it comprises an adiabatic summation and array 10, an adiabatic 4-2 compressor reducer 20 and an adiabatic Parallel Prefix Adder 30, adiabatic summation comprises 16 independently CTGAL AND circuit with array 10, and adiabatic Parallel Prefix Adder 30 is 8 Ladner-Fischer totalizers based on CTGAL.
Progression time delay of whole array can be tapered to 0 ((log by 0 (n/2*d) of serial addition array based on the Wallace of adiabatic 4-2 compressor reducer tree
2N) * d), wherein, n is the number of partial product, and d is the time delay of a 4-2 compressor reducer.By Fig. 8, Fig. 9 as seen, when partial product has 16, be the time delay of seven grades of adiabatic 4-2 compressor reducers and one-level Parallel Prefix Adder the time delay of serial addition permutation, and be the time delay of three grades of adiabatic 4-2 compressor reducers and an one-level Parallel Prefix Adder time delay of Wallace tree.
Adopt time delay than summing signal and the carry signal addition of short Ladner-Fischer totalizer to the final output of Wallace tree, the Ladner-Fischer totalizer is made up of a series of " 0 " computing, and the calculating process of " 0 " computing as shown in figure 11.Figure 12 is the structural drawing of 8 Ladner-Fischer totalizers, and be (log its time delay
2M) * l, wherein m is the figure place (getting bigger) of addend or summand, l is the time delay of " a 0 " computing.Also need quote following formula for realizing the complete additive operation of Ladner-Fischer totalizer:
g
i＝a
i·b
i，
(1)
s
0＝p
0，
s
n＝c
n-1，i＝1，2，…，n-1(2)
When carrying out additive operation, two number a that earlier will be to be sued for peace
i, b
i(i=0,1 ..., n-1) calculate signal g by formula (1)
i, p
i, g
i, p
iBe the input signal of Ladner-Fischer totalizer, after the computing of Ladner-Fischer totalizer, again with output signal c
iAnd p
iCan obtain two count and s by formula (2) calculating
i(i=0,1 ..., n).
Claims (2)
1, a kind of adiabatic 4-2 compressor reducer based on CTGAL, form by at least two 4-2 compression unit serial connections, it is characterized in that described 4-2 compression unit comprises that high-order carry signal produces circuit, the next stage carry signal produces circuit and summing signal produces circuit, described high-order carry signal produces circuit and is made up of two CTGAL OR circuit and a CTGAL AND circuit, described next stage carry signal produces circuit by two CTGAL AND circuit, a CTGAL OR circuit and a CTGAL alternative selector switch are formed, described summing signal produces circuit and is made up of four CTGAL NOR gate circuits, the output terminal that described summing signal produces second level CTGAL NOR gate circuit in the circuit is connected with the selection input end of described CTGAL alternative selector switch, the high-order carry signal output terminal that the described high-order carry signal of the described 4-2 compression unit of adjacent low level produces circuit is connected with the low level carry signal input end of the described 4-2 compression unit of an adjacent high position, and described low level carry signal input end is connected to described summing signal and produces an input end of afterbody CTGAL XOR gate in the circuit and the input end that described next stage carry signal produces the CTGAL alternative selector switch in the circuit.
2, use 4 * 4 multipliers of the described adiabatic 4-2 compressor reducer of claim 1, it is characterized in that it comprises adiabatic summation of a level Four and array, an adiabatic 4-2 compressor reducer and an adiabatic Parallel Prefix Adder, described adiabatic Parallel Prefix Adder is 8 adiabatic Ladner-Fischer totalizers, described adiabatic summation comprises 16 independently CTGAL AND circuit with array, described adiabatic 4-2 compressor reducer is formed by four 4-2 compression unit serial connections, described 4-2 compression unit comprises that high-order carry signal produces circuit, the next stage carry signal produces circuit and summing signal produces circuit, described high-order carry signal produces circuit and is made up of two CTGAL OR circuit and a CTGAL AND circuit, described next stage carry signal produces circuit by two CTGAL AND circuit, a CTGAL OR circuit and a CTGAL alternative selector switch are formed, described summing signal produces circuit and is made up of four CTGAL NOR gate circuits, the output terminal that described summing signal produces second level CTGAL NOR gate circuit in the circuit is connected with the selection input end of described CTGAL alternative selector switch, the high-order carry signal output terminal that the described high-order carry signal of the described 4-2 compression unit of adjacent low level produces circuit is connected with the low level carry signal input end of the described 4-2 compression unit of an adjacent high position, and described low level carry signal input end is connected to described summing signal and produces an input end of afterbody CTGAL XOR gate in the circuit and the input end that described next stage carry signal produces the CTGAL alternative selector switch in the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810062541A CN100580620C (en) | 2008-06-19 | 2008-06-19 | Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810062541A CN100580620C (en) | 2008-06-19 | 2008-06-19 | Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101303641A true CN101303641A (en) | 2008-11-12 |
| CN100580620C CN100580620C (en) | 2010-01-13 |
Family
ID=40113559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810062541A Expired - Fee Related CN100580620C (en) | 2008-06-19 | 2008-06-19 | Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100580620C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634750A (en) * | 2017-08-03 | 2018-01-26 | 宁波大学 | A kind of multidigit multivalue thermal insulation multiplier of passgate structures |
| CN109542393A (en) * | 2018-11-19 | 2019-03-29 | 电子科技大学 | A kind of approximation 4-2 compressor and approximate multiplier |
| CN110190843A (en) * | 2018-04-10 | 2019-08-30 | 北京中科寒武纪科技有限公司 | Compressor circuit, Wallace tree circuit, multiplier circuit, chip and equipment |
-
2008
- 2008-06-19 CN CN200810062541A patent/CN100580620C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634750A (en) * | 2017-08-03 | 2018-01-26 | 宁波大学 | A kind of multidigit multivalue thermal insulation multiplier of passgate structures |
| CN107634750B (en) * | 2017-08-03 | 2020-06-16 | 宁波大学 | Multi-bit multi-valued adiabatic multiplier with transmission gate structure |
| CN110190843A (en) * | 2018-04-10 | 2019-08-30 | 北京中科寒武纪科技有限公司 | Compressor circuit, Wallace tree circuit, multiplier circuit, chip and equipment |
| CN110190843B (en) * | 2018-04-10 | 2020-03-10 | 中科寒武纪科技股份有限公司 | Compressor circuit, Wallace tree circuit, multiplier circuit, chip and apparatus |
| CN109542393A (en) * | 2018-11-19 | 2019-03-29 | 电子科技大学 | A kind of approximation 4-2 compressor and approximate multiplier |
| CN109542393B (en) * | 2018-11-19 | 2022-11-04 | 电子科技大学 | Approximate 4-2 compressor and approximate multiplier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100580620C (en) | 2010-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103176767B (en) | The implementation method of the floating number multiply-accumulate unit that a kind of low-power consumption height is handled up | |
| Singh et al. | Performance analysis of 32-bit array multiplier with a carry save adder and with a carry-look-ahead adder | |
| CN103092560B (en) | A kind of low-consumption multiplier based on Bypass technology | |
| CN103227635A (en) | High-speed and low-power-consumption CMOS full adder and operation method thereof | |
| CN100580620C (en) | Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL | |
| CN106444345B (en) | Time measuring circuit, method and measuring device | |
| CN100465877C (en) | High speed split multiply accumulator apparatus | |
| Matsunaga et al. | Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs | |
| CN107092462B (en) | 64-bit asynchronous multiplier based on FPGA | |
| Sasipriya et al. | Design of low power VLSI circuits using two phase adiabatic dynamic logic (2PADL) | |
| CN101866278B (en) | Asynchronous iteration 64-bit integer multiplier and computing method thereof | |
| US7603398B2 (en) | Data converter and a delay threshold comparator | |
| Tiwari et al. | Fpga design and implementation of matrix multiplication architecture by ppi-mo techniques | |
| CN202218216U (en) | Low-power-consumption asynchronous comparison gate for low density parity check (LDPC) decoder | |
| Malekpour et al. | A comparative study of energy/power consumption in parallel decimal multipliers | |
| Sharma | Disposition (reduction) of (negative) partial product for radix 4 Booth's algorithm | |
| Rajalakshmi et al. | Performance Analysis of Energy Efficient MAC Unit for Digital Applications | |
| CN103324461A (en) | Four-addend binary parallel synchronous adder | |
| CN201177811Y (en) | Data processing system and constituted ASIC chip thereby | |
| Kashfi et al. | Designing an ultra-high-speed multiply-accumulate structure | |
| CN102832928A (en) | Three-value adiabatic domino addition unit | |
| CN101087128B (en) | Heat isolation access locket and heat isolation CMOS time sequence circuit of no heat isolation gate | |
| Singh et al. | Modified booth multiplier with carry select adder using 3-stage pipelining technique | |
| CN102902508B (en) | Ternary adiabatic domino multiplication unit | |
| Kharwar et al. | Design & Comparison of 32-bit CSLA with Hybrid Logic |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100113 Termination date: 20140619 |
|
| EXPY | Termination of patent right or utility model |