CN109860135B - 混合互连器件和方法 - Google Patents

混合互连器件和方法 Download PDF

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Publication number
CN109860135B
CN109860135B CN201810459800.8A CN201810459800A CN109860135B CN 109860135 B CN109860135 B CN 109860135B CN 201810459800 A CN201810459800 A CN 201810459800A CN 109860135 B CN109860135 B CN 109860135B
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dielectric layer
waveguide
conductive
interconnect
substrate
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CN109860135A (zh
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余振华
王垂堂
夏兴国
廖佑广
张智杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/124—Geodesic lenses or integrated gratings
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12002—Three-dimensional structures
    • G—PHYSICS
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    • G02B6/12004—Combinations of two or more optical elements
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    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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Abstract

在实施例中，方法包括：形成包括设置在多个介电层中的波导和导电部件的互连件，导电部件包括导线和通孔，波导由具有第一折射率的第一材料形成，介电层由具有小于第一折射率的第二折射率的第二材料形成；将多个管芯接合至互连件的第一侧，管芯通过导电部件电连接，管芯通过波导光连接；以及在互连件的第二侧上形成多个导电连接件，导电连接件通过导电部件电连接至管芯。本发明的实施例还涉及混合互连器件和方法。

Description

混合互连器件和方法
技术领域
本发明的实施例涉及混合互连器件和方法。
背景技术
电信号传导和处理是信号传输和处理的一种技术。近年来，光信号传导和处理已经用于越来越多的应用中，特别是使用与光纤相关的应用来传输信号。
光信号传导和处理通常与电信号传导和处理结合，以提供全面的应用。例如，光纤可以用于远程信号传输，并且电信号可以用于短程信号传输以及处理和控制。因此，为了光信号和电信号之间的转换以及光信号和电信号的处理，形成集成光学组件和电子组件的器件。因此，封装件可以包括光学(光子)管芯(包括光学器件)和电子管芯(包括电子器件)。
发明内容
本发明的实施例提供了一种互连件，包括：第一介电层，包括具有第一折射率的第一材料，所述第一介电层具有第一表面和与所述第一表面相对的第二表面；波导，位于所述第一介电层中，所述波导具有由所述波导中的凹槽限定的光栅耦合器，所述波导包括具有大于所述第一折射率的第二折射率的第二材料；多个第二介电层，位于所述第一介电层的第一表面上，所述第二介电层的每个均包括所述第一材料；多个导电部件，位于所述第二介电层中，所述导电部件包括导线和第一通孔，从所述光栅耦合器延伸至所述第二介电层的顶面的光传输路径没有所述导电部件；多个第二通孔，延伸穿过所述第一介电层；以及多个导电连接件，位于所述第一介电层的第二表面上，所述第二通孔将所述导电连接件电连接至所述导电部件。
本发明的另一实施例提供了一种形成互连器件的方法，包括：图案化衬底的部分以形成波导，所述衬底具有第一表面和与所述第一表面相对的第二表面；在所述波导和所述衬底的所述第一表面上沉积第一介电层；形成延伸穿过所述第一介电层的通孔；在所述第一介电层上沉积多个第二介电层；在所述第二介电层中形成多个导电部件，所述第二介电层的第一区域没有所述导电部件；将多个管芯附接至所述第二介电层，所述管芯电连接至所述导电部件，所述管芯通过所述第二介电层的所述第一区域光连接至所述波导；减薄所述衬底的所述第二表面以暴露所述通孔；以及形成电连接至所述通孔的导电连接件。
本发明的又一实施例提供了一种形成互连器件的方法，包括：形成互连件，所述互连件包括设置在多个介电层中的波导和导电部件，所述导电部件包括导线和通孔，所述波导由具有第一折射率的第一材料形成，所述介电层由具有小于所述第一折射率的第二折射率的第二材料形成；将多个管芯接合至所述互连件的第一侧，所述管芯通过所述导电部件电连接，所述管芯通过所述波导光连接；以及在所述互连件的第二侧上形成多个导电连接件，所述导电连接件通过所述导电部件电连接至所述管芯。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A和图1B示出了根据一些实施例的多芯片系统。
图2A至图12B示出了根据一些实施例的在用于形成多芯片系统的工艺期间的中间步骤的各个视图。
图13是根据一些实施例的操作期间产生的多芯片系统的截面图。
图14A至图24B是根据一些其它实施例的在用于形成多芯片系统的工艺期间的中间步骤的各个视图。
图25是根据一些其它实施例的操作期间产生的多芯片系统的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，提供了包括光学器件和电子器件的三维(3D)封装件及其形成方法。具体地，形成具有用于传输电信号的导电部件和用于传输光信号的波导的混合互连件。将用于形成不同计算位点的管芯附接至混合互连件。不同位点通过混合互连件光和电连接。根据一些实施例，示出了形成封装件的中间阶段。讨论可一些实施例的一些变型。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1A和图1B示出了根据一些实施例的多芯片系统100。多芯片系统100是例如高性能计算(HPC)系统，并且包括多个位点102，每个位点均是独立的计算系统。图1A示出了所有位点102，并且图1B是示出四个位点102A至102D的区域100A的详细视图。
位点102通过光路径104互连，这允许独立的计算系统通信。具体地，光路径104是连接至多芯片系统100的每个位点102的闭环(或环)。因此，每个位点102均可以经由光路径104与任何其它位点102通信。在实施例中，光路径104包括多个波导，并且每个波导均以点对点方式连接两个位点102。在一些实施例中，光路径104是硅光子互连件，但是可以使用其它类型的光路径。每个位点102均包括处理器管芯106、存储器管芯108、电子管芯110和光子管芯112。光路径104在每个位点102的一个或多个组件下方延伸，而且至少在每个位点102的光子管芯112下方延伸。位点102通过电路径(未在图1A和图1B中示出，但在下面描述)互连。
处理器管芯106可以是中央处理单元(CPU)、图形处理单元(GPU)、专用集成电路(ASIC)等。存储器管芯108可以是诸如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)等的易失性存储器。在所示的实施例中，每个位点均包括一个处理器管芯106和四个存储器管芯108，但是应该理解，每个位点102均可以包括更多或更少的存储器管芯108。
光子管芯112传输和接收光信号。具体地，光子管芯112将来自处理器管芯106的电信号转换成光信号，并且将来自光路径104的光信号转换成电信号。因此，光子管芯112负责至/来自光路径104的光信号的输入/输出(I/O)。光子管芯112可以是光子集成电路(PIC)。光子管芯112光耦合至光路径104并且通过光学I/O端口118(下面在图8A和图8B中示出)电连接至电子管芯110。电子管芯110包括将处理器管芯106与光子管芯112接口所需的电子电路。例如，电子管芯110可以包括控制器、互阻抗放大器等。电子管芯110根据从处理器管芯106接收的电信号(数字或模拟)来控制光子管芯112的高频信号传导。电子管芯110可以是电子集成电路(EIC)。
激光源114经由光路径104向每个位点102提供载波信号。激光源114可以是一个位点102的一部分，或可以位于位点102的外部，并且通过边缘或光栅耦合光耦合至光路径104。激光源114可以沿着光路径104的一个波导传输载波信号，从而使得载波信号由每个位点102的光子管芯112接收。光子管芯112根据来自处理器管芯106的电信号调制载波信号来产生光信号。
虽然处理器管芯106、存储器管芯108和电子管芯110示出为单独的管芯，但是应该理解，位点102可以是片上系统(SoC)或集成电路上系统(SoIC)器件。在这种实施例中，处理器、存储器和/或电子控制功能可以集成在同一管芯上。
图2A至图12B是根据一些实施例的在用于形成多芯片系统100的工艺期间的中间阶段的各个视图。图2A至图12B是截面图，其中，沿着图1B的截面A-A(例如，沿着处理器管芯106和存储器管芯108)示出以字符“A”结尾的图，并且沿着图1B的截面B-B(例如，沿着存储器管芯108、光子管芯112和电子管芯110)示出以字符“B”结尾的图。
在图2A和图2B中，提供衬底202。衬底202可以是可以掺杂(例如，掺杂有p型或n型掺杂剂)或未掺杂的半导体衬底，诸如块状半导体等。衬底202可以是诸如硅晶圆的晶圆。但是也可以使用诸如多层或梯度衬底的其它衬底。在一些实施例中，衬底202的半导体材料可以包括硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。在实施例中，衬底202是例如12英寸硅晶圆的硅晶圆。该衬底可以具有前侧或正面(例如，图2A和图2B中面向上的侧)以及背侧或背面(例如，图2A和图2B中面向下的侧)。衬底202具有多个区域，包括将形成位点102A的第一区域和将形成位点102B的第二区域。
在图3A和图3B中，图案化衬底202的前侧以形成波导204。波导204形成连接多芯片系统100的所有位点102的连续环。可以用可接受的光刻和蚀刻技术完成衬底202的图案化。例如，可以在衬底202的前侧上形成并且显影光刻胶。光刻胶可以被图案化为具有对应于波导204的开口。可以使用图案化的光刻胶作为蚀刻掩模来实施一个或多个蚀刻工艺。具体地，可以蚀刻衬底202的前侧以形成限定波导204的凹槽；衬底202的剩余的未凹进部分形成波导204，其中，剩余的未凹进部分的侧壁限定波导204的侧壁。蚀刻工艺可以是各向异性湿蚀刻或干蚀刻。应该理解，波导204的尺寸取决于应用；在实施例中，波导204具有从约500nm至约3000nm(诸如约500nm)的宽度，以及从约220nm至约300nm(诸如约250nm)的高度。
波导204包括形成在波导204的顶部中的光栅耦合器206。光栅耦合器206允许波导204将光传输至上面的光源或光信号源(例如，光子管芯112)或从上面的光源或光信号源接收光。可以通过可接受的光刻和蚀刻技术形成光栅耦合器206。在实施例中，在限定波导204之后形成光栅耦合器206。例如，可以在衬底202的前侧上(例如，在波导204上以及在限定它们的凹槽中)形成并且显影光刻胶。光刻胶可以被图案化为具有对应于光栅耦合器206的开口。可以使用图案化的光刻胶作为蚀刻掩模来实施一个或多个蚀刻工艺。具体地，可以蚀刻衬底202的前侧以在波导204中形成限定光栅耦合器206的凹槽。蚀刻工艺可以是各向异性湿蚀刻或干蚀刻。
在图4A和图4B中，在衬底202的前侧上形成介电层208。在波导204上方并且在限定波导204和光栅耦合器206的凹槽中形成介电层208。介电层208可以由氧化硅、氮化硅、它们的组合等形成，并且可以通过CVD、PVD、原子层沉积(ALD)、旋涂介电工艺等或它们的组合形成。在形成之后，可以诸如通过化学机械抛光(CMP)或机械研磨平坦化介电层208以避免波导204的图案转移至介电层208。在实施例中，介电层208是衬底202的材料的氧化物，诸如氧化硅。由于波导204和介电层208的材料的折射率差异，波导204具有高内反射，从而使得光被限制在波导204中，这取决于光的波长和相应材料的反射率。在实施例中，波导204的材料的折射率高于介电层208的材料的折射率。
在图5A和图5B中，在介电层208中形成开口210。可以通过可接受的光刻和蚀刻技术形成开口210。可以实施对介电层208的材料有选择性的一个或多个蚀刻步骤，从而使得开口210基本不会延伸至衬底202内。
在图6A和图6B中，在开口210中形成导电材料，从而在介电层208中形成通孔212。诸如扩散阻挡层、粘合层等的衬垫(未示出)等的衬垫(未示出)可以由TaN、Ta、TiN、Ti、CoW等形成在开口210中，并且可以通过诸如ALD等的沉积工艺形成在开口中。可以在开口210中沉积包括铜或铜合金的晶种层(未示出)。使用例如ECP或化学镀在开口210中形成导电材料。导电材料可以是包括金属或金属合金(诸如铜、银、金、钨、钴、铝或它们的合金)的金属材料。可以实施诸如CMP或机械研磨的平坦化工艺以沿着介电层208的顶面去除过量的导电材料，从而使得通孔212与介电层208的顶面齐平。
在图7A和图7B中，形成介电层213，并且在介电层213中形成导电部件214。介电层213可以由选自介电层208的备选材料的材料形成，或可以包括不同的材料。介电层213可以通过选自形成介电层208的备选方法的方法形成，或可以通过不同的方法形成。例如，在一些实施例中，介电层208由低k介电材料形成。导电部件214可以是线和通孔，并且可以通过例如双镶嵌、单镶嵌等的镶嵌工艺形成。焊盘216形成为连接至介电层213的最上层中的导电部件214，并且可以包括微凸块、导电焊盘、凸块下金属化结构、焊料连接件等。
仅在介电材料213的区域的子集中形成导电部件214。具体地，介电层213的一些区域基本没有导电部件214。该区域是介电层213的沿着用于光信号的光传输路径218的部分。光传输路径218在光栅耦合器206和上面的光源或光信号源(例如，之后附接的光子管芯112)之间延伸。
波导204、介电层208、介电层213、导电部件214和焊盘216的组合形成本文称为的混合互连件220。混合互连件220包括用于互连管芯与电信号的导电部件214，并且也包括用于互连管芯与光信号的波导204。
在图8A和图8B中，将处理器管芯106、存储器管芯108、光子管芯112和电子管芯110附接至混合互连件220。各个管芯每个均包括连接至混合互连件220的焊盘216的管芯连接件116。可以接合各个管芯，从而使得衬底202的前侧以及处理器管芯106、存储器管芯108、光子管芯112和电子管芯110的有源表面彼此相对(“面对面”)。例如，接合可以是例如混合接合、熔融接合、直接接合、介电接合、金属接合、焊料接点(例如，微凸块)等。
在一些实施例中，处理器管芯106通过混合接合而接合至混合互连件220。在这种实施例中，利用诸如处理器管芯106的介电层213和表面介电层(未示出)的氧化物层形成共价键。在实施接合之前，可以对处理器管芯106实施表面处理。下一步，可以实施预接合工艺，其中，处理器管芯106和混合互连件220对准。将处理器管芯106和混合互连件220按压在一起以在介电层213的顶部形成弱接合。在预接合工艺之后，退火处理器管芯106和混合互连件220以增强弱接合。在退火期间，介电层213的顶部中的OH键断裂以在处理器管芯106和混合互连件220之间形成Si-O-Si键，从而增强接合。在混合接合期间，金属接合也发生在处理器管芯106的管芯连接件116和混合互连件220的焊盘216之间。
在一些实施例中，存储器管芯108、光子管芯112和电子管芯110通过导电连接件222接合至混合互连件220。在这种实施例中，导电连接件222由导电材料形成，导电材料诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等的方法形成焊料层来形成导电连接件222。一旦在结构上形成焊料层，则可以实施回流以将导电连接件222成形为期望的凸块形状。导电连接件222形成焊盘216和存储器管芯108、光子管芯112和电子管芯110的管芯连接件116之间的接头。
虽然处理器管芯106示出为通过混合接合而接合至混合互连件220，并且存储器管芯108、光子管芯112和电子管芯110示出为通过导电连接件接合至混合互连件220，但是应该理解，管芯可以通过任何技术接合。例如，所有管芯均可以通过混合接合来接合，或所有管芯均可以通过导电连接件接合。可以使用用于各个管芯的接合类型的任何组合。此外，虽然各个管芯的一些可以示出为彼此紧邻，但是应该理解，管芯可以间隔开。
将光子管芯112接合至混合互连件220，从而使得每个光子管芯112的光学I/O端口118沿着相应的光传输路径218设置。因为光传输路径218基本没有导电部件214，因此光学I/O端口118对波导204的相应的光栅耦合器206具有清晰的视线。
在图9A和图9B中，可以在混合互连件220和由导电连接件222接合的管芯(例如，存储器管芯108、光子管芯112和电子管芯110)之间形成底部填充物224。底部填充物224可以是模制底部填充物、聚合物底部填充物等，并且可以在将管芯附接至混合互连件220之后通过毛细管流动工艺形成，或可以在附接管芯之前通过合适的沉积方法形成。底部填充物224对于用于光信号的光的波长可以是不透明的。
在图10A和图10B中，在各个组件上形成密封剂226。密封剂226可以是模塑料、环氧树脂等，并且可以通过压缩模制、传递模制等施加。可以在混合互连件220上方形成密封剂226，从而掩埋或覆盖处理器管芯106、存储器管芯108、光子管芯112和电子管芯110。之后，固化密封剂226。可以诸如通过CMP平坦化密封剂226。
在图11A和图11B中，减薄衬底202的背侧以暴露通孔212。可以通过诸如CMP、机械研磨等减薄衬底202。介电层208和/或通孔212的导电材料可以具有与衬底202的材料不同的去除速率，从而使得介电层208和/或通孔212用作平坦化停止层。在减薄之后，波导204保持嵌入在介电层208内。
在图12A和图12B中，在暴露的通孔212、介电层208的背侧和波导204上形成导电焊盘228。导电焊盘228电连接至处理器管芯106、存储器管芯108、光子管芯112和电子管芯110。导电焊盘228可以是铝焊盘或铝铜焊盘，但是可以使用其它金属焊盘。
在介电层208的背侧和波导204上形成覆盖导电焊盘228的钝化膜230。钝化膜230可以由介电材料形成，介电材料诸如氧化硅、氮化硅等或它们的组合。穿过钝化膜230形成开口以暴露导电焊盘228的中心部分。
在导电焊盘228和钝化膜230上形成凸块下金属(UBM)232。可以通过在钝化膜230上和开口中形成毯式导电层(诸如通过电镀)来形成UBM232。导电层可以由铜、铜合金、银、金、铝、镍等和它们的组合形成。可以图案化导电层以形成UBM 232。
可以在UBM 232上形成导电连接件234。导电连接件234可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件234可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转印、球植等常用的方法形成焊料层来形成导电连接件234。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件234是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在导电连接件234的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们组合，并且可以通过镀工艺形成。
在形成之后，可以分割晶圆中形成的多芯片系统100。每个分割的多芯片系统100均包括多个位点102。
图13是根据一些实施例的操作期间产生的多芯片系统100的截面图。具体地，示出了从位点102A至位点102B的光信号120的传输。在传输期间，电子管芯110根据来自处理器管芯106的电信号控制发射位点102A的光子管芯112来调制载波信号并且产生光信号120。光信号120传输至波导204。接收位点102B的光子管芯112接收光信号120并且解调它们以产生相应的电信号，将电信号发送至处理器管芯106。因此，光路径104用作具有低延时的高带宽和高密度信号路由器件。具体地，与具有硅通孔(TSV)的路由信号相比，光路径104可以在高频处具有较少的信号衰减、较少的串扰和较少的开关噪声。
图14A至图24B是根据一些其它实施例的在用于形成多芯片系统100的工艺期间的中间步骤的各个视图。图14A至图24B是截面图，其中，沿着图1B的截面A-A(例如，沿着处理器管芯106和存储器管芯108)示出以字符“A”结尾的图，并且沿着图1B的截面B-B(例如，沿着存储器管芯108、光子管芯112和电子管芯110)示出以字符“B”结尾的图。
在图14A和图14B中，提供衬底302。衬底302是绝缘体上半导体(SOI)衬底，其包括形成在绝缘层302B上的半导体材料层302A。绝缘层302B可以是例如埋氧(BOX)层、氧化硅层等。在通常为硅或玻璃衬底的半导体材料302C上提供绝缘层302B。
在图15A和图15B中，图案化衬底302的前侧以形成波导204。可以用可接受的光刻和蚀刻技术完成衬底302的图案化。具体地，在半导体材料302A中蚀刻开口，并且半导体材料302A的剩余部分形成波导204。绝缘层302B可以用作蚀刻工艺的蚀刻停止层。也在波导204的顶部中形成光栅耦合器206。
在图16A和图16B中，在衬底302的前侧上形成介电层208。具体地，在波导204和绝缘层302B上、限定波导204的半导体材料302A的开口中以及限定光栅耦合器206的凹槽中形成介电层208。在一些实施例中，介电层208与绝缘层302B的材料相同。
在图17A和图17B中，形成开口210。在所示的实施例中，开口210穿过介电层208、穿过绝缘层302B并且部分地延伸至半导体材料302C。可以通过可接受的光刻和蚀刻技术形成开口210。
在图18A和图18B中，在开口210中形成导电材料，从而在介电层208中形成通孔212。可以实施诸如CMP或机械研磨的平坦化工艺以沿着介电层208的顶面去除过量的导电材料，从而使得通孔212与介电层208的顶面齐平。
在图19A和图19B中，形成介电层213，并且在介电层213中形成导电部件214。焊盘216形成为连接至介电层213的最上层中的导电部件214。介电层213的一些区域基本没有导电部件214，该区域限定用于光信号的光传输路径218。波导204、介电层208、介电层213、导电部件214和焊盘216的组合形成混合互连件220。
在图20A和图20B中，将处理器管芯106、存储器管芯108、光子管芯112和电子管芯110附接至混合互连件220。各个管芯均以面对面方式接合。在一些实施例中，处理器管芯106通过混合接合而接合至混合互连件220，而存储器管芯108、光子管芯112和电子管芯110通过导电连接件222接合至混合互连件220。将光子管芯112接合至混合互连件220，从而使得每个光子管芯112的光学I/O端口118沿着相应的光传输路径218设置。
在图21A和图21B中，可以在混合互连件220和由导电连接件222接合的管芯(例如，存储器管芯108、光子管芯112和电子管芯110)之间形成底部填充物224。
在图22A和图22B中，在各个组件上形成密封剂226。可以在混合互连件220上方形成密封剂226，从而掩埋或覆盖处理器管芯106、存储器管芯108、光子管芯112和电子管芯110。之后，固化并且可以平坦化密封剂226。
在图23A和图23B中，减薄衬底202的背侧以暴露通孔212。可以通过诸如CMP、机械研磨等减薄衬底202，这减薄了半导体材料302C。绝缘层302B作为减薄工艺的蚀刻停止层。在一些实施例中，在平坦化之后，保留半导体材料302C的薄部分。在减薄之后，波导204保持嵌入在介电层208内并且暴露通孔212。
在图24A和图24B中，在暴露的通孔212、剩余的半导体材料302C的背侧上形成导电焊盘228。在导电焊盘228和剩余的半导体材料302C的背侧上形成钝化膜230。穿过钝化膜230形成开口以暴露导电焊盘228的中心部分。在导电焊盘228和钝化膜230上形成UBM 232。在UBM 232上形成导电连接件234。
在形成之后，可以分割晶圆中形成的多芯片系统100。每个分割的多芯片系统100均包括多个位点102。
图25是根据一些其它实施例的操作期间产生的多芯片系统100的截面图。波导204的所有侧面均由折射率低于波导204的材料的折射率的材料包覆。具体地，波导204由介电层208和绝缘层302B围绕。如此，可以因此改善波导204的全内反射。
实施例可以实现许多优势。与使用TSV传输电信号相比，在混合互连件220中传输光信号可以在高频处具有较少的信号衰减、较少的串扰和较少的开关噪声。光通信可以允许一些位点102之间的较低延时和较高带宽的通信。导电部件214允许电信号也在位点102之间传输。在同一混合互连件220中允许电和光互连可以允许增加例如包括许多互连计算机系统的HPC应用程序中的器件性能。
在实施例中，互连件包括：第一介电层，包括具有第一折射率的第一材料，第一介电层具有第一表面和与第一表面相对的第二表面；位于第一介电层中的波导，该波导具有由波导中的凹槽限定的光栅耦合器，波导包括具有大于第一折射率的第二折射率的第二材料；位于第一介电层的第一表面上的多个第二介电层，第二介电层的每个均包括第一材料；位于第二介电层中的多个导电部件，导电部件包括导线和通孔，从光栅耦合器延伸至第二介电层的顶面的光传输路径没有导电部件；穿过第一介电层延伸的多个通孔；以及位于第一介电层的第二表面上的多个导电连接件，通孔将导电连接件电连接至导电部件。
在一些实施例中，第一材料是硅并且第二材料是氧化硅。在一些实施例中，互连件还包括：位于第二介电层的最上层中的焊盘，该焊盘电连接至通孔。在一些实施例中，没有导电部件设置在沿着光传输路径的每个第二介电层中。在一些实施例中，通孔的顶面与第一介电层的第一表面齐平，并且通孔的底面与第一介电层的第二表面齐平。在一些实施例中，波导的底面与第一介电层的第二表面齐平。在一些实施例中，第一介电层位于波导上并且围绕波导。在一些实施例中，第一介电层设置在限定光栅耦合器的波导的凹槽中。在一些实施例中，互连件还包括：绝缘层，具有第一侧和与第一侧相对的第二侧，波导设置在绝缘层的第一侧上，通孔穿过绝缘层延伸；以及半导体材料，半导体材料设置在绝缘层的第二侧上，通孔穿过半导体材料延伸。
在实施例中，方法包括：图案化衬底的部分以形成波导，衬底具有第一表面和与第一表面相对的第二表面；在波导和衬底的第一表面上沉积第一介电层；形成穿过第一介电层延伸的通孔；在第一介电层上沉积多个第二介电层；在第二介电层中形成多个导电部件，第二介电层的第一区域没有导电部件；将多个管芯附接至第二介电层，管芯电连接至导电部件，管芯通过第二介电层的第一区域光连接至波导；减薄衬底的第二表面以暴露通孔；并且形成电连接至通孔的导电连接件。
在一些实施例中，衬底由具有第一折射率的材料形成，并且第一介电层由具有小于第一折射率的第二折射率的材料形成。在一些实施例中，该方法还包括：在衬底上形成激光源，波导在衬底周围连续延伸，激光源光耦合至波导。在一些实施例中，该方法还包括：在波导中形成凹槽以限定波导中的光栅耦合器。在一些实施例中，在第二介电层的第二区域中形成导电部件，第二介电层的第一区域从光栅耦合器延伸至第二介电层的顶面。在一些实施例中，衬底包括连续的半导体材料，并且其中，图案化衬底的部分以形成波导，包括：在半导体材料中形成凹槽，衬底的未凹进部分形成波导。在一些实施例中，衬底包括绝缘层上半导体材料，并且其中，图案化衬底的部分以形成波导，包括：在半导体材料中形成开口以暴露绝缘层，半导体材料的剩余部分形成波导。
在实施例中，方法包括：形成包括设置在多个介电层中的波导和导电部件的互连件，导电部件包括导线和通孔，波导由具有第一折射率的第一材料形成，介电层由具有小于第一折射率的第二折射率的第二材料形成；将多个管芯接合至互连件的第一侧，管芯通过导电部件电连接，管芯通过波导光连接；以及在互连件的第二侧上形成多个导电连接件，导电连接件通过导电部件电连接至管芯。
在一些实施例中，波导包括光栅耦合器，并且其中，互连件在波导的光栅耦合器和相应的光子集成电路之间延伸的区域中基本上没有导电部件。在一些实施例中，将多个管芯接合至互连件的第一侧包括：利用混合接合将多个管芯接合至互连件的第一侧。在一些实施例中，将多个管芯接合至互连件的第一侧包括：利用导电连接件将多个管芯接合至互连件的第一侧。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种互连件，包括：
第一介电层，包括具有第一折射率的第一材料，所述第一介电层具有第一表面和与所述第一表面相对的第二表面；
波导，位于所述第一介电层中，所述波导具有由所述波导中的凹槽限定的光栅耦合器，所述波导包括具有大于所述第一折射率的第二折射率的第二材料；
多个第二介电层，位于所述第一介电层的第一表面上，所述第二介电层的每个均包括所述第一材料；
多个导电部件，位于所述第二介电层中，所述导电部件包括导线和第一通孔，从所述光栅耦合器延伸至所述第二介电层的顶面的光传输路径没有所述导电部件；
多个第二通孔，延伸穿过所述第一介电层；以及
多个导电连接件，位于所述第一介电层的第二表面上，所述第二通孔将所述导电连接件电连接至所述导电部件。
2.根据权利要求1所述的互连件，其中，所述第一材料是硅并且所述第二材料是氧化硅。
3.根据权利要求1所述的互连件，还包括：
焊盘，位于所述第二介电层的最上层中，所述焊盘电连接至所述第二通孔。
4.根据权利要求1所述的互连件，其中，没有导电部件设置在沿着所述光传输路径的所述第二介电层的每个中。
5.根据权利要求1所述的互连件，其中，所述第二通孔的顶面与所述第一介电层的所述第一表面齐平，并且所述第二通孔的底面与所述第一介电层的所述第二表面齐平。
6.根据权利要求1所述的互连件，其中，所述波导的底面与所述第一介电层的所述第二表面齐平。
7.根据权利要求1所述的互连件，其中，所述第一介电层位于所述波导上并且围绕所述波导。
8.根据权利要求1所述的互连件，其中，所述第一介电层设置在限定所述光栅耦合器的所述波导的凹槽中。
9.根据权利要求1所述的互连件，还包括：
绝缘层，具有第一侧和与所述第一侧相对的第二侧，所述波导设置在所述绝缘层的第一侧上，所述第二通孔延伸穿过所述绝缘层；以及
半导体材料，所述半导体材料设置在所述绝缘层的所述第二侧上，所述第二通孔延伸穿过所述半导体材料。
10.一种形成互连器件的方法，包括：
图案化衬底的部分以形成波导，所述衬底具有第一表面和与所述第一表面相对的第二表面；
在所述波导和所述衬底的所述第一表面上沉积第一介电层；
形成延伸穿过所述第一介电层的通孔；
在所述第一介电层上沉积多个第二介电层；
在所述第二介电层中形成多个导电部件，所述第二介电层的第一区域没有所述导电部件；
将多个管芯附接至所述第二介电层，所述管芯电连接至所述导电部件，所述管芯通过所述第二介电层的所述第一区域光连接至所述波导；
减薄所述衬底的所述第二表面以暴露所述通孔；以及
形成电连接至所述通孔的导电连接件。
11.根据权利要求10所述的方法，其中，所述衬底由具有第一折射率的材料形成，并且所述第一介电层由具有小于所述第一折射率的第二折射率的材料形成。
12.根据权利要求10所述的方法，还包括：
在所述衬底上形成激光源，所述波导在所述衬底周围连续延伸，所述激光源光耦合至所述波导。
13.根据权利要求10所述的方法，还包括：
在所述波导中形成凹槽以限定所述波导中的光栅耦合器。
14.根据权利要求13所述的方法，其中，在所述第二介电层的第二区域中形成所述导电部件，所述第二介电层的所述第一区域从所述光栅耦合器延伸至所述第二介电层的顶面。
15.根据权利要求10所述的方法，其中，所述衬底包括连续的半导体材料，并且其中，图案化所述衬底的部分以形成所述波导包括：
在所述半导体材料中形成凹槽，所述衬底的未凹进部分形成所述波导。
16.根据权利要求10所述的方法，其中，所述衬底包括绝缘层上的半导体材料，并且其中，图案化所述衬底的部分以形成所述波导包括：
在所述半导体材料中形成开口以暴露所述绝缘层，所述半导体材料的剩余部分形成所述波导。
17.一种形成互连器件的方法，包括：
形成互连件，所述互连件包括设置在具有第一介电层和第二介电层的多个介电层中的波导和导电部件，所述波导由具有第一折射率的第一材料形成，所述多个介电层由具有小于所述第一折射率的第二折射率的第二材料形成，形成所述互连件包括：
在所述波导周围沉积所述第一介电层；
从所述第一介电层的第一侧到所述第一介电层的第二侧形成多个通孔；
在所述第一介电层的所述第一侧上沉积多个第二介电层，所述第二介电层由所述第二材料形成；
在所述第二介电层中形成多个导线，所述导电部件包括所述多个导线和所述通孔；
将多个管芯接合至所述导线，所述管芯通过所述导线电连接，所述管芯通过所述波导光连接；以及
在所述第一介电层的第二侧上形成多个导电连接件，所述导电连接件通过所述导电部件电连接至所述管芯。
18.根据权利要求17所述的方法，其中，所述波导包括光栅耦合器，并且其中，所述互连件在所述波导的所述光栅耦合器和相应的光子集成电路之间延伸的区域中没有所述导电部件。
19.根据权利要求17所述的方法，其中，将所述多个管芯接合至所述导线包括：
利用混合接合将所述多个管芯接合至所述导线。
20.根据权利要求17所述的方法，其中，将所述多个管芯接合至所述导线包括：
利用另一导电连接件将所述多个管芯接合至所述导线。
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