CN109842382A - Digital analog converter, digital power amplifier subsystem, digital power amplifier system - Google Patents
Digital analog converter, digital power amplifier subsystem, digital power amplifier system Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of digital analog converters, digital power amplifier subsystem, digital power amplifier system, the digital analog converter includes: the first composition branch and the second composition branch, the first composition branch includes: concatenated first switch structure and the first current source, first current source includes: the 4th resistance, first field-effect tube, second field-effect tube and second operational amplifier, the second composition branch includes: concatenated second switch structure and the second current source, second current source includes: the 5th resistance, third field-effect tube, 4th field-effect tube and third operational amplifier, when being applied to digital power amplifier system, considerably increase the equivalent output impedance of the digital analog converter, reduce the power supply rejection ratio of the digital power amplifier system.
Description
Technical field
The present invention relates to field of circuit technology more particularly to a kind of digital analog converters, digital power amplifier subsystem, number
Power amplification system.
Background technique
Digital power amplifier has many advantages, such as that the small, low noise of distortion, dynamic range be big and strong antijamming capability, in the transparent of sound quality
Advantage in terms of degree, parsing power, quiet and low frequency the shock dynamics of background substantially exceeds traditional analog amplifier and class
D power amplifier.
With DVD home theater, mini audio system, set-top box, PC, LCD TV, flat-panel monitor and movement
The new source of sound specification of some high sample frequencys of the update of the consumer products such as phone, especially SACD, DVD Audio etc. goes out
Existing and sound system all accelerates the development of digital power amplifier from stereo to the evolution of multichannel surrounding system.
It is existing a kind of new noun " pure digi-tal power amplifier " occur for HIFI enthusiast in digital power amplifier field,
It supports many digital audio-format signals to input, such as 12S and TDM, can be handled by number DSP, realize sound abundant
Imitate algorithm, there is very strong RF anti-interference ability, on mobile phone, there is natural advantage, digital signal in transmission process not
The problems such as phase delay, phase distortion and intermodulation distortion can be brought, the benefit of sense of hearing be exactly sound can be more fully apparent from, position it is more quasi- with
And sound is closer to really.
But in some application systems, power supply is often less clean, has the power supply ripple of different frequency, if audio function
The power supply rejection ratio (PSRR) for putting chip is made imperfect words, and the audio-frequency noise on power supply will be passed by audio frequency power amplifier chip
It is sent on loudspeaker, causes irritated audio-frequency noise, influence voice or music sense of hearing.
Summary of the invention
In order to solve the above technical problems, the embodiment of the invention provides a kind of digital analog converter, to be applied to number
When word power amplification system, the power supply rejection ratio of the digital power amplifier system is reduced, reduces output noise, improves audio output quality.
To solve the above problems, the embodiment of the invention provides following technical solutions:
A kind of digital analog converter, comprising:
First composition branch and the second composition branch, wherein the first composition branch first end and voltage input end connect
It connects, second end is electrically connected with common-mode voltage input terminal, and third end is connect with the second composition branch；The second composition branch
First end is electrically connected with the first composition branch, and second end ground connection, third end is electrically connected with the common-mode voltage input terminal；Institute
State signal output end of the connecting node of the first composition branch and the second composition branch as the digital analog converter；
The first composition branch includes: concatenated first switch structure and the first current source, the first switch structure
It is switched including first switch and third, one end of the first switch is electrically connected with voltage input end, the other end and described first
One end of current source electrical connection, the third switch is electrically connected with common-mode voltage input terminal, the other end and first current source
Electrical connection；First current source includes: the 4th resistance, the first field-effect tube, the second field-effect tube and second operational amplifier,
Wherein,
Described 4th resistance one end is the first end of first current source, is electrically connected with the first switch structure, separately
One end is electrically connected with the first end of the first field-effect tube；
The second end of first field-effect tube is electrically connected with the first end of second field-effect tube, first effect
Should the control terminal of pipe be electrically connected with the output end of the second operational amplifier；
The inverting input terminal of the second operational amplifier is electrically connected with the first end of first field-effect tube, with mutually defeated
Enter end and be electrically connected to the first preset potential, first preset potential is equal to the voltage of voltage input end and the difference of reference voltage
First field-effect tube is biased in work for exporting the first bias voltage to first field-effect tube by value, output end
State；
The second end of second field-effect tube is the second end of first current source, with the second composition branch electricity
Connection, the control terminal of second field-effect tube are electrically connected the second bias voltage, and second bias voltage is used for described the
Two field-effect tube are biased in working condition；
The second composition branch includes: concatenated second switch structure and the second current source, the second switch structure
It include: second switch and the 4th switch, one end of the second switch is electrically connected with ground terminal, the other end and second electric current
One end of source electrical connection, the 4th switch is electrically connected with the common-mode voltage input terminal, the other end and second current source
Electrical connection；Second current source includes: the 5th resistance, third field-effect tube, the 4th field-effect tube and third operational amplifier,
Wherein,
Described 5th resistance one end is the first end of second current source, is electrically connected with the second switch structure, separately
One end is electrically connected with the first end of the 4th field-effect tube；
The second end of 4th field-effect tube is electrically connected with the first end of the third field-effect tube, the 4th effect
Should the control terminal of pipe be electrically connected with the output end of the third operational amplifier；
The inverting input terminal of the third operational amplifier is electrically connected with the first end of the 4th field-effect tube, with mutually defeated
Enter end and be electrically connected to the second preset potential, second preset potential is equal to the reference voltage, and output end is for exporting the 4th
4th field-effect tube is biased in working condition by bias voltage；
The second end of the third field-effect tube is the second end of second current source, with the first composition branch electricity
Connection, the control terminal of the third field-effect tube are electrically connected third bias voltage, and the third bias voltage is used for described the
Three field-effect tube are biased in working condition；
Wherein, the switching sequence of the first switch and the second switch is on the contrary, the first switch and third switch
Timing is on the contrary, the second switch and the 4th switching sequence are opposite.
Optionally, first field-effect tube and second field-effect tube are p-type field-effect tube, the third field-effect
Pipe and the 4th field-effect tube are N-type field-effect tube.
Optionally, the 4th resistance is identical with the resistance value of the 5th resistance.
Optionally, the switch state of the first switch is controlled by the first input signal, the switch shape of the second switch
State is controlled by the second input signal, and the first switch and the second switch is the identical transistor of type, the first input letter
Number and the second input signal be opposite in phase square-wave signal.
Optionally, the switch state of the first switch is controlled by the first input signal, the switch shape of the second switch
State is controlled by the second input signal, and the first switch and the second switch is different types of transistor, the first input letter
Number and the second input signal be the identical square-wave signal of phase.
Optionally, the switch state of the third switch is controlled by second input signal, and the 4th switch is opened
Off status is controlled by first input signal, and the first switch and the 4th switch are the identical transistor of type, and described the
Two switches and third switch are the identical transistor of type.
A kind of digital power amplifier subsystem, the digital power amplifier subsystem include:
Digital analog converter provided by any of the above-described, the first operational amplifier, integrator, PWM comparator, driving
Device, first resistor and first capacitor, wherein
The inversion signal input terminal phase of the signal output end of the digital analog converter and first operational amplifier
Even, the positive signal input part of first operational amplifier is for receiving common mode voltage signal, first operational amplifier
Signal output end be connected with the signal input part of the integrator；
The signal output end of the integrator is connected with the signal input part of the PWM comparator, the PWM comparator
Signal output end is connected with the signal input part of the driver, and the signal output end of the driver is as above-mentioned digital power amplifier
The signal output end of subsystem；
One end of the first resistor is connected to the connection section of the digital analog converter Yu first operational amplifier
Point, another signal output end for being terminated at the driver of the first resistor；
One end of the first capacitor is connected to the connection section of first operational amplifier Yu the digital analog converter
Point, another connecting node for being terminated at first operational amplifier and the integrator of the first capacitor C1.
Optionally, the common mode voltage signal can be the received voltage input end input of the digital analog converter
The half of voltage signal.
A kind of digital power amplifier system, the digital power amplifier system include the first digital power amplifier subsystem and the second digital power amplifier
Subsystem, wherein the first digital power amplifier subsystem is the channel VOP；The second digital power amplifier subsystem is the channel VON；
At least one digital power amplifier subsystem in the first digital power amplifier subsystem and the second digital power amplifier subsystem
System is using digital power amplifier subsystem provided by any of the above-described.
Compared with prior art, above-mentioned technical proposal has the advantage that
Digital analog converter provided by the embodiment of the present invention is considerably increased when being applied to digital power amplifier system
The equivalent output impedance of the digital analog converter reduces the power supply rejection ratio of the digital power amplifier system.
Moreover, digital analog converter provided by the embodiment of the present invention not only may be used when being applied to digital power amplifier system
With by the resistance for adjusting first field-effect tube, the second field-effect tube, third field-effect tube and the 4th field-effect tube or across
The equivalent impedance for increasing the digital analog converter is led, it can also be by adjusting the 4th resistance and the 5th resistance
Resistance value increases the equivalent impedance of the digital analog converter, can also be by adjusting the second operational amplifier and described
The gain of third operational amplifier increases the equivalent impedance of the digital analog converter, to further decrease the digital function
The power supply rejection ratio of place system improves the noise signal rejection ability of the digital power amplifier system.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is that the structure of the digital power amplifier system of the application of digital analog converter provided by one embodiment of the invention is shown
It is intended to；
Fig. 2 is a kind of structural schematic diagram of digital power amplifier subsystem；
Fig. 3 is the structural schematic diagram of digital analog converter provided by one embodiment of the invention；
Fig. 4 is the schematic equivalent circuit of digital analog converter provided by one embodiment of the invention；
Fig. 5 is the structural schematic diagram of digital power amplifier subsystem provided by another embodiment of the present invention；
Fig. 6 is the first input signal PWM_P, the second input signal/PWM_P, the common mode voltage signal VCM, institute
The output signal DAC_VO and the comparison of wave shape of the output signal VOP of the digital power amplifier subsystem for stating digital analog converter show
It is intended to.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
As shown in FIG. 1, FIG. 1 is a kind of digital analog converters provided in an embodiment of the present invention to be applied to digital power amplifier system
When, the structural schematic diagram of digital power amplifier system, by digital module, treated that pwm signal is converted into analog signal for effect,
Including two channels VOP and VON, since VOP is similar with the working principle in two channels VON, below with the digital function in the channel VOP
It puts and is illustrated for subsystem.
With reference to Fig. 2, Fig. 2 is a kind of structural schematic diagram of the digital power amplifier subsystem in channel VOP, the number in the channel VOP
Word power amplifier subsystem includes: digital analog converter DAC, the first operational amplifier AMP1, integrator 21, PWM comparator 22, drives
Dynamic device 23, first resistor RF and capacitor C1 and common mode voltage signal generation module 24.
Wherein, the signal output end DAC_VOP of the digital analog converter DAC and the first operational amplifier AMP1
Inverting input terminal connection, the non-inverting input terminal of the first operational amplifier AMP1 and the common mode voltage signal generation module
24 output end VCM connection, the output terminals A MP_VP1 of the first operational amplifier AMP1 and the input terminal of the integrator 21
Connection.
The output end of the integrator 21 is connect with the input terminal of the PWM comparator 22, the PWM comparator 22 it is defeated
Outlet PWM_P2 is connect with the input terminal of the driver 23, and the output end of the driver is as the digital power amplifier subsystem
Signal output end VOP.
One end of the first resistor RF is connect with the inverting input terminal of the first operational amplifier AMP1, and described first
The other end of resistance RF is connect with the output end of the driver.
One end of the capacitor C1 is connect with the inverting input terminal of the first operational amplifier AMP1, the capacitor C1's
The other end is connect with the output terminals A MP_VP1 of the first operational amplifier AMP1.
Wherein, the common mode voltage signal generation module 24 includes: second resistance R1 and 3rd resistor R2, wherein described
One end of second resistance R1 is connect with voltage input end VDD, and the other end of the second resistance R1 is with the 3rd resistor R2's
One end connection；The other end of the 3rd resistor R1 is connect with ground terminal GND；The second resistance R1 and 3rd resistor R2
Output end VCM of the connecting node as the common-mode voltage generation module 24.
In the above-described embodiments, the signal output end VOP of the digital power amplifier subsystem passes through first resistor RF, the first fortune
It calculates amplifier AMP1, integrator 21, PWM comparator 22 and driver 23 and forms feedback loop, to the digital power amplifier subsystem
The distorted signals and power supply noise of system are inhibited.
For the digital power amplifier subsystem in the above-mentioned channel VOP, due to the power supply rejection ratio of digital analog converter DAC
Very high with the power supply rejection ratio of the first operational amplifier AMP1, the loop gain of digital power amplifier subsystem is very big, therefore, digital function
It puts the power supply noise in the feedback loop of subsystem to tend to be inhibited well, is not to influence the digital power amplifier subsystem
Power supply rejection ratio key, and the output end VCM of the common mode voltage signal generation module is to the letter of digital power amplifier subsystem
Number output end VOP forms amplifier in the same direction, and the voltage on the output end VCM of the common mode voltage signal generation module is restless same
It is the key that the power supply rejection ratio for influencing the sub- power amplification system of number to amplification.
Similarly, the digital power amplifier subsystem in the channel VON and the digital power amplifier subsystem in the channel VOP are identical, no longer explain herein
It states.
It is derived below with reference to power supply rejection ratio PSRR of the Fig. 1 and Fig. 2 to digital power amplification system, specific as follows:
Firstly, the voltage signal VCM that exports of the common mode voltage signal generation module 24 passes through the by voltage input end VDD
Two resistance R1 and 3rd resistor R2 divide to obtain, specifically:
Definition,
So, the output pulsation of the digital power amplifier subsystem in the channel VOP are as follows:
Δ VOP=Δ VDD* α * (1+RFP/r0P_dac)
Similarly, the output pulsation of the digital power amplifier subsystem in the channel VON are as follows:
Δ VON=Δ VDD* α * (1+RFN/r0N_dac)
Wherein, r0P_dac indicates that the equivalent output impedance of the digital analog converter DAC in the channel VOP, r0N_dac indicate
The equivalent output impedance of the digital analog converter DAC in the channel VON, RFP indicate the RF resistance (i.e. first resistor) in the channel VOP,
RFN indicates that the RF resistance in the channel VON, Δ VDD indicate the fluctuation of the received voltage signal VDD of digital analog converter DAC.
The output pulsation of the digital power amplifier system are as follows:
Δ Vout=Δ VOP- Δ VON
That is, the output pulsation of digital power amplifier system are as follows:
And since there are mismatch, mismatching δ for the current source of the digital analog converter DAC in the channel VOP and the channel VON1
Meet the following conditions:
R0P_dac=(1+ δ1)*r0N_dac
Since there is also mismatch, mismatching δ for the RF resistance in the channel VOP and the channel VON2Meet the following conditions:
RFP=(1+ δ2)*RFN
Then, the output pulsation of the digital power amplifier system are as follows:
The power supply rejection ratio PSRR of the digital power amplifier system are as follows:
Wherein, RF indicates the resistance value of the RF resistance in the channel VOP or the channel VON, and r0_dac indicates the channel VOP or the channel VON
Digital analog converter DAC equivalent output impedance.
By the formula of the power supply rejection ratio of above-mentioned digital power amplifier system it is found that the equivalent output of digital analog converter DAC
Impedance r0_dac is on the denominator of the formula, i.e. the equivalent output impedance r0_dac of digital analog converter DAC is bigger, the number
The power supply rejection ratio PSRR of word power amplification system is smaller, and the Power supply rejection ability of the digital power amplifier system is better.
Based on this, the embodiment of the invention provides a kind of digital analog converter and including the digital analog converter
Digital power amplifier subsystem, the digital power amplifier system including the digital power amplifier subsystem.
As shown in figure 3, digital analog converter provided by the embodiment of the present invention includes: the first composition branch and second group
At branch, wherein the first composition branch first end is connect with voltage input end VDD, second end and common-mode voltage input terminal
VCM electrical connection, third end are connect with the second composition branch；The second composition branch first end and the first composition branch
Road electrical connection, second end ground connection, third end is electrically connected with the common-mode voltage input terminal VCM；The first composition branch and institute
State signal output end DAC_VOP of the connecting node of the second composition branch as the digital analog converter DAC；
The first composition branch includes: concatenated first switch structure and the first current source IDAC1, the first switch
Structure includes first switch S1 and third switch S3, wherein one end of the first switch S1 is electrically connected with voltage input end VDD
It connects, the other end is electrically connected with the first current source IDAC1, one end of the third switch S3 and common-mode voltage input terminal VCM
Electrical connection, the other end are electrically connected with the first current source IDAC1；The first current source IDAC1 include: the 4th resistance RS1,
First field-effect tube M1, the second field-effect tube M2 and second operational amplifier AMP2, wherein
Described 4th one end resistance RS1 is the first end of the first current source IDAC1, with the first switch structure electricity
Connection, the other end are electrically connected with the first end of the first field-effect tube M1；
The second end of the first field-effect tube M1 is electrically connected with the first end of the second field-effect tube M2, and described first
The control terminal of field-effect tube M1 is electrically connected with the output end of the second operational amplifier AMP2；
The inverting input terminal of the second operational amplifier AMP2 is electrically connected with the first end of the first field-effect tube M1,
Non-inverting input terminal is electrically connected to the first preset potential, voltage of first preset potential equal to voltage input end VDD and reference
The difference of voltage VREF, output end is for exporting the first bias voltage VBP1 to first field-effect tube, by described first
Effect pipe is biased in working condition；
The second end of the second field-effect tube M2 is the second end of the first current source IDAC1, with described second group
It is electrically connected at branch, the control terminal of the second field-effect tube M2 is electrically connected the second bias voltage VBP2, second biased electrical
Pressure VBP2 is used to second field-effect tube being biased in working condition；
The second composition branch includes: concatenated second switch structure and the second current source IDAC2, the second switch
Structure includes: second switch S2 and the 4th switch S4, and one end of the second switch S2 is electrically connected with ground terminal GND, the other end
It is electrically connected with the second current source IDAC2, one end of the 4th switch S4 is electrically connected with the common-mode voltage input terminal VCM
It connects, the other end is electrically connected with the second current source IDAC2；The second current source IDAC2 includes: the 5th resistance RS2, third
Field-effect tube M3, the 4th field-effect tube M4 and third operational amplifier AMP3, wherein
Described 5th one end resistance RS2 is the first end of the second current source IDAC2, with the second switch structure electricity
Connection, the other end are electrically connected with the first end of the 4th field-effect tube M4；
The second end of the 4th field-effect tube M4 is electrically connected with the first end of the third field-effect tube M3, and the described 4th
The control terminal of field-effect tube M4 is electrically connected with the output end of the third operational amplifier AMP3；
The inverting input terminal of the third operational amplifier AMP3 is electrically connected with the first end of the 4th field-effect tube M4,
Non-inverting input terminal is electrically connected to the second preset potential, and second preset potential is equal to reference voltage VREF, and output end is for defeated
4th field-effect tube is biased in working condition by the 4th bias voltage VBN2 out；
The second end of the third field-effect tube M3 is the second end of the second current source IDAC2, with described first group
It is electrically connected at branch, the control terminal of the third field-effect tube M3 is electrically connected third bias voltage VBN1, the third biased electrical
Pressure VBN1 is used to the third field-effect tube being biased in working condition.
In the above-described embodiments, the first bias voltage VBP1 is generated by second operational amplifier AMP2, and described
Four bias voltage VBN2 are generated by third operational amplifier AMP3, the first bias voltage VBP1 and the 4th bias voltage
VBN2 gives the control terminal of the first field-effect tube M1 and the 4th field-effect tube M4 to provide voltage respectively, forms mirror current source IDAC,
Improve the output impedance of the digital analog converter.
It should be noted that on the basis of the above embodiments, in one embodiment of the invention, second biasing
Voltage VBP2 and third bias voltage VBN1 generates branch by additional electric current and generates, be respectively supplied to the second field-effect tube M2 and
The control terminal of third field-effect tube M3 forms mirror current source, improves the output impedance of digital analog converter.But the present invention couple
This and without limitation, in other embodiments of the invention, the digital analog converter can also include the second bias voltage
Generation circuit and third bias voltage generation circuit, with the inside of the digital analog converter generate it is described second partially
Voltage and the third bias voltage are set, is specifically depended on the circumstances.
From the foregoing, it will be observed that in digital analog converter provided by the embodiment of the present invention, first current source and described
Two current sources are all made of cascode structure, so as to improve the output resistance of first current source and second current source
Anti- and stability, and then the power supply rejection ability of the digital analog converter is improved, reduce the digital analog converter
Influence of the output end DAC_VO to first current source and second current source.
Optionally, on the basis of the above embodiments, in one embodiment of the invention, first field-effect tube and
Second field-effect tube is p-type field-effect tube, and the third field-effect tube and the 4th field-effect tube are N-type field-effect
Pipe, the present invention to this and without limitation, specifically depend on the circumstances.
It should be noted that in embodiments of the present invention, the 4th resistance RS1 and the 5th resistance RS2 are identical, so that first
The electric current IDAC2 for forming the composition branch of electric current IDAC1 and second of branch is equal.
In the above-described embodiments, the second operational amplifier AMP2, the first field-effect tube M1 and the 4th resistance RS1 are formed
Source negative feedback generates electric current, and it is negative that third operational amplifier AMP3, the 4th field-effect tube M4 and the 5th resistance RS2 form source electrode
Feedback generates electric current, current value are as follows:
Wherein, RS1,2 indicate the resistance of RS1 or RS2, wherein the resistance value of RS1 and RS2 is identical.
Optionally, based on any of the above embodiments, in one embodiment of the invention, the first field-effect tube M1
The corresponding current source IDAC2 of corresponding current source IDAC1 and third field-effect tube M3 should guarantee in technique change and not as far as possible
It is almost equal under synthermal, to guarantee that the digital power amplifier subsystem is defeated when the first input signal PWM_P is 50% duty ratio
The signal of outlet VOP output is also 50% duty ratio, so that digital power amplifier subsystem output end VOP output DC voltage is VDD/
2。
It should be noted that in embodiments of the present invention, the switch shape of the first switch S1 and the 4th switch S4
State is controlled by the first input signal PWM_P, and the switch state of the second switch S2 and the third switch S3 are by the second input
Signal/PWM_P control, and the switching sequence of the first switch S1 and second switch S2 is on the contrary, the first switch S1 and institute
The switching sequence of third switch S3 is stated on the contrary, the switching sequence of the second switch S2 and the 4th switch S4 are opposite.Wherein,
The first input signal PWM_P and the second input signal/PWM_P is by the digital module in digital power amplifier system to receiving
The digital input signals such as I2S, TDM obtain after audio effect processing, digital gain amplification and digital filtering, usually pwm signal,
That is square-wave signal.
In embodiments of the present invention, the switching sequence of the first switch S1 and second switch S2 refers on the contrary: same
In period, when the first switch S1 in the closure state, the second switch S2 is in an off state, when described first
When switch S1 is in an off state, the second switch S2 is in closed state, so that the first current source IDAC1 or second
The image current that current source IDAC2 is generated is exported as output signal.
The switching sequence of the first switch S1 and third switch refers on the contrary: within the same period, when described first
In the closure state, the third switch S3 is in an off state by switch S1, when the first switch S1 is in an off state
When, the third switch S3 is in closed state, thus during first switch S1 is disconnected, so that the first switch S1 and institute
The voltage for stating the connecting node VA of third switch S3 is maintained at the voltage value of common-mode voltage input terminal VCM, without randomized jitter.
On the basis of the above embodiments, in one embodiment of the invention, first predeterminated voltage is greater than described
The voltage of common-mode voltage input terminal, i.e. VDD-VREF > VCM, thus disconnected in first switch S1, during third switch S3 is closed,
So that no current flows through in the first field-effect tube of current mirror pipe, and is closed in the first switch S1, third switch S3 is disconnected
Period, the first field-effect tube of current mirror pipe M1 can be opened faster, be flowed through electric current IDAC1, avoid unnecessary delay.
Optionally, on the basis of the above embodiments, in one embodiment of the invention, the third switch S3 is in institute
It states and is closed before first switch S1 is fully disconnected, to reduce the connecting node of the first switch S1 and the third switch S3
The voltage fluctuation of VA.
Similarly, the switching sequence of the second switch S2 and the 4th switch S4 refers on the contrary: within the same period, working as institute
State second switch S2 in the closure state, the 4th switch S4 is in an off state, closes when the second switch S2 is in
When disconnected state, the 4th switch S4 is in closed state, to pass through the 4th switch during second switch S2 is disconnected
S4 is closed so that the voltage of the connecting node VB of the second switch S2 and the 4th switch S4 are maintained at common-mode voltage input
The voltage value for holding VCM, without randomized jitter.
On the basis of the above embodiments, in one embodiment of the invention, second predeterminated voltage is less than described
The voltage of common-mode voltage input terminal, i.e. VREF < VCM, thus disconnected in second switch S2, during the 4th switch S4 is closed, so that
No current flows through in current mirror pipe third field-effect tube, and is closed in the second switch S2, during the 4th switch S4 is disconnected,
Current mirror pipe third field-effect tube M3 can be opened faster, flowed through electric current IDAC2, avoided unnecessary delay.
Optionally, on the basis of the above embodiments, in one embodiment of the invention, the 4th switch S4 is in institute
It states and is closed before second switch S2 is fully disconnected, to reduce the connecting node of the second switch S2 and the 4th switch S4
The voltage fluctuation of VB.
It should be noted that in embodiments of the present invention, the switching sequence phase of the first switch S1 and second switch S2
It can instead be believed by the type and the input of the first input signal PWM_P and second for controlling first switch S1 and second switch S2
Number/phase of PWM_P realizes.
Specifically, the first switch S1 and second switch S2 are that type is identical in one embodiment of the application
Transistor, i.e., when receiving high level or low level signal at the same time, state in which is identical, at this point, first input signal
PWM_P and the second input signal/PWM_P is the square-wave signal of opposite in phase；In another embodiment of the present invention, described
One switch S1 and second switch S2 is different types of transistor, i.e., locating when receiving high level or low level signal at the same time
State on the contrary, at this point, the first input signal PWM_P and the second input signal/PWM_P can be the identical square wave of phase
Signal.The present invention to this and without limitation, specifically depends on the circumstances.
Similarly, in embodiments of the present invention, the switching sequence of the first switch S1 and third switch S3 can lead on the contrary
Cross the type and the first input signal PWM_P and the second input signal/PWM_P of control first switch S1 and third switch S3
Phase realize.
Specifically, the first switch S1 and third switch S3 are that type is identical in one embodiment of the application
Transistor, i.e., when receiving high level or low level signal at the same time, state in which is identical, at this point, first input signal
PWM_P and the second input signal/PWM_P is the square-wave signal of opposite in phase；In another embodiment of the present invention, described
One switch S1 and third switch S3 is different types of transistor, i.e., locating when receiving high level or low level signal at the same time
State on the contrary, at this point, the first input signal PWM_P and the second input signal/PWM_P can be the identical square wave of phase
Signal.The present invention to this and without limitation, specifically depends on the circumstances.
Similarly, the switching sequence of the second switch S2 and the 4th switch S4 on the contrary can by control second switch S2 and
The type of 4th switch S4 and the first input signal PWM_P and the second input signal/PWM_P phase are realized.
Specifically, the second switch S2 and the 4th switch S4 are that type is identical in one embodiment of the application
Transistor, i.e., when receiving high level or low level signal at the same time, state in which is identical, at this point, first input signal
PWM_P and the second input signal/PWM_P is the square-wave signal of opposite in phase；In another embodiment of the present invention, described
Two switch S2 and the 4th switch S4 are different types of transistor, i.e., locating when receiving high level or low level signal at the same time
State on the contrary, at this point, the first input signal PWM_P and the second input signal/PWM_P can be the identical square wave of phase
Signal.The present invention to this and without limitation, specifically depends on the circumstances.
Optionally, in one embodiment of the invention, the first switch S1, second switch S2, third switch S3 and
4th switch S4 is same type of transistor, i.e., the described first switch S1, second switch S2, third switch S3 and the 4th are opened
It is identical to close S4 phase, in embodiments of the present invention, the first input signal PWM_P and the second input signal/PWM_P are phase
Opposite square-wave signal；In another embodiment of the present invention, the first switch S1 and the 4th switch S4 is type
Identical transistor, the second switch S2 and the third switch S3 are the identical transistor of type, the first switch S1
It is different types of transistor with third switch S3, second switch S2 and the 4th switch S4 are different types of transistor, i.e. institute
It is identical as the 4th switch S4 phase to state first switch S1, the second switch S2 is identical with the third switch S3 phase,
The first switch S1 and third switch S3 phase is different, and second switch S2 and the 4th switch S4 phase are different, of the invention real
It applies in example, the first input signal PWM_P and the second input signal/PWM_P are the identical square-wave signal of phase.Optionally,
The first input signal PWM_P is the duty ratio pulsewidth modulation square-wave signal directly proportional to input signal amplitude.
As shown in figure 4, Fig. 4 show digital analog converter provided by the embodiment of the present invention in the first switch and
The schematic equivalent circuit when second switch is closed.As shown in Figure 4, digital simulation provided by the embodiment of the present invention turns
The equivalent output impedance r0_dac of parallel operation are as follows:
R0_dac=(gm_N1*ro3*AV3*gm_N2*ro4*RS2) ∥
(gm_P2*ro2*AV2*gm_P1*ro1*RS1)
Wherein, gm_N1 indicates the mutual conductance of third field-effect tube, and gm_N2 indicates the mutual conductance of the 4th field-effect tube, gm_P1 table
Show the mutual conductance of the first field-effect tube, gm_P2 indicates the mutual conductance of the second field-effect tube, and ro1 indicates the equivalent electricity of the first field-effect tube
Resistance, ro2 indicate that the equivalent resistance of the second field-effect tube, ro3 indicate that the equivalent resistance of third field-effect tube, ro4 indicate the 4th
The equivalent resistance of effect pipe, AV3 indicate the gain of third operational amplifier, and AV2 indicates the gain of third operational amplifier.
From the foregoing, it will be observed that digital analog converter provided by the embodiment of the present invention, when being applied to digital power amplifier system, greatly
The equivalent output impedance for increasing the digital analog converter greatly reduces the power supply rejection ratio of the digital power amplifier system.
Moreover, digital analog converter provided by the embodiment of the present invention not only may be used when being applied to digital power amplifier system
With by the resistance for adjusting first field-effect tube, the second field-effect tube, third field-effect tube and the 4th field-effect tube or across
The equivalent impedance for increasing the digital analog converter is led, it can also be by adjusting the 4th resistance and the 5th resistance
Resistance value increases the equivalent impedance of the digital analog converter, can also be by adjusting the second operational amplifier and described
The gain of third operational amplifier increases the equivalent impedance of the digital analog converter, to further decrease the digital function
The power supply rejection ratio of place system improves the noise signal rejection ability of the digital power amplifier system.
In addition, in embodiments of the present invention, continuing as shown in figure 3, the first switch S1 is located at the voltage input end
Between VDD and the first current source IDAC1, i.e., the first end of the described first current source IDAC1 and first switch S1 electricity
Connection, the second end of the first current source IDAC1 are electrically connected with the second composition branch, and the first switch S1's is another
End is electrically connected with voltage input end VDD, the clock feed-through effect and ditch that first switch S1 can be made to generate in switching process
Road charge injection phenomenon will not cross the first current source IDAC1 load in the output signal of digital analog converter, to keep away
Exempt to inject phenomenon to digital simulation due to the first switch S1 clock feed-through effect generated in switching process and channel charge
The adverse effect of the output signal of converter reduces the output noise of the digital power amplifier system.
Similarly, in embodiments of the present invention, continue as shown in figure 3, the second switch S2 be located at ground terminal GND with it is described
Between second current source IDAC2, i.e., the first end of the described second current source IDAC2 is electrically connected with the second switch S2, described
The second end of second current source IDAC2 is electrically connected with the first composition branch, the other end of the second switch S2 and ground connection
GND electrical connection is held, clock feed-through effect and the channel charge injection that second switch S2 can be made to generate in switching process are existing
As the second current source IDAC2 load will not be crossed in the output signal of digital analog converter, so as to avoid due to second
Output of clock feed-through effect and channel charge the injection phenomenon that switch S2 is generated in switching process to digital analog converter
The adverse effect of signal reduces the output noise of the digital power amplifier system.
Correspondingly, the embodiment of the invention also provides a kind of digital power amplifier subsystem, as shown in figure 5, the digital power amplifier is sub
System includes:
Digital analog converter DAC provided by any of the above-described embodiment, the first operational amplifier AMP1, integrator 31,
PWM comparator 32, driver 33, first resistor RF and first capacitor C1, wherein
The signal output end DAC_VOP of the digital analog converter and the inversion signal of first operational amplifier are defeated
Enter end to be connected, the positive signal input part of first operational amplifier is for receiving common mode voltage signal VCM, first fortune
The signal output end for calculating amplifier is connected with the signal input part of the integrator；
The signal output end of the integrator is connected with the signal input part of the PWM comparator, the PWM comparator
Signal output end is connected with the signal input part of the driver, and the signal output end of the driver is as above-mentioned digital power amplifier
The signal output end VOP of subsystem；
An end of the first resistor RF is connected to the connection of the digital analog converter Yu first operational amplifier
Node, another signal output end for being terminated at the driver of the first resistor RF；
An end of the first capacitor C1 is connected to the connection of first operational amplifier and the digital analog converter
Node, another connecting node for being terminated at first operational amplifier and the integrator of the first capacitor C1.
When specific works, the first input signal PWM_P and second input signal/PWM_P are by digital module
The digital input signals such as I2S, TDM for receiving are converted into after audio effect processing, digital gain amplification, digital filtering
Pwm signal, the pwm signal are handled by digital analog converter DAC, and pass through integrator, PWM comparator, drive module
PWM square wave is exported afterwards, to realize the amplification of analog gain, to greatly improve the digital function of the digital power amplifier subsystem application
The power supply rejection ability of the audio frequency power amplifier of place system.
It is described below with the first input signal PWM_P and second input signal/PWM_P opposite in phase
Between high period, first switch S1 closure, second switch S2 is disconnected PWM_P, when the PWM_P is low level, first switch
S1 is disconnected, and for second switch S2 closure, the working principle of above-mentioned digital power amplifier subsystem is described.
When the first input signal PWM_P be high level when, second input signal/PWM_P be low level, first
Switch S1 closure, second switch S2 are disconnected, and the third switch S3 is disconnected, the 4th switch S4 closure, the second switch
The connecting node VB of S2 and the 4th switch S4 are maintained at the voltage value of common-mode voltage VCM, meanwhile, the digital simulation turns
The first current source IDAC1 in parallel operation is to the anti-of the first resistor RF and first capacitor C1 and the first operational amplifier AMP1
The capacitor board charging of phase output terminal electrical connection, the output end of the first operational amplifier AMP1 is to the first capacitor and first
The capacitor board electric discharge of the output end electrical connection of operational amplifier AMP1, the output voltage AMP_V1 drop of the first operational amplifier AMP1
It is low, and by integrator, PWM comparator and driver, so that the signal that the output end VOP of the digital power amplifier subsystem is exported
For low level；
When the PWM_P is low level, first switch S1 is disconnected, and second switch S2 closure, the third switch S3 is closed
It closes, the 4th switch S4 is disconnected, and the connecting node VA of the first switch S1 and the third switch S3 are maintained at common mode
The voltage value of voltage VCM, meanwhile, the second current source IDAC2 in the digital analog converter to the first resistor RF with
And the capacitor board that first capacitor C1 is electrically connected with the reversed-phase output of the first operational amplifier AMP1 discharges, first fortune
Calculate the capacitor board that the output end of amplifier AMP1 is electrically connected the first capacitor with the output end of the first operational amplifier AMP1
It charging, the output voltage AMP_V1 of the first operational amplifier AMP1 is increased, and passes through integrator, comparator and driver,
So that the signal that the output end VOP of the digital power amplifier subsystem is exported is high level.
From the foregoing, it will be observed that in digital power amplifier subsystem provided by the embodiment of the present invention, the one of the first input signal PWM_P
(including a high level signal and a low level signal), the output signal of the first operational amplifier AMP1 in a period
AMP_V1 is triangular signal, and the signal of the output end VOP output of the sub- power amplification system of number is square-wave signal, is then passed through
After the low-frequency filter characteristics of low-pass filtering or loudspeaker itself, audio signal is restored.
As shown in fig. 6, Fig. 6 shows the first input signal PWM_P, the second input signal/PWM_P, the common mode
The output signal of voltage signal VCM, the output signal DAC_VO of the digital analog converter and the digital power amplifier subsystem
The comparison of wave shape schematic diagram of VOP, from fig. 6 it can be seen that the first input signal PWM_P and the second input signal/PWM_P
It is the input signal of opposite in phase, by loop negative feedback, the signal of the digital analog converter output end DAC_VO
Fluctuation up and down is carried out centered on VCOM, adjusts loop error signal.In addition, due to device each in loop (such as integrator and
Driver etc.) there is delay, the output signal of the digital analog converter and the output signal of digital power amplifier subsystem are opposite
In the first input signal PWM_P and the second input signal/PWM_P response, there are certain delay LD (Loop
Delaytime)。
In addition, since feedback loop gain is very big, the value very little of differential signal (DAC_VO-VCM), so the number
The ripple very little of relatively described common mode voltage signal VCM or more the fluctuation of the signal of analog converter output end DAC_VO output, from
And the signal of the digital analog converter output end DAC_VO output is carried out up and down centered on common mode voltage signal VCM
Small fluctuation, the output stability of the raising digital analog converter of high degree.
Based on any of the above embodiments, in one embodiment of the invention, the common mode voltage signal can be with
For the half of the voltage signal of the digital analog converter received voltage input end VDD input, i.e. VCM=VDD/2,
But the present invention is to this and without limitation, and in other embodiments of the invention, the common mode voltage signal can be the number
One third or a quarter of the voltage signal of the received voltage input end VDD input of analog converter etc., specifically optionally
Depending on.
Based on any of the above embodiments, in one embodiment of the invention, the digital power amplifier subsystem is also
Including common mode voltage signal generation module, to generate the common mode voltage signal VCM.Optionally, in an implementation of the invention
In example, the common mode voltage signal generation module includes concatenated second resistance and 3rd resistor, wherein the second resistance back
One end from the 3rd resistor is electrically connected the voltage input end VDD, and the 3rd resistor deviates from the one of the second resistance
The connecting node of end ground connection, the second resistance and the 3rd resistor is electrically connected the positive input of first operational amplifier
End.But the present invention is to this and without limitation, and in other embodiments of the invention, the common mode voltage signal generation module may be used also
The common mode voltage signal is provided in other ways, specifically depend on the circumstances.
In digital power amplifier subsystem shown in Fig. 5, the first input signal PWM_P or the second input signal/PWM_P to number
The gain of the signal of word power amplifier subsystem final output are as follows: AV=2 × (2 × Din-1) × IDAC × RF, wherein Din first
Input signal PWM_P or the second input signal/PWM_P high level duty ratio, IDAC indicate the first current source IDAC1 or
The current value that second current source IDAC2 is generated, RF indicate the resistance value of the first resistor RF.
In addition, the digital power amplifier system includes the first number the embodiment of the invention also provides a kind of digital power amplifier system
Word power amplifier subsystem and the second digital power amplifier subsystem, wherein the first digital power amplifier subsystem is the channel VOP；Described
Two digital power amplifier subsystems are the channel VON；In the first digital power amplifier subsystem and the second digital power amplifier subsystem extremely
A few digital power amplifier subsystem is using digital power amplifier subsystem provided by any of the above-described embodiment of the present invention.
In conclusion digital analog converter provided by the embodiment of the present invention, the number including the digital analog converter
Word power amplifier subsystem and digital power amplifier system including the digital power amplifier subsystem, considerably increase the digital-to-analogue conversion
The equivalent output impedance of device reduces the power supply rejection ratio of the digital power amplifier system.
Moreover, digital analog converter provided by the embodiment of the present invention, the digital function including the digital analog converter
Subsystem and the digital power amplifier system including the digital power amplifier subsystem are put, it not only can be by adjusting first field-effect
Pipe, the resistance of the second field-effect tube, third field-effect tube and the 4th field-effect tube or mutual conductance increase the digital analog converter
Equivalent impedance, can also pass through and adjust the resistance value of the 4th resistance and the 5th resistance and increase the digital simulation and turn
The equivalent impedance of parallel operation can also be increased by adjusting the gain of the second operational amplifier and the third operational amplifier
The equivalent impedance of the digital analog converter improves to further decrease the power supply rejection ratio of the digital power amplifier system
The noise signal rejection ability of the digital power amplifier system.
Various pieces are described in a progressive manner in this specification, and what each some importance illustrated is and other parts
Difference, same and similar part may refer to each other between various pieces.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to embodiment illustrated herein, and is to fit to consistent with the principles and novel features disclosed in this article
Widest scope.
Claims (9)
1. a kind of digital analog converter characterized by comprising
First composition branch and the second composition branch, wherein the first composition branch first end is connect with voltage input end, the
Two ends are electrically connected with common-mode voltage input terminal, and third end is connect with the second composition branch；The second composition branch first
End is electrically connected with the first composition branch, and second end ground connection, third end is electrically connected with the common-mode voltage input terminal；Described
Signal output end of the connecting node of one composition branch and the second composition branch as the digital analog converter；
The first composition branch includes: concatenated first switch structure and the first current source, and the first switch structure includes
First switch and third switch, one end of the first switch are electrically connected with voltage input end, the other end and first electric current
One end of source electrical connection, the third switch is electrically connected with common-mode voltage input terminal, and the other end is electrically connected with first current source
It connects；First current source includes: the 4th resistance, the first field-effect tube, the second field-effect tube and second operational amplifier,
In,
Described 4th resistance one end is the first end of first current source, is electrically connected with the first switch structure, the other end
It is electrically connected with the first end of the first field-effect tube；
The second end of first field-effect tube is electrically connected with the first end of second field-effect tube, first field-effect tube
Control terminal be electrically connected with the output end of the second operational amplifier；
The inverting input terminal of the second operational amplifier is electrically connected with the first end of first field-effect tube, non-inverting input terminal
It is electrically connected to the first preset potential, first preset potential is equal to the voltage of voltage input end and the difference of reference voltage, defeated
First field-effect tube is biased in working condition for exporting the first bias voltage to first field-effect tube by outlet；
The second end of second field-effect tube is the second end of first current source, is electrically connected with the second composition branch
It connects, the control terminal of second field-effect tube is electrically connected the second bias voltage, and second bias voltage is used for described second
Field-effect tube is biased in working condition；
The second composition branch includes: concatenated second switch structure and the second current source, and the second switch structure includes:
Second switch and the 4th switch, one end of the second switch are electrically connected with ground terminal, the other end and second current source electricity
One end of connection, the 4th switch is electrically connected with the common-mode voltage input terminal, and the other end is electrically connected with second current source
It connects；Second current source includes: the 5th resistance, third field-effect tube, the 4th field-effect tube and third operational amplifier,
In,
Described 5th resistance one end is the first end of second current source, is electrically connected with the second switch structure, the other end
It is electrically connected with the first end of the 4th field-effect tube；
The second end of 4th field-effect tube is electrically connected with the first end of the third field-effect tube, the 4th field-effect tube
Control terminal be electrically connected with the output end of the third operational amplifier；
The inverting input terminal of the third operational amplifier is electrically connected with the first end of the 4th field-effect tube, non-inverting input terminal
It is electrically connected to the second preset potential, second preset potential is equal to the reference voltage, and output end is for exporting the 4th biasing
4th field-effect tube is biased in working condition by voltage；
The second end of the third field-effect tube is the second end of second current source, is electrically connected with the first composition branch
It connects, the control terminal of the third field-effect tube is electrically connected third bias voltage, and the third bias voltage is used for the third
Field-effect tube is biased in working condition；
Wherein, the switching sequence of the first switch and the second switch is on the contrary, the first switch and the third switching sequence
On the contrary, the second switch and the 4th switching sequence are opposite.
2. digital analog converter according to claim 1, which is characterized in that first field-effect tube and described second
Field-effect tube is p-type field-effect tube, and the third field-effect tube and the 4th field-effect tube are N-type field-effect tube.
3. digital analog converter according to claim 1, which is characterized in that the 4th resistance and the 5th resistance
Resistance value it is identical.
4. digital analog converter according to claim 1, which is characterized in that the switch state of the first switch is by
The control of one input signal, the switch state of the second switch are controlled by the second input signal, and the first switch and second is opened
Close the square-wave signal for being the identical transistor of type, first input signal and the second input signal for opposite in phase.
5. digital analog converter according to claim 1, which is characterized in that the switch state of the first switch is by
The control of one input signal, the switch state of the second switch are controlled by the second input signal, and the first switch and second is opened
Closing is different types of transistor, and first input signal and the second input signal are the identical square-wave signal of phase.
6. digital analog converter according to claim 4 or 5, which is characterized in that the switch state of the third switch
It being controlled by second input signal, the switch state of the 4th switch is controlled by first input signal, and described first
Switch and the 4th switch are the identical transistor of type, and the second switch and third switch are the identical crystal of type
Pipe.
7. a kind of digital power amplifier subsystem, which is characterized in that the digital power amplifier subsystem includes:
Digital analog converter provided by claim any one of 1-6, the first operational amplifier, integrator, PWM comparator,
Driver, first resistor and first capacitor, wherein
The signal output end of the digital analog converter is connected with the inversion signal input terminal of first operational amplifier, institute
The positive signal input part of the first operational amplifier is stated for receiving common mode voltage signal, the signal of first operational amplifier
Output end is connected with the signal input part of the integrator；
The signal output end of the integrator is connected with the signal input part of the PWM comparator, the signal of the PWM comparator
Output end is connected with the signal input part of the driver, and the signal output end of the driver is as above-mentioned digital power amplifier subsystem
The signal output end of system；
One end of the first resistor is connected to the connecting node of the digital analog converter Yu first operational amplifier, institute
State another signal output end for being terminated at the driver of first resistor；
One end of the first capacitor is connected to the connecting node of first operational amplifier and the digital analog converter, institute
State another connecting node for being terminated at first operational amplifier and the integrator of first capacitor C1.
8. digital power amplifier subsystem according to claim 7, which is characterized in that the common mode voltage signal can be described
The half of the voltage signal of the received voltage input end input of digital analog converter.
9. a kind of digital power amplifier system, which is characterized in that the digital power amplifier system includes the first digital power amplifier subsystem and the
Two digital power amplifier subsystems, wherein the first digital power amplifier subsystem is the channel VOP；The second digital power amplifier subsystem
For the channel VON；
At least one digital power amplifier subsystem is adopted in the first digital power amplifier subsystem and the second digital power amplifier subsystem
The digital power amplifier subsystem provided by claim 7 or 8.
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| CN201910097381.2A CN109842382A (en) | 2019-01-31 | 2019-01-31 | Digital analog converter, digital power amplifier subsystem, digital power amplifier system |
| PCT/CN2020/072166 WO2020156161A1 (en) | 2019-01-31 | 2020-01-15 | Digital-to-analog converter, digital power amplification subsystem, and digital power amplification system |
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| CN201910097381.2A CN109842382A (en) | 2019-01-31 | 2019-01-31 | Digital analog converter, digital power amplifier subsystem, digital power amplifier system |
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| WO2020156161A1 (en) * | 2019-01-31 | 2020-08-06 | 上海艾为电子技术股份有限公司 | Digital-to-analog converter, digital power amplification subsystem, and digital power amplification system |
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| CN109004936A (en) * | 2018-08-07 | 2018-12-14 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter and digital power amplifier subsystem |
| CN109120269A (en) * | 2018-08-07 | 2019-01-01 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter |
| CN209233795U (en) * | 2019-01-31 | 2019-08-09 | 上海艾为电子技术股份有限公司 | Digital analog converter, digital power amplifier subsystem, digital power amplifier system |
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| CN109004936A (en) * | 2018-08-07 | 2018-12-14 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter and digital power amplifier subsystem |
| CN109120269A (en) * | 2018-08-07 | 2019-01-01 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter |
| CN209233795U (en) * | 2019-01-31 | 2019-08-09 | 上海艾为电子技术股份有限公司 | Digital analog converter, digital power amplifier subsystem, digital power amplifier system |
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| WO2020156161A1 (en) * | 2019-01-31 | 2020-08-06 | 上海艾为电子技术股份有限公司 | Digital-to-analog converter, digital power amplification subsystem, and digital power amplification system |
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Country or region after: China Address after: Room 1201, No.2, Lane 908, Xiuwen Road, Minhang District, Shanghai, 201199 Applicant after: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Address before: 201199 room 1201, building 2, Lane 908, Xiuwen Road, Minhang District, Shanghai Applicant before: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Country or region before: China |