CN109104194A - A kind of digital analog converter and digital power amplifier subsystem - Google Patents
A kind of digital analog converter and digital power amplifier subsystem Download PDFInfo
- Publication number
- CN109104194A CN109104194A CN201810888488.4A CN201810888488A CN109104194A CN 109104194 A CN109104194 A CN 109104194A CN 201810888488 A CN201810888488 A CN 201810888488A CN 109104194 A CN109104194 A CN 109104194A
- Authority
- CN
- China
- Prior art keywords
- switch
- effect tube
- analog converter
- signal
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 76
- 239000003990 capacitor Substances 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 6
- 238000004088 simulation Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 13
- 230000008569 process Effects 0.000 abstract description 10
- 238000002347 injection Methods 0.000 abstract description 7
- 239000007924 injection Substances 0.000 abstract description 7
- 230000002411 adverse Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 9
- 238000012545 processing Methods 0.000 description 5
- 101001116668 Homo sapiens Prefoldin subunit 3 Proteins 0.000 description 4
- 102100024884 Prefoldin subunit 3 Human genes 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000001914 filtration Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 101710170230 Antimicrobial peptide 1 Proteins 0.000 description 2
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005236 sound signal Effects 0.000 description 2
- 101100063435 Caenorhabditis elegans din-1 gene Proteins 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/662—Multiplexed conversion systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/82—Digital/analogue converters with intermediate conversion to time interval
- H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The present invention provides a kind of digital analog converter and digital power amplifier subsystems, wherein, clock feed-through effect and channel charge the injection phenomenon that the first switch and the second switch of digital analog converter generates in switching process will not cross the first current source and the second current source loads in the output signal of digital analog converter, the adverse effect so as to avoid clock feed-through effect and channel charge the injection phenomenon generated in switching process due to first switch and the second switch to the output signal of digital analog converter；So that the size of first switch and the second switch can not be limited, it can solve the problems, such as to consume excessive voltage drop due to first switch and the second switch and the first current source and the second current source are worked in linear zone using the switching tube of larger size as the first switch and the second switch.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, and more specifically, it relates to a kind of digital analog converters
And digital power amplifier subsystem.
Background technique
Digital power amplifier has the characteristics that the small, low noise of distortion, dynamic range be big, strong antijamming capability, in the transparent of sound quality
Degree parses power, and the advantage in terms of quiet, low frequency the shock dynamics of background substantially exceeds traditional analog amplifier and class D
Power amplifier.With DVD home theater, mini audio system, set-top box, PC, LCD TV, flat-panel monitor and mobile electricity
The development with rapid changepl. never-ending changes and improvements of the consumer products such as words, the especially new source of sound specification of some high sample frequencys such as SACD, DVD Audio
Appearance and sound system from stereo to the evolution of multichannel surrounding system, all accelerate the development of digital power amplifier.In number
There is a kind of new noun " pure digi-tal function now with for the user for pursuing the requirement of high-fidelity sound quality in word power domain
Put ", it supports many digital audio-format signal inputs, such as I2S, TDM, can handle, realize abundant by number DSP
Sound effect algorithms have very strong RF anti-interference ability, on mobile phone, have natural advantage, digital signal is in transmission process
Phase retard, phase distortion, intermodulation distortion etc. will not be brought, the benefit of sense of hearing is exactly that sound can be more fully apparent from, position more quasi-, sound
Closer to really.
Two digital power amplifier subsystems are generally included in digital power amplifier system, two digital power amplifier subsystems first are used respectively
In receiving the first input signal and the second input signal, the first input signal and the second input signal by digital module to receiving
The digital input signals such as I2S, TDM convert and obtain after audio effect processing, digital gain amplification, digital filtering；So latter two
Digital power amplifier subsystem carries out digital-to-analogue conversion processing (Digital- to the first input signal and the second input signal respectively
To-Analog Conversion, DAC) analog signal is obtained afterwards, and a series of waveform processings are carried out to the analog signal of acquisition
Afterwards, PWM square-wave signal is obtained, realizes the amplification of analog gain；The square-wave signal of last the two digital power amplifier subsystems output
After the low-frequency filter characteristics of low-pass filtering or loudspeaker itself, audio signal is restored.In this whole process, to first
What input signal and the second input signal carried out digital-to-analogue conversion processing is the digital analog converter of digital power amplifier subsystem.
Digital analog converter in the prior art due to circuit structure limitation so that its switch for receiving input signal
The size of pipe cannot be too big, and the parasitic capacitance otherwise generated between the drain electrode and source electrode of switching tube can become larger, in switching process
Clock feed-through effect and the channel charge injection of generation can increase, and generate bad shadow to the output signal of digital analog converter
It rings, so that the performance to entire digital power amplifier system generates adverse effect；And the clock feedback in order to avoid switching tube in switch
Logical effect, the size of the switching tube of digital analog converter can only design it is smaller so that the resistance of these switching tubes compared with
Greatly, certain voltage drop can be consumed on these switching tubes, when the supply voltage of digital analog converter is lower, can make total
The current source of word analog converter works in linear zone, thus output current value and equivalent output resistance to digital analog converter
Anti- generation adverse effect, finally brings adverse effect to the performance of digital analog converter.
Summary of the invention
In view of this, the present invention provides a kind of digital analog converter and digital power amplifier subsystem, to solve due to number
The size of switching tube in word analog converter can only design smaller, and bring bad shadow to the performance of digital analog converter
Loud problem.
To achieve the above object, the invention provides the following technical scheme:
A kind of digital analog converter is applied in digital power amplifier system, and the digital analog converter includes: first to open
Pass, second switch, the first current source and the second current source, in which:
Signal input part of the first end of the first switch as the digital analog converter, the first switch
Second end is connected with the first end of first current source, and the signal input part is for receiving drive voltage signal；
The second end of first current source is connected with the first end of second current source, first current source and institute
State signal output end of the connecting node of the second current source as the digital analog converter；
The second end of second current source is connected with the first end of the second switch, the second end of the second switch
Ground connection；
The switch state of the first switch is controlled by the first input signal, and the switch state of the second switch is by second
Input signal control, and the switching sequence of the first switch and the second switch is opposite.
Further, first current source includes first resistor, the first field-effect tube and the first operational amplifier；It is described
Second current source includes second resistance, the second field-effect tube and second operational amplifier；Wherein:
The first end of the first resistor is as the first end of first current source and the second end of the first switch
It is connected, the source electrode of first field-effect tube is connected with the second end of the first resistor, the drain electrode of first field-effect tube
It is connected with the source electrode of second field-effect tube, the negative input of first operational amplifier and first field-effect tube
Source electrode be connected, the positive input of first operational amplifier receives the difference of the supply voltage and reference voltage；It is described
First operational amplifier generates the first bias voltage, and the grid of first field-effect tube is defeated with first operational amplifier
Outlet is connected, and the grid of first field-effect tube is for receiving first bias voltage；
The source electrode of second field-effect tube is connected with the first end of the second resistance, the second end of the second resistance
Second end as second current source is connected with the second switch, the negative input of the second operational amplifier with
The source electrode of second field-effect tube is connected, and the positive input of the second operational amplifier receives the reference voltage, institute
It states second operational amplifier and generates the second bias voltage, grid and the second operational amplifier of second field-effect tube
Output end is connected, and the grid of second field-effect tube is for receiving second bias voltage；
The connecting node of the drain electrode of the drain electrode and second field-effect tube of first field-effect tube is as the number
The signal output end of analog converter.
Further, first field-effect tube is p-type field-effect tube.
Further, second field-effect tube is N-type field-effect tube.
Further, the first switch and the second switch are field-effect tube.
Further, the first switch is p-type field-effect tube, and the second switch is N-type field-effect tube.
Further, the first switch is N-type field-effect tube, and the second switch is p-type field-effect tube.
A kind of digital power amplifier subsystem, comprising: digital analog converter as described above, amplifier, integrator, PWM
Comparator, driver, first resistor and first capacitor, wherein
The signal output end of the digital analog converter is connected with the first signal input part of the amplifier, described to put
The second signal input terminal of big device is for receiving common mode voltage signal, the signal output end of the amplifier and the integrator
Signal input part is connected；
The signal output end of the integrator is connected with the signal input part of the PWM comparator, the PWM comparator
Signal output end is connected with the signal input part of the driver, and the signal output end of the driver is as the digital power amplifier
The signal output end of subsystem；
One end of the first resistor is connected to the connecting node of the digital analog converter Yu the amplifier, and described
Another signal output end for being terminated at the driver of one resistance；
One end of the first capacitor is connected to the connecting node of the amplifier Yu the digital analog converter, and described
Another connecting node for being terminated at the amplifier Yu the integrator of one capacitor.
Further, the common mode voltage signal is two points of the received drive voltage signal of the digital analog converter
One of or one third.
It can be seen via above technical scheme that compared with prior art, the invention discloses a kind of digital analog converters
And digital power amplifier subsystem, wherein the first switch of the digital analog converter is located at the first current source far from digital simulation
The signal output end side of converter, the second switch of the digital analog converter are located at the second current source far from digital simulation
The signal output end side of converter, the clock feedthrough effect that so first switch and the second switch generates in switching process
Phenomenon should be injected with channel charge will not cross the first current source and the load of the second current source in the output of digital analog converter
In signal, so as to avoid clock feed-through effect and the channel electricity generated in switching process due to first switch and the second switch
Lotus injects adverse effect of the phenomenon to the output signal of digital analog converter；So that the ruler of first switch and the second switch
It is very little to can not be limited, can using larger size switching tube as the first switch and the second switch, solve due to
First switch and the second switch consumes excessive voltage drop and the first current source and the second current source is worked in linear zone
Problem.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of digital power amplifier system application scenarios signal of digital analog converter provided in an embodiment of the present invention
Figure；
Fig. 2 is a kind of structural schematic diagram of digital analog converter provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another digital analog converter provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of the digital power amplifier subsystem in the channel VOP provided in an embodiment of the present invention；
Fig. 5 is the waveform time diagram of the first input signal provided in an embodiment of the present invention and the second input signal；
Fig. 6 is the first input signal provided in an embodiment of the present invention, the second input signal, common mode voltage signal, digital mould
The waveform time diagram of the output signal of the output signal and digital power amplifier subsystem of quasi- converter；
Fig. 7 is the wave of the output signal of amplifier provided in an embodiment of the present invention, integrator, PWM comparator and driver
Shape time diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
With reference to Fig. 1, Fig. 1 is a kind of digital power amplifier system applied field of digital analog converter provided in an embodiment of the present invention
Scape schematic diagram, by digital module, treated that pwm signal is converted into analog signal for effect, logical including VOP and VON two
Road is illustrated by taking the digital power amplifier subsystem in the channel VOP as an example below.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
As shown in Fig. 2, it is applied to digital power amplifier subsystem the embodiment of the invention provides a kind of digital analog converter,
Above-mentioned digital analog converter includes: first switch S1, second switch S2, the first current source IDAC1 and the second current source
IDAC2, wherein
Signal input part of the first end of above-mentioned first switch S1 as above-mentioned digital analog converter, above-mentioned first switch
Second end be connected with the first end of above-mentioned first current source, above-mentioned signal input part is for receiving drive voltage signal VDD.
The second end of above-mentioned first current source IDAC1 is connected with the first end of above-mentioned second current source IDAC2, and above-mentioned first
Signal output end of the connecting node of current source IDAC1 and above-mentioned second current source IDAC2 as above-mentioned digital analog converter
DAC_VO。
The second end of above-mentioned second current source IDAC2 is connected with the first end of above-mentioned second switch S2, above-mentioned second switch
The second end of S2 is grounded GND.
The switch state of above-mentioned first switch S1 is controlled by the first input signal PWM_P, the switch of above-mentioned second switch S2
State is controlled by the second input signal/PWM_P, and the switching sequence of above-mentioned first switch S1 and above-mentioned second switch S2 are opposite.
In the present embodiment, above-mentioned first input signal PWM_P and the second input signal/PWM_P control above-mentioned first are opened
Close the switch state of S1 and above-mentioned second switch S2.Above-mentioned first input signal PWM_P and the second input signal/PWM_P are by counting
Digital module in word power amplification system puts the digital input signals such as I2S, the TDM received by audio effect processing, digital gain
It is obtained after big and digital filtering, usually pwm signal, i.e. square-wave signal.
In Fig. 2, DAV_VO indicates the signal of above-mentioned digital analog converter output.
The switching sequence of above-mentioned first switch S1 and second switch S2 refers on the contrary, within the same period, when above-mentioned
In the open state, above-mentioned second switch S2 is in an off state by one switch S1；When above-mentioned first switch S1 is off shape
When state, above-mentioned second switch S2 is in the open state.The first current source IDAC1 or the second current source IDAC2 is enabled in this way
The image current of generation is exported as output signal.
In the present embodiment, the first switch S1 of above-mentioned digital analog converter is located at the first current source IDAC1 far from number
The second switch S2 of the signal output end side of word analog converter, above-mentioned digital analog converter is located at the second current source
Signal output end side of the IDAC2 far from digital analog converter, so first switch S1 and second switch S2 are being switched
Clock feed-through effect and channel charge the injection phenomenon generated in the process will not cross the first current source IDAC1 and the second current source
IDAC2 is loaded in the output signal of digital analog converter, is existed so as to avoid due to first switch S1 and second switch S2
Clock feed-through effect and channel charge the injection phenomenon generated in switching process to the output signal of digital analog converter not
Good influence；So that the size of first switch S1 and second switch S2 can not be limited, it can opening using larger size
Pipe is closed as above-mentioned first switch S1 and second switch S2, is solved since first switch S1 and second switch S2 is consumed excessively
Voltage drop and the first current source IDAC1 and the second current source IDAC2 are worked the linear zone the problem of.
The switching sequence of above-mentioned first switch S1 and second switch S2 on the contrary can be by controlling first switch S1 and second
The type of switch S2 and the first input signal PWM_P and the second input signal/PWM_P phase are realized.Specifically, exist
In one embodiment of the application, above-mentioned first switch and above-mentioned second switch are field-effect tube.
In the present embodiment, above-mentioned first switch S1 and second switch S2 be different types of transistor, i.e., above-mentioned first
Switch is p-type field-effect tube, and above-mentioned second switch is N-type field-effect tube；Above-mentioned first switch is N-type field-effect tube, above-mentioned the
Two switches are p-type field-effect tube.High level is received at the same time or when low level signal, state in which is above-mentioned also on the contrary, therefore
First input signal PWM_P and the second input signal/PWM_P can be the identical square-wave signal of phase.
In addition, above-mentioned first switch S1 and second switch S2 can also be P in the alternative embodiment of the application
Type field-effect tube is N-type field-effect tube；Above-mentioned first input signal PWM_P and above-mentioned second input signal/PWM_P is phase
The opposite square-wave signal in position.
In the present embodiment, above-mentioned first switch S1 and second switch S2 is the identical field-effect tube of type, is connect at the same time
When receiving high level or low level signal, state in which is identical, at this point, received first input signal of above-mentioned first switch S1
PWM_P and above-mentioned received second input signal of second switch S2/PWM_P need the square-wave signal for opposite in phase, to guarantee
The switching sequence of above-mentioned first switch S1 and second switch S2 is opposite.
On the basis of the above embodiments, the specific embodiment of the application provides a kind of specific first current source
The embodiment of IDAC1 and the second current source IDAC2, as shown in figure 3,
Above-mentioned first current source IDAC1 includes first resistor RS1, the first field-effect tube MP1 and the first operational amplifier
AMP1, above-mentioned second current source IDAC2 include second resistance RS2, the second field-effect tube MN1 and second operational amplifier AMP2,
Wherein:
First end and above-mentioned first switch of the first end of above-mentioned first resistor RS1 as above-mentioned first current source IDAC1
The second end of S1 is connected, and the source electrode of above-mentioned first field-effect tube MP1 is connected with the second end of above-mentioned first resistor RS1, and above-mentioned the
The drain electrode of one field-effect tube MP1 is connected with the source electrode of above-mentioned second field-effect tube MN1, above-mentioned first operational amplifier IDAC1's
Negative input (-) is connected with the source electrode of above-mentioned first field-effect tube MP1, and the forward direction of above-mentioned first operational amplifier IDAC1 is defeated
Enter the difference that end (+) receives above-mentioned supply voltage VDD and reference voltage VREF；Above-mentioned first operational amplifier IDAC1 generates first
Bias voltage VBP1, the grid of above-mentioned first field-effect tube MP1 are connected with the output end of above-mentioned first operational amplifier IDAC1,
The grid of above-mentioned first field-effect tube MP1 is for receiving above-mentioned first bias voltage VBP1.
The source electrode of above-mentioned second field-effect tube MN1 is connected with the first end of above-mentioned second resistance, and the of above-mentioned second resistance
Two ends are connected as the second end of above-mentioned second current source IDAC2 with above-mentioned second switch S2, above-mentioned second operational amplifier
The negative input (-) of IDAC2 is connected with the source electrode of above-mentioned second field-effect tube MN1, above-mentioned second operational amplifier IDAC2's
Positive input meets (+) and receives said reference voltage VREF, and above-mentioned second operational amplifier IDAC2 generates the second bias voltage
The grid of VBN1, above-mentioned second field-effect tube MN1 are connected with the output end of above-mentioned second operational amplifier IDAC2, and above-mentioned second
The grid of field-effect tube MN1 is for receiving above-mentioned second bias voltage VBN1.
The connecting node of the drain electrode of the drain electrode and above-mentioned second field-effect tube MN1 of above-mentioned first field-effect tube MP1 is as upper
State the signal output end DAC_VO of digital analog converter.
Wherein, above-mentioned first bias voltage VBP1 is used to the first field-effect tube MP1 being biased in working condition, and above-mentioned second
Bias voltage VBN1 is used to the second field-effect tube MN1 being biased in working condition.
It should be noted that first resistor RS1 is identical with second resistance RS2, so that two-way IDAC electric current is equal up and down.The
One switch S1 and second switch S2 are controlled by PWM_P, opposite in phase, i.e. first switch S1 and the one of switch of second switch S2
Another is disconnected when closure.By operational amplifier as current generating circuit, the bias voltage VBP1 and VBN1 of generation divide
Not Gei the first field-effect tube MP1 and the second field-effect tube MN1 grid provide voltage, formed mirror current source IDAC.First puts
Big device AMP1, the first field-effect tube MP1 and first resistor RS1 form source negative feedback, generate electric current；Second amplifier AMP2,
Second field-effect tube MN1 and second resistance RS2 forms source negative feedback, generates electric current.The electric current that first field-effect tube MP1 is generated
The current source IDAC that source IDAC and the second field-effect tube MN1 is generated should guarantee as far as possible under technique change and different temperatures almost
It is equal, to guarantee that, when PWM_P is 50% duty ratio, output VOP is also 50% duty ratio, so that OP output DC voltage is
VDD/2, current value are as follows:Wherein, RS1,2 refer to the resistance of first resistor RS1 or second resistance RS2,
And RS1=RS2.
The embodiment of the invention also provides a kind of digital power amplifier subsystems, as shown in Figure 4, comprising:
Such as the above-mentioned digital analog converter 10 of above-mentioned any embodiment, AMP amplifier 20, integrator 30, PWM comparator
40, driver 50, first resistor RF and first capacitor C1, wherein
The signal output end of above-mentioned digital analog converter 10 is connected with the first signal input part of above-mentioned amplifier 20, on
The second signal input terminal of amplifier 20 is stated for receiving common mode voltage signal, the signal output end of above-mentioned amplifier 20 with it is above-mentioned
The signal input part of integrator 30 is connected；
The signal output end of above-mentioned integrator 30 is connected with the signal input part of above-mentioned PWM comparator 40, and above-mentioned PWM compares
The signal output end of device 40 is connected with the signal input part of above-mentioned driver 50, and the signal output end of above-mentioned driver 50 is as upper
State the signal output end of digital power amplifier subsystem；
An end of above-mentioned first resistor RF is connected to the connecting node of above-mentioned digital analog converter 10 and above-mentioned amplifier 20,
Another signal output end for being terminated at above-mentioned driver 50 of above-mentioned first resistor RF；
An end of above-mentioned first capacitor C1 is connected to the connecting node of above-mentioned amplifier 20 and above-mentioned digital analog converter 10,
Another connecting node for being terminated at above-mentioned amplifier 20 and above-mentioned integrator 30 of above-mentioned first capacitor C1.
In Fig. 4, VCM indicates that above-mentioned common mode voltage signal, AMP_V1 indicate the output signal of above-mentioned amplifier, VOP table
Show the output signal of above-mentioned digital power amplifier subsystem.
In embodiments of the present invention, the first input signal PWM_P and the second input signal/PWM_P phase phase are designed as
Instead, above-mentioned first input signal PWM_P and the second input signal/PWM_P waveform diagram refer to Fig. 5, and above-mentioned first
When input signal PWM_P is in high level, above-mentioned first switch S1 is opened, and above-mentioned second input signal/PWM_P is in low at this time
Level, above-mentioned second switch S2 shutdown；When above-mentioned first input signal PWM_P is in low level, above-mentioned first switch S1 is closed
Disconnected, the second input signal/PWM_P is in high level at this time, and above-mentioned second switch S2 is opened.
Above-mentioned first input signal PWM_P, the second input signal/PWM_P, common mode voltage signal, above-mentioned digital simulation turn
The comparison of wave shape schematic diagram of the output signal of the output signal and digital power amplifier subsystem of parallel operation 10 refers to Fig. 6, in Fig. 6, VCM table
Show that the waveform of above-mentioned common mode voltage signal, DAC_VO indicate the waveform of the output signal of above-mentioned digital analog converter 10, VOP table
Show the waveform of the output signal of above-mentioned digital power amplifier subsystem；From fig. 6 it can be seen that intrinsic due to device each in loop
There is certain consolidate in the output signal of above-mentioned digital analog converter 10 and the output signal of digital power amplifier subsystem in delay
There is delay LD (Loop Delaytime).
When above-mentioned first switch S1 is opened, and above-mentioned second switch S2 is turned off, the first current source IDAC1 output at this time first
Electric current charges to first resistor RF and first capacitor C1, and amplifier 20 discharges to first capacitor C1, the output of amplifier 20
It holds voltage to reduce, is low level by the signal that integrator 30, PWM comparator 40 and driver 50 export.It opens when above-mentioned first
S1 shutdown is closed, when above-mentioned second switch S2 is opened, the second current source IDAC2 exports the second electric current to first resistor RF and the at this time
One capacitor C1 discharges, and amplifier 20 charges to first capacitor C1, and the output end voltage of amplifier 20 increases, and passes through integrator
30, the signal that PWM comparator 40 and driver 50 export is high level.In a cycle of the first input signal PWM_P, put
The waveform that big device 20, integrator 30, PWM comparator 40 and driver 50 respectively export is with reference to Fig. 7, in Fig. 7, sine wave AMP_
V0 indicates that the waveform that above-mentioned amplifier 20 exports, triangular wave AMP_V1 indicate the waveform that above-mentioned integrator 30 exports, square-wave signal
PWMQ indicates that the waveform that above-mentioned PWM comparator 40 exports, square wave VOP indicate the signal that above-mentioned driver 50 exports；From Fig. 5 and figure
As can be seen that the signal that amplifier 20 exports forms triangular wave in 7.The signal that driver 50 exports is square wave, and driver 50
The driving capability of the square-wave signal of output is better than the driving capability of the square-wave signal of the output of PWM comparator 40.Driver 50 is defeated
Signal out restores audio signal after the low-frequency filter characteristics of low-pass filtering or loudspeaker itself.
In above-mentioned digital power amplifier subsystem, above-mentioned common mode voltage signal can receive for above-mentioned digital analog converter 10
Drive voltage signal VDD half or one third, as long as guaranteeing in the received drive of above-mentioned digital analog converter 10
The first transistor MP1 in the variation range of dynamic voltage signal VDD as the first current source IDAC1 does not enter linear zone.
Since feedback loop gain is very big, the value of differential signal (DAC_VO-VCM) will very little, so DAC_VO is with respect to VCM or more
The ripple very little of fluctuation, thus digital analog converter 10 export signal DAC_VO centered on common mode voltage signal VCM into
Small fluctuation above and below row, the power supply that the non-linear distortion of digital power amplifier subsystem can improve digital power amplifier subsystem inhibit energy
Power.
In digital power amplifier subsystem shown in Fig. 4, the first input signal PWM_P or the second input signal/PWM_P to number
The gain of the signal of word power amplifier subsystem final output are as follows:
A V=2* (2*Din-1) * ID A C*RF
Wherein, Din indicates the first input signal PWM_P or the second input signal/PWM_P high level duty ratio, IDAC
Indicate that the current value that above-mentioned first current source IDAC1 or the second current source IDAC2 is generated, RF indicate the electricity of above-mentioned first resistor RF
Resistance value.
To sum up above-mentioned, the embodiment of the present application provides a kind of digital analog converter and digital power amplifier subsystem, wherein on
The first switch S1 for stating digital analog converter is located at the first signal output end of the current source IDAC1 far from digital analog converter
The second switch S2 of side, above-mentioned digital analog converter is located at the second letter of the current source IDAC2 far from digital analog converter
Number output end side, the clock feed-through effect and ditch that so first switch S1 and second switch S2 are generated in switching process
Road charge injection phenomenon will not cross the first current source IDAC1 and the second current source IDAC2 load in digital analog converter
In output signal, so as to avoid the clock feed-through effect generated in switching process due to first switch S1 and second switch S2
Adverse effect with channel charge injection phenomenon to the output signal of digital analog converter；So that first switch S1 and
The size of two switch S2 can not be limited, and can be opened using the switching tube of larger size as above-mentioned first switch S1 and second
Close S2, solve due to first switch S1 and second switch S2 consumes excessive voltage drop and make the first current source IDAC1 and
Second current source IDAC2 work is the linear zone the problem of.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
Circuit and method proposed by the invention are exemplarily described in conjunction with attached drawing above, above embodiments are said
It is bright to be merely used to help understand the core idea of the present invention.For those of ordinary skill in the art, according to the thought of the present invention,
There will be changes in the specific implementation manner and application range, the hybrid power system for having motor to participate in driving such as front-rear axle
System etc..In conclusion the contents of this specification are not to be construed as limiting the invention.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (9)
1. a kind of digital analog converter is applied in digital power amplifier system, which is characterized in that the digital analog converter packet
It includes: first switch, second switch, the first current source and the second current source, in which:
Signal input part of the first end of the first switch as the digital analog converter, the second of the first switch
End is connected with the first end of first current source, and the signal input part is for receiving drive voltage signal；
The second end of first current source is connected with the first end of second current source, first current source and described
Signal output end of the connecting node of two current sources as the digital analog converter；
The second end of second current source is connected with the first end of the second switch, the second termination of the second switch
Ground；
The switch state of the first switch is controlled by the first input signal, and the switch state of the second switch is by the second input
Signal control, and the switching sequence of the first switch and the second switch is opposite.
2. digital analog converter according to claim 1, which is characterized in that first current source includes the first electricity
Resistance, the first field-effect tube and the first operational amplifier；Second current source includes second resistance, the second field-effect tube and second
Operational amplifier；Wherein:
The first end of the first resistor is connected as the first end of first current source with the second end of the first switch,
The source electrode of first field-effect tube is connected with the second end of the first resistor, the drain electrode of first field-effect tube with it is described
The source electrode of second field-effect tube is connected, the source electrode of the negative input of first operational amplifier and first field-effect tube
It is connected, the positive input of first operational amplifier receives the difference of the supply voltage and reference voltage；First fortune
It calculates amplifier and generates the first bias voltage, the output end phase of the grid of first field-effect tube and first operational amplifier
Even, the grid of first field-effect tube is for receiving first bias voltage；
The source electrode of second field-effect tube is connected with the first end of the second resistance, the second end conduct of the second resistance
The second end of second current source is connected with the second switch, the negative input of the second operational amplifier with it is described
The source electrode of second field-effect tube is connected, and the positive input of the second operational amplifier receives the reference voltage, and described the
Two operational amplifiers generate the second bias voltage, the grid of second field-effect tube and the output of the second operational amplifier
End is connected, and the grid of second field-effect tube is for receiving second bias voltage；
The connecting node of the drain electrode of the drain electrode and second field-effect tube of first field-effect tube is as the digital simulation
The signal output end of converter.
3. digital analog converter according to claim 2, which is characterized in that first field-effect tube is p-type field effect
Ying Guan.
4. digital analog converter according to claim 2, which is characterized in that second field-effect tube is N-type field effect
Ying Guan.
5. digital analog converter according to claim 1, which is characterized in that the first switch and the second switch
For field-effect tube.
6. digital analog converter according to claim 5, which is characterized in that the first switch is p-type field-effect tube,
The second switch is N-type field-effect tube.
7. digital analog converter according to claim 5, which is characterized in that the first switch is N-type field-effect tube,
The second switch is p-type field-effect tube.
8. a kind of digital power amplifier subsystem characterized by comprising as the described in any item digital simulations of claim 1-7 turn
Parallel operation, amplifier, integrator, PWM comparator, driver, first resistor and first capacitor, wherein
The signal output end of the digital analog converter is connected with the first signal input part of the amplifier, the amplifier
Second signal input terminal for receiving common mode voltage signal, the signal of the signal output end of the amplifier and the integrator
Input terminal is connected；
The signal output end of the integrator is connected with the signal input part of the PWM comparator, the signal of the PWM comparator
Output end is connected with the signal input part of the driver, and the signal output end of the driver is as the digital power amplifier subsystem
The signal output end of system；
One end of the first resistor is connected to the connecting node of the digital analog converter Yu the amplifier, first electricity
Another signal output end for being terminated at the driver of resistance；
One end of the first capacitor is connected to the connecting node of the amplifier Yu the digital analog converter, first electricity
Another connecting node for being terminated at the amplifier Yu the integrator held.
9. digital power amplifier subsystem according to claim 8, which is characterized in that the common mode voltage signal is the number
The half or one third of the received drive voltage signal of analog converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810888488.4A CN109104194A (en) | 2018-08-07 | 2018-08-07 | A kind of digital analog converter and digital power amplifier subsystem |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810888488.4A CN109104194A (en) | 2018-08-07 | 2018-08-07 | A kind of digital analog converter and digital power amplifier subsystem |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109104194A true CN109104194A (en) | 2018-12-28 |
Family
ID=64848941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810888488.4A Pending CN109104194A (en) | 2018-08-07 | 2018-08-07 | A kind of digital analog converter and digital power amplifier subsystem |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109104194A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842381A (en) * | 2019-01-31 | 2019-06-04 | 上海艾为电子技术股份有限公司 | Digital analog converter, digital power amplifier subsystem, digital power amplifier system |
| TWI755300B (en) * | 2021-03-15 | 2022-02-11 | 立錡科技股份有限公司 | Class-d amplifying system and class-d amplifier circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07231228A (en) * | 1994-02-16 | 1995-08-29 | Hitachi Ltd | Semiconductor integrated circuit device |
| CN101179275A (en) * | 2006-11-07 | 2008-05-14 | 三星电子株式会社 | Continuous time delta-sigma modulator and electronic circuit including the same |
| US8723566B1 (en) * | 2012-11-28 | 2014-05-13 | Cadence Ams Design India Private Limited | Correcting for offset-errors in a PLL/DLL |
| CN104199501A (en) * | 2014-08-25 | 2014-12-10 | 长沙瑞达星微电子有限公司 | High-output impedance current source circuit |
| CN106656065A (en) * | 2016-11-16 | 2017-05-10 | 上海艾为电子技术股份有限公司 | Audio power amplifier and audio device |
| CN208539885U (en) * | 2018-08-07 | 2019-02-22 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter and digital power amplifier subsystem |
-
2018
- 2018-08-07 CN CN201810888488.4A patent/CN109104194A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07231228A (en) * | 1994-02-16 | 1995-08-29 | Hitachi Ltd | Semiconductor integrated circuit device |
| CN101179275A (en) * | 2006-11-07 | 2008-05-14 | 三星电子株式会社 | Continuous time delta-sigma modulator and electronic circuit including the same |
| US8723566B1 (en) * | 2012-11-28 | 2014-05-13 | Cadence Ams Design India Private Limited | Correcting for offset-errors in a PLL/DLL |
| CN104199501A (en) * | 2014-08-25 | 2014-12-10 | 长沙瑞达星微电子有限公司 | High-output impedance current source circuit |
| CN106656065A (en) * | 2016-11-16 | 2017-05-10 | 上海艾为电子技术股份有限公司 | Audio power amplifier and audio device |
| CN208539885U (en) * | 2018-08-07 | 2019-02-22 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter and digital power amplifier subsystem |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842381A (en) * | 2019-01-31 | 2019-06-04 | 上海艾为电子技术股份有限公司 | Digital analog converter, digital power amplifier subsystem, digital power amplifier system |
| TWI755300B (en) * | 2021-03-15 | 2022-02-11 | 立錡科技股份有限公司 | Class-d amplifying system and class-d amplifier circuit |
| US11870400B2 (en) | 2021-03-15 | 2024-01-09 | Richtek Technology Corporation | Class-D amplifying system and class-D amplifier circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109004936A (en) | A kind of digital analog converter and digital power amplifier subsystem | |
| CN101847968B (en) | High-performance D type audio power amplifier with high-order multipath feedback structure | |
| CN209233795U (en) | Digital analog converter, digital power amplifier subsystem, digital power amplifier system | |
| WO2014113369A1 (en) | Telescopic op-amp with slew rate control | |
| CN101557202B (en) | High power D-type power amplifier | |
| WO2020081220A1 (en) | Chopped triangular wave pwm quantizer and pwm modulator having quantizer with controllable analog gain and calibratable for multi-non-ideal gain-affecting characteristics | |
| CN109104194A (en) | A kind of digital analog converter and digital power amplifier subsystem | |
| US20170272043A1 (en) | Generation of voltage reference signals in a hybrid switched mode amplifier | |
| CN108649959B (en) | Digital-analog converter and digital power amplifier subsystem | |
| CN109120269B (en) | Digital-analog converter | |
| CN208539885U (en) | A kind of digital analog converter and digital power amplifier subsystem | |
| CN109672413A (en) | Digital analog converter, digital power amplifier subsystem, digital power amplifier system | |
| CN209627327U (en) | Digital analog converter, digital power amplifier subsystem, digital power amplifier system | |
| CN101483408A (en) | Passive frequency mixer | |
| CN209571993U (en) | Digital analog converter, digital power amplifier subsystem, digital power amplifier system | |
| CN208433953U (en) | A kind of digital analog converter and digital power amplifier subsystem | |
| CN108718198A (en) | A kind of digital analog converter | |
| CN208433952U (en) | A kind of digital analog converter and digital power amplifier subsystem | |
| CN109150188B (en) | A kind of current mode digital-to-analog converter output-stage circuit of adjustable output common mode level | |
| WO2020156161A9 (en) | Digital-to-analog converter, digital power amplification subsystem, and digital power amplification system | |
| CN208539884U (en) | A kind of digital analog converter and digital power amplifier subsystem | |
| CN208433954U (en) | A kind of digital analog converter | |
| CN208539886U (en) | A kind of digital analog converter | |
| CN109104196A (en) | A kind of digital analog converter and digital power amplifier subsystem | |
| CN111404497B (en) | Digital audio power amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: Room 1201, No.2, Lane 908, Xiuwen Road, Minhang District, Shanghai, 201199 Applicant after: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Address before: Room 303-39, building 33, 680 Guiping Road, Xuhui District, Shanghai 200233 Applicant before: SHANGHAI AWINIC TECHNOLOGY Co.,Ltd. Country or region before: China |