JP2008017358A - Class d amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a class-D amplifier capable of correcting offset voltage caused by the difference in the resistance value constituting the class-D amplifier. <P>SOLUTION: The class-D amplifier comprises an input means for inputting an input signal; an integration means that comprises a differential operational amplifier, having an offset voltage correction functions and integrates the input signal inputted via the input means; a modulation means for generating a pulse signal, where a result integrated by the integration means is subjected to pulse width modulation and the integrated result is reflected on pulse width; an output means for outputting the pulse signal; a feedback means for making the output signal of the output means superimpose on the input signal for feeding back to the integration means; an input control means for setting the input means to be a signal absence input state; and an output control means for setting the voltage of the output signal of the output means to voltage to be fed back by the feedback means in the signal absense input state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a circuit technique for correcting an offset voltage of a class D amplifier.

Conventionally, a class D amplifier that converts an analog signal such as a music signal into a pulse signal and amplifies the power is known.
FIG. 8 shows an example of a conventional class D amplifier. In this example, analog input signals AIN (+) and AIN (−) having opposite polarities are applied to the input terminals INP and INM from an external signal source, and the analog input signals AIN (+) and AIN (−) are applied. Is input to the input terminals T11 and T12 of the class D amplifier via capacitors Cin1 and Cin2. The signal input to the class D amplifier is input to the input stage amplifier circuit 100 and amplified, and then input to the integration circuit 110. A pulse width modulation (PWM) circuit 120 performs pulse width modulation on the output signal of the integration circuit 110.

  The output buffer 1300 outputs complementary pulse signals OUTP and OUTM based on the output signal of the pulse width modulation circuit 120. The pulse signals OUTP and OUTM are fed back to the input side of the differential operational amplifier 114 constituting the integrating circuit 110 via the feedback resistors R41 and R42, thereby correcting the waveform distortion of the pulse signal. The pulse signals OUTP and OUTM are output to the outside via the output terminals T21 and T22, and become analog signals that drive the speaker SP through a low-pass filter including the inductors L1 and L2 and the capacitor C.

By the way, in general, in an amplifier for audio, a pop sound is generated due to an offset voltage of a circuit. Similarly, in the above-described class D amplifier, since the transistors constituting the differential operational amplifiers 101 and 114 have an offset voltage due to manufacturing process variations and the like, the voltage of the output pulse signal OUTP even when there is no signal input. And the average value of the voltage of OUTM are different from each other. That is, an offset voltage is output.
In this case, since the offset voltage is always applied to the speaker, a pop sound is generated from the speaker when muting or when the power is turned off.

Therefore, as a conventional technique for correcting the offset voltage of the differential operational amplifier as described above, an offset voltage correction circuit for correcting the offset voltage by injecting a current into one side of the differential pair of transistors constituting the differential operational amplifier. Is known (see Patent Document 1).
In this prior art, an input equivalent offset voltage corresponding to the amount of current is obtained by flowing a current ios into one side of a MOS transistor constituting a differential pair. Therefore, even when the differential operational amplifier has an offset voltage, the offset voltage can be corrected by adjusting the current ios.
JP-A-8-256025

Incidentally, in the class D amplifier shown in FIG. 8 (however, the differential operational amplifiers 101 and 114 do not include the above-described offset correction circuit according to the prior art), the power supply voltage of the output buffer 1300 is the integration circuit 110 and the input. The power supply voltage of the stage amplifier circuit 100 may be different. For example, consider the case where the former is 15V and the latter is 3.3V.
In this case, rectangular pulses with a duty ratio of 50% are complementarily output as output pulse signals OUTP and OUTM when no signal is input. Since the power supply voltage of the output buffer 1300 is 15 V, there is no offset voltage in the differential operational amplifiers 101 and 114, and the resistance between the positive phase side (R31) and the negative phase side (R32) of the input resistance of the integrator 110 Under ideal conditions where the values are equal and the resistance values on the positive phase side (R41) and the negative phase side (R42) of the feedback resistor are equal, the average voltage of the output pulse signals OUTP and OUTM is 7.5V. Therefore, the voltage difference applied between the input terminals of the speaker SP is 0 V, and no sound is generated.

  On the other hand, since the average voltage of each of the output signals SA and SB of the differential operational amplifier 101 whose power supply voltage is 3.3 V is common-mode feedback so as to match the reference voltage which is a half of the power supply voltage. 1.65V. Therefore, the voltage difference of 5.85 V between the average value of the output pulse signals OUTP and OUTM and the average value of the output signals SA and SB is the feedback resistor R41, the input resistor R31 of the integrator 110, the feedback resistor R42, and the integrator 110. To the input resistance R32. As a result, a current corresponding to the sum of the resistance values of the feedback resistor R41 and the input resistor R31 and the sum of the resistance values of the feedback resistor R42 and the input resistor R32 flows from the output portion of the output buffer 1300 to the output portion of the differential operational amplifier 101. Flowing.

  Here, a case is considered in which there is a difference in resistance value due to variations or the like in the feedback resistors R41 and R42. The voltages at the two inputs of the differential operational amplifier 114 are equal because of feedback. Since the differential operational amplifier 114 functions so that the voltage applied to both ends of the input resistor R31 is equal to the voltage applied to both ends of the input resistor R32, the currents flowing through the resistors become equal.

  Since the currents having the same values flow through the feedback resistors R41 and R42, respectively, the voltage drop of the feedback resistors R41 and R42 is applied to the output portion of the output buffer 1300 even when the values of the input resistors R31 and R32 are equal. The difference occurs. Accordingly, an offset voltage corresponding to the difference between the resistance values of the feedback resistors R41 and R42 is generated in the output pulse signals OUTP and OUTM.

Further, the offset voltages (difference potentials) generated in the signals SA and SB by the differential operational amplifier 101 are input resistors R31 and R32, feedback resistors R41 and R42, an integrator 110, a pulse width modulation circuit 120, and an output. The amplification factor (R41 / R31) of the negative feedback amplifier formed by the buffer 1300 is multiplied and appears at the output terminals T21 and T22. For example, when the resistance values R31: R41 are 1:20, the offset voltage generated in the signals SA and SB is multiplied by 20 and output. When there is a difference between the resistance values of the feedback resistors R41 and R42, the amplification factor is also different between the positive phase side and the negative phase side, and the offset voltage is further increased.
The offset voltage also occurs when there is a difference in resistance value between the input resistors R31 and R32.

  That is, if the amplification factor (R41 / R31) on the positive phase side and the amplification factor (R42 / R32) on the negative phase side of the negative feedback amplifier constituting the class D amplifier differ due to variations in resistance value, the output offset voltage As a result, the speaker SP is driven by the offset voltage, which causes a pop sound when the power is turned off or muted.

  However, the offset voltage of the differential operational amplifier itself can be corrected even if the offset voltage correction circuit according to the above-described prior art is used to eliminate the above offset voltage, but the input resistance value or feedback resistance value of the class D amplifier However, there is a problem that the offset voltage generated when the positive phase side and the negative phase side are different cannot be corrected.

  The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a class D amplifier capable of correcting an offset voltage caused by a difference in resistance value constituting the class D amplifier.

  The present invention has been made to solve the above problems, and a class D amplifier according to the present invention includes an input means (input stage amplifier 100) for inputting an input signal and a differential operation having an offset voltage correction function. An integration unit (integration circuit 110) comprising an amplifier (111) for integrating an input signal input via the input unit, and integrating the result of integration by the pulse width, and the integration result is reflected in the pulse width. Modulation means (pulse width modulation circuit 120) for generating the pulse signal, output means (drive circuit 130) for outputting the pulse signal, and integrating means by superimposing the output signal of the output means on the input signal Feedback means (for example, feedback resistors R41 and R42) for feedback to the input, input control means (for example, switches SWOS1 and SWOS2) for setting the input means to a no-signal input state, Output control means for setting the voltage of the output signal of the output means to the voltage to be fed back by the feedback means in the non-signal input state (for example, switches SWOUT1, SWOUT2, offset voltage correcting DC voltage source 160, output buffer 131, 132 output impedance control means).

  In the class D amplifier, the output control means includes an output impedance control means for controlling an output impedance of the output means to a high impedance state, a voltage applying means for applying a voltage to be fed back by the feedback means, and the output And a signal path control means for opening a connection between the output of the means and one end of the feedback means and connecting one end of the feedback means to the voltage applying means.

  In the class D amplifier, the input control means is a switch connected between an input resistance (R11, R12) of the input means and an input section of the differential operational amplifier (101).

  The class D amplifier is configured to generate and output a first pulse signal and a second pulse signal in which the duty ratio complementarily changes in accordance with the signal level of the input signal by pulse width modulation of the input signal. It is characterized by things.

  In the class D amplifier, a signal of a predetermined level is output from one of the first and second output terminals (T21, T22) according to the signal level of the input signal, and the first and second output terminals On the other hand, it is characterized in that the pulse signal subjected to pulse width modulation is output.

  According to the present invention, since the feedback path is opened and the offset voltage correction voltage is applied to one end of the feedback resistor, the offset due to the difference in resistance value between the positive phase side and the negative phase side of the feedback resistor or input resistor is provided. A voltage appears at the output of the differential operational amplifier. Therefore, by adjusting the offset voltage of the differential operational amplifier, a class D that can simultaneously correct the offset voltage caused by the difference in resistance value constituting the class D amplifier and the offset voltage of the differential operational amplifier. An amplifier can be provided.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings (first embodiment).
FIG. 1 shows an example of a class D amplifier according to the first embodiment of the present invention. The class D amplifier shown in FIG. 2 is a pulse signal OUTP, OUTM in which the duty ratio is complementarily changed in accordance with the signal level of the analog input signal AIN by modulating the pulse width of the analog input signal AIN from the external signal source SIG. Is generated and output, and further includes an offset voltage correction circuit in addition to the configuration of the conventional class D amplifier shown in FIG.

  That is, the class D amplifier according to this embodiment shown in FIG. 1 includes input terminals T11 and T12, feedback resistors R41 and R42, an input stage amplifier 100, an integration circuit 110, a pulse width modulation circuit 120, a drive circuit 130, a comparator 140, The control circuit 141, the offset voltage correcting DC voltage source 160, the switches SWOUT1 and SWOUT2, and the output terminals T21 and T22 are connected to the analog input signals AIN (+) having opposite polarities from the signal source SIG. , AIN (−) are input via capacitors Cin1 and Cin2.

  Here, the input stage amplifier 100 (input means) includes a differential operational amplifier 101, input resistors R11 and R12, feedback resistors R21 and R22, and switches SWOS1 and SWOS2 (input control means). One end of the switch SWOS1 is connected to the inverting input portion of the differential operational amplifier 101, and the other end of the switch SWOS1 is connected to one end of the input resistor R11. The other end of the input resistor R11 is connected to the input terminal T11. One end of the switch SWOS2 is connected to the non-inverting input part of the differential operational amplifier 101, and the other end of the switch SWOS2 is connected to one end of the input resistor R12. The other end of the input resistor R12 is connected to the input terminal T12. A feedback resistor R21 is connected between the inverting input unit and the non-inverting output unit of the differential operational amplifier 101, and a feedback resistor R22 is connected between the non-inverting input unit and the inverting output unit. .

The integration circuit 110 (integration means) includes a differential operational amplifier 111 having an offset voltage correction function, capacitors 112 and 113, and input resistors R31 and R32. An input resistor R31 is connected between the inverting input portion of the differential operational amplifier 111 having an offset voltage correction function and the non-inverting output portion of the differential operational amplifier 101, and the offset voltage correction function is provided. An input resistor R32 is connected between the non-inverting input portion of the differential operational amplifier 111 and the inverting output portion of the differential amplifier 101. A capacitor 112 is connected between the inverting input unit and the non-inverting output unit of the differential operational amplifier 111 having an offset voltage correction function, and a capacitor is connected between the non-inverting input unit and the inverting output unit. 113 is connected.
The differential operational amplifier 111 having an offset voltage correction function is a differential operational amplifier capable of offset voltage correction, and can change the correction amount by setting conditions.

  One input section of the pulse width modulation circuit 120 (modulation means) is connected to the non-inverting output section of the differential operational amplifier 111 having the offset voltage correction function, and the other input section has the offset voltage correction function. It is connected to the inverting output part of the differential operational amplifier 111.

The drive circuit 130 (output means) is composed of output buffers 131 and 132. The input part of the output buffer 131 is connected to one output part of the pulse width modulation circuit 120, and the output part of the output buffer 131 is connected to the output terminal T21 and to the terminal B1 of the switch SWOUT1 (signal path control means). Connected. An input terminal of the switch SWOUT1 is connected to an inverting input portion of the differential operational amplifier 111 having the offset voltage correction function via a feedback resistor R41 (feedback means). The input portion of the output buffer 132 is connected to the other output portion of the pulse width modulation circuit 120. The output portion of the output buffer 132 is connected to the output terminal T22 and the terminal of the switch SWOUT2 (signal path control means). Connected to B2. An input terminal of the switch SWOUT2 is connected to a non-inverting input portion of the differential operational amplifier 111 having the offset voltage correction function via a feedback resistor R42 (feedback means).
The output buffers 131 and 132 are provided with output impedance control means that can change the output impedance to a high impedance during offset voltage correction.

The terminals A1 and A2 of the switches SWOUT1 and SWOUT2 are commonly connected to one end of the offset voltage correcting DC voltage source 160 (voltage applying means). The other end of the offset voltage correcting DC voltage source 160 is grounded.
Two input terminals of the comparator 140 are respectively connected to two output terminals of the differential operational amplifier 111 having an offset voltage correction function. The output terminal of the comparator 140 is connected to the input terminal of the control circuit 141, and the output terminal of the control circuit 141 is connected to the control terminal of the differential operational amplifier 111 having an offset voltage correction function.

  Among the components described above, the switches SWOS1, SWOS2, SWOUT1, SWOUT2, the differential operational amplifier 111 having an offset voltage correction function, the offset voltage correction DC voltage source 160, the comparator 140, the control circuit 141, The output voltage control circuit included in the output buffers 131 and 132 constitutes an offset voltage correction circuit.

One output terminal T21 is connected to one end of an inductor L1, and the other end of the inductor L1 is connected to one input terminal of the speaker SP. One end of the inductor L2 is connected to the other output terminal T22, and the other end of the inductor L2 is connected to the other input terminal of the speaker SP. A capacitor C is connected between the other end of the inductor L1 and the other end of the inductor L2. The inductors L1 and L2 and the capacitor C constitute a low-pass filter for removing a carrier frequency component in pulse width modulation from the output signal of the class D amplifier.
In this embodiment, the power supply voltage of the output buffers 131 and 132 is 15 V, and the power supply voltage of the differential operational amplifier 101 and the differential operational amplifier 111 having the offset voltage correction function is 3.3 V.

Next, the operation of the class D amplifier according to this embodiment will be described by classifying it into an amplification operation, an offset voltage generation operation, and an offset voltage correction operation.
(1) Amplification Operation First, the amplification operation (power amplification operation) will be described with reference to the waveform diagram of FIG.
An analog input signal AIN (+) from the signal source SIG is applied to the input terminal T11 shown in FIG. 1, and an analog input signal that is a signal having a polarity opposite to that of the analog input signal AIN (+) is applied to the other input terminal T12. (-) Is applied. These analog input signals AIN (+) and AIN (−) are input to the input stage differential amplifier 100 via capacitors Cin1 and Cin2.
During the amplification operation, the switches SWOS1 and SWOS2 are closed, and the switches SWOUT1 and SWOUT2 are connected to the terminal B1 side and the terminal B2 side, respectively, to form a feedback path.

  The input stage differential amplifier circuit 100 amplifies the difference between the analog signal AIN (+) and the analog input signal AIN (−), and outputs the positive-phase signal (output signal from the non-inverting output unit) SA of the amplified signal. In addition to outputting from the inverting output unit, a reverse phase signal (output signal from the inverting output unit) SB of the amplified signal is output from the inverting output unit. The normal phase signal SA and the negative phase signal SB are input to the integration circuit 110.

  The integrating circuit 110 integrates the difference between the signals SA and SB amplified by the input stage amplifier circuit 100, and outputs a positive-phase signal (output signal from the non-inverting output unit) SC of the difference from the non-inverting output unit. The negative phase signal (output signal from the inverted output unit) SD of the difference is output from the inverted output unit. The normal phase signal SC and the negative phase signal SD are input to the pulse width modulation circuit 120.

  The pulse width modulation circuit 120 compares the positive-phase signal SC and the negative-phase signal SD output from the integration circuit 110 with a triangular wave signal output from a triangular wave generation circuit (not shown) to thereby generate a pulse signal P that has been subjected to pulse width modulation. , M are output. These pulse signals P and M are generated so that the integration result is reflected in the pulse width. The pulse signals P and M are output from the driving circuit 130 as output pulse signals OUTP and OUTM via output terminals T21 and T22, and the output pulse signals OUTP and OUTM are supplied via feedback resistors R41 and R42. Thus, the output waveform distortion is reduced by being fed back to the differential operational amplifier 111 having the offset voltage correction function of the integration circuit 110 and superimposed on the input signal of the integration circuit.

  In the no-signal input state, the difference between the normal phase signal SA and the negative phase signal SB is zero. Therefore, since the difference between the input signal of the inverting input unit and the input signal of the non-inverting input unit of the differential operational amplifier 111 having the offset voltage correction function is zero, the waveform of the normal phase signal SC and the negative phase signal SD are That is, the difference between the normal phase signal SC and the negative phase signal SD becomes zero. In the no-signal input state, the relationship between the triangular wave signal, the positive phase signal SA, and the negative phase signal SB is set so that the duty ratios of the pulse signals P and M and the output pulse signals OUTP and OUTM are 50%. ing.

  Here, the high level period (pulse width) of the pulse signals P and M depends on the signal levels of the positive phase signal SA and the negative phase signal SB, and the signal levels of the positive phase signal SA and the negative phase signal SB are analog inputs. It depends on the signal levels of the signals AIN (+) and AIN (−). Therefore, the pulse widths of the pulse signals P and M depend on the signal levels of the analog input signals AIN (+) and AIN (−), thereby realizing pulse width modulation.

  In the no-signal input state, as shown in FIG. 2A, the duty ratio of the output pulse signal OUTP is 50%, so the average value of the signal level of the output pulse signal OUTP is 7.5V. Further, since the duty ratio of the output pulse signal OUTM is also 50%, the average value thereof is 7.5V. Therefore, in the no-signal input state, 7.5V is applied to both input terminals of the speaker and the difference voltage becomes 0V, so that the speaker SP is not driven and no sound is output.

  When the signal level of the analog input signal AIN (+) increases from the above-described no-signal input state and the signal level of the analog input signal AIN (−) having the opposite polarity decreases, the period of the high level of the output pulse signal OUTP increases. Along with the increase, the low level period of the output pulse signal OUTM increases. That is, the duty ratio of the output pulse signal OUTP increases and the duty ratio of the output pulse signal OUTM decreases.

  In this case, as shown in FIG. 2B, the average value of the output pulse signal OUTP is, for example, 9.5 V, which is higher than 7.5 V at the time of no signal input, while the average value of the output pulse signal OUTM is no signal. For example, 5.5V, which is lower than 7.5V at the time of input. Therefore, the voltage difference between the input terminals of the speaker SP becomes, for example, 4 V (= 9.5 V−5.5 V), and the cone paper of the speaker SP is driven forward, for example.

  On the contrary, when the signal level of the analog input signal AIN (+) decreases and the analog input signal AIN (−) increases from the above-described no-signal input state, as shown in FIG. The duty ratio of the output pulse signal OUTP decreases while the duty ratio of the output pulse signal OUTM increases. Thereby, the difference voltage between the input terminals of the speaker SP becomes, for example, −4 V (= 5.5 V−9.5 V), and the cone paper of the speaker SP is driven backward, for example.

  As described above, in the normal amplification operation, the duty ratios of the output pulse signal OUTP and the output pulse signal OUTM are complementarily controlled according to the signal level of the analog input signal AIN, so that the two terminals of the speaker SP are connected. The speaker SP is driven by generating a differential voltage.

(2) Offset Voltage Generation Operation Next, the offset voltage generation operation will be described. Here, regarding the offset voltage generation operation in the no-signal input state, first, it is assumed that a plurality of offset voltage generation sources exist independently, and finally, all of them are added to obtain the offset voltage of the entire class D amplifier.

First, due to the offset voltage of the differential operational amplifier 101, the average voltage of each of the signals SA and SB is different from a reference voltage (half of the power supply voltage) 1.65V set by the common-mode feedback circuit. Become. This offset voltage is multiplied by the amplification factor (R41 / R31) of the negative feedback amplifier formed by the feedback resistors R41 and R42, the integrator 110, the pulse width modulation circuit 120, and the output buffer 130, and the difference between the output terminals T21 and T22. Appears as a potential (offset voltage).
Further, due to the offset voltage of the differential operational amplifier 111 having the offset voltage correction function, the average voltages of the signals SC and SD are different from the reference voltage 1.65V set by the common-mode feedback circuit. .

Further, the output pulse signals OUTP and OUTM have an offset voltage due to a difference in resistance value between the feedback resistors R41 and R42 or a difference in resistance value between the input resistors R31 and R32. Different values. The reason will be described below.
As shown in FIG. 2A, the output pulse signals OUTP and OUTM at the time of no-signal input are complementarily outputted as rectangular waves with a duty ratio of 50%. Since the power supply voltage of the output buffer 130 is 15V, there is no offset voltage in the differential operational amplifier, and the output pulse signals OUTP and OUTM are ideal under ideal conditions where the resistance values on the positive phase side and the negative phase side are all equal. As described above, the average voltage is 7.5V for both.

  On the other hand, since the average voltage of each of the output signals SA and SB of the differential operational amplifier 101 whose power supply voltage is 3.3 V is common-mode feedback so as to match the reference voltage which is a half of the power supply voltage. 1.65V. Therefore, the voltage difference of 5.85 V between the average value of the output pulse signals OUTP and OUTM and the average value of the output signals SA and SB is the feedback resistor R41, the input resistor R31 of the integrator 110, the feedback resistor R42, and the integrator 110. To the input resistance R32. As a result, a current corresponding to the sum of the resistance values of the feedback resistor R41 and the input resistor R31 is transferred from the output portion of the output buffer 130 to the positive phase output portion of the differential operational amplifier 101 via the feedback resistor R41 and the input resistor R31. Flowing. Similarly, a current corresponding to the sum of the resistance values of the feedback resistor R42 and the input resistor R32 is transferred from the output unit of the output buffer 130 to the negative phase output unit of the differential operational amplifier 101 via the feedback resistor R42 and the input resistor R32. Flowing.

  Here, consider a case where there is a difference between the resistance values of the feedback resistors R41 and R42. The voltages at the two input portions of the differential operational amplifier 111 having the offset voltage correction function are equal because feedback is performed. Therefore, since the voltage applied to both ends of the input resistor R31 is equal to the voltage applied to both ends of the input resistor R32, the currents flowing through the resistors are equal.

  Since the currents having the same values flow through the feedback resistors R41 and R42, respectively, the voltage drop of the feedback resistors R41 and R42 is applied to the output portion of the output buffer 1300 even when the values of the input resistors R31 and R32 are equal. The difference occurs. Accordingly, an offset voltage corresponding to the difference between the resistance values of the feedback resistors R41 and R42 is generated in the output pulse signals OUTP and OUTM.

Similarly, when there is a difference between the resistance values of the input resistors R31 and R32, a current corresponding to the difference between the resistance values flows through the feedback resistors R41 and R42, and an offset voltage caused by the current flows as output pulse signals OUTP and OUTM. Appearing at the output terminals T21 and T22.
That is, if the amplification factor (R41 / R31) on the positive phase side and the amplification factor (R42 / R32) on the negative phase side of the negative feedback amplifier constituting the class D amplifier differ due to variations in resistance values, the output offset Appears as a voltage.

There are offset voltage generation sources other than the three typical offset voltage generation sources described above, but a description thereof is omitted here.
These offset voltages are all combined and appear at the output terminals T21 and T22, and the speaker SP is driven by the offset voltage, which causes a pop sound when the power is turned off or muted.
In the present invention, the offset voltage is corrected by an offset voltage correction operation described below.

(3) Offset voltage correction operation In the present invention, by setting the voltage of the output signal of the output buffer (output means) to the voltage to be fed back by the feedback resistor (feedback means) in the no-signal input state, the difference in resistance value is set. The basic principle is to generate and correct the offset voltage generated at the input of the differential operational amplifier. One embodiment thereof will be described below with reference to FIG.
FIG. 3 is a flowchart showing the offset voltage correction method.
First, a control circuit (not shown) controls their output impedances to a high impedance state by the output impedance control means of the output buffers 131 and 132 (step S1).

  Next, a control circuit (not shown) turns off the switches SWOS1 and SWOS2 connected to the input of the differential operational amplifier 101, cuts off the input signal from the outside, and sets it to the no-signal input state (step S2). Thus, even when an input signal is input to the input terminals T11 and T12, the offset voltage can be corrected in that state.

  Next, a control circuit (not shown) connects the switch SWOUT1 to the terminal A1 side and the switch SWOUT2 to the terminal A2 side to open the feedback path (step S3). As a result, the connection between the output of the output buffer 131 and the feedback resistor R41 and the connection between the output of the output buffer 132 and the feedback resistor R42 are released, and one end of each of the feedback resistors R41 and R42 is common to the DC voltage source 160 for offset voltage correction. Connected.

  By these steps S1 to S3, the feedback path is opened, and the DC voltage from the offset voltage correcting DC voltage source 160 is applied to one end of the feedback resistors R41 and R42. This voltage value is the same voltage as the average value (voltage to be fed back) of the output pulse signals OUTP and OUTM at the time of no signal input in normal operation (7.5 V which is a half of the power supply voltage 15 V in this embodiment). Set to

  Therefore, one end of the feedback resistors R41 and R42 is set to the same bias condition as that at the time of actual no-signal input in which the feedback path is formed, and when there is a difference in the resistance value as described above, As a result, a difference occurs in the value of the current flowing through the resistor, and an offset voltage is generated between the inverting input portion and the non-inverting input portion of the differential operational amplifier 111 having the offset voltage correction function.

  Specifically, since a voltage of 7.5−1.65 = 5.85 [V] is applied to the feedback resistor R41 and the input resistor R31, the negative phase of the differential operational amplifier 111 having an offset voltage correction function. A voltage of 1.65 + 5.85 × R31 / (R31 + R41) [V] is applied to the input section. Similarly, a voltage of 1.65 + 5.85 × R32 / (R32 + R42) [V] is applied to the positive phase input portion of the differential operational amplifier 111 having the offset voltage correction function. As can be seen from both equations, a voltage difference (that is, an offset voltage) corresponding to variations in resistance values of the input resistors R31 and R32 and the feedback resistors R41 and R42 is an input portion of the differential operational amplifier 111 having an offset voltage correction function. Occurs. This amount of offset voltage is equal to the amount of offset voltage generated at the time of no signal input in normal operation in which a feedback path is formed.

In addition, the offset voltage of the differential operational amplifier 101 is generated at the input of the differential operational amplifier 111 having an offset voltage correction function.
Further, the offset voltage of the differential operational amplifier 111 itself provided with the offset voltage correction function is generated at the input section as an input conversion offset voltage.
As a result, the offset voltage due to all the above-mentioned factors appears at the input of the differential operational amplifier 111 having the offset voltage correction function, and the offset voltage is the differential operational amplifier 111 having the offset voltage correction function. Is amplified by an amplification factor of 2 and output to the output signals SC and SD.

Therefore, by performing the offset voltage correction by the differential operational amplifier 111 having the offset voltage correction function, all the above-described offset voltages are corrected simultaneously.
Note that the voltage of the offset voltage correction voltage source 160 is not limited to the above voltage, and may be arbitrarily set.

Next, the control circuit 141 changes the offset voltage correction condition of the differential operational amplifier 111 having the offset voltage correction function (step S4). As a result, the differential operational amplifier 111 having the offset voltage correction function generates an offset voltage having a predetermined voltage determined by the offset voltage correction condition.
Here, when an offset voltage having the opposite polarity and the same magnitude as the offset voltage generated by the class D amplifier is generated by the differential operational amplifier 111 having the offset voltage correction function, the voltage difference between the output signals SC and SD is changed. Therefore, the offset voltage can be optimally corrected by detecting these voltage differences.

Next, the control circuit 141 determines whether or not the signal level of the output signal Comp of the comparator 140 is inverted from the initial state. If the signal level is not inverted, the offset voltage amount and polarity are not appropriate. The return offset voltage correction condition is changed (step S5; No). If the signal level of the output signal Comp of the comparator 140 is inverted, it means that the offset voltage has become sufficiently small under the offset voltage correction condition, and the process proceeds to step S6 (step S5; Yes).
Instead of using the comparator 140, it may be determined whether or not the signal level of one output signal (for example, the signal SC) of the differential operational amplifier 111 having the offset voltage correction function is inverted.

Next, the control circuit 141 stores the offset voltage correction condition in the register (step S6). Using the offset voltage correction condition stored in this register, the offset voltage is corrected during the normal amplification operation.
Next, a control circuit (not shown) turns on the switches SWOS1 and SWOS2 (step S7).

Next, a control circuit (not shown) connects the switch SWOUT1 to the B1 side and the switch SWOUT2 to the B2 side (step S8).
Finally, a control circuit (not shown) cancels the high impedance state of the output impedance of the output buffer and changes it to the normal state (step S9). By these steps S7 to S9, the class D amplifier can perform a normal amplification operation.

  By executing the offset voltage correction method described above, the differential operational amplifier 101 and the offset voltage correction function are provided in addition to the offset voltage caused by the difference in resistance value between the input resistors R31 and R32 and the feedback resistors R41 and R42. Offset voltage correction including the offset voltage of the differential operational amplifier 111 can be performed. That is, by using this configuration, offset voltage correction of the entire class D amplifier can be performed simultaneously by one offset voltage correction operation. Further, since the offset voltage correction can be executed by a single differential operational amplifier having an offset voltage correction function, the circuit configuration is not complicated and the increase in area can be reduced.

Next, an example of the differential operational amplifier 111 having an offset voltage correction function used in the class D amplifier according to this embodiment will be described.
FIG. 4 is a circuit diagram of a differential operational amplifier having an offset voltage correction function.
In the figure, reference numerals 1100 and 1101 denote NMOS transistors constituting a differential transistor pair of the differential operational amplifier having the offset voltage correction function, and 1102 and 1103 denote loads of the differential operational amplifier having the offset voltage correction function. PMOS transistors 1104 and 1105 constituting a transistor pair are PMOS transistors constituting an output stage of a differential operational amplifier having an offset voltage correction function, 1106 and 1107 are common-mode feedback resistors, and 1108 and 1109 are common-mode feedback. NMOS transistors 1110 and 1111 constituting the differential pair of the amplifiers are PMOS transistors constituting the load of the common-mode feedback amplifier.

  Further, 1122 is a bias current source of a differential operational amplifier having an offset voltage correction function, 1123 and 1124 are bias current sources of an output stage of the differential operational amplifier having an offset voltage correction function, and 1125 is an in-phase feedback. Amplifier bias current sources, SWCTR1 and SWCTR2 are switches, 401 to 404 are current source changeover switches, 405 to 408 are current sources, and 409 is a control circuit. A differential operational amplifier having an offset voltage correction function is configured by the components shown in FIG.

  Here, one end of the offset voltage correcting resistor RosA is connected to the source of the PMOS transistor 1102, and the other end is connected to the power supply (VDD). Similarly, one end of the offset voltage correcting resistor RosB is connected to the source of the PMOS transistor 1103, and the other end is connected to the power supply (VDD).

  The switch SWCTR1 has one end connected to a connection point between the resistor RosA and the source of the PMOS transistor 1102, the other end connected to one end of the switch SWCTR2, and a common connection to one end of each of the current source changeover switches 401 to 404. ing. The other end of the switch SWCTR2 is connected to a connection point between the resistor RosB and the source of the PMOS transistor 1103.

The other ends of the current source changeover switches 401 to 404 are respectively connected to one ends of the current sources 405 to 408. The other ends of the current sources 405 to 408 are grounded.
The control circuit 409 is connected to the current source changeover switches 401 to 404. In the illustrated circuit example, the control circuit 409 controls the on and off states of the current source changeover switches 401 to 404 by a 4-bit binary code. The MSB of the binary code controls the current source changeover switch 401, the LSB controls the current source changeover switch 404, and the bits between them control the current source changeover switches 402 and 403 in order.

Next, the offset voltage correction operation by the differential operational amplifier having the offset voltage correction function will be described.
First, the electrical characteristics of the MOS transistors constituting the differential amplifier are in an ideal state in which the offset voltage of the differential amplifier does not result, and the voltage applied to the input terminals AINP and AINN of the differential amplifier is Consider an equal steady state. The current value of the bias current 1122 of the differential amplifier is assumed to be It.

First, when the switches SWCTR1 and SWCTR2 are off, the current value flowing through the resistor RosA becomes It / 2, which is half the current value It of the bias current 1122. Therefore, the voltage drop VRosA caused by the resistor RosA is
VRosA = RosA · It / 2 (1)
It can be expressed.

Next, when only the switch SWCTR1 is closed and the current source changeover switch 404 is closed from the above state, the current from the current source Ipd is added to the constant current It / 2 and flows to the resistor RosA. As a result, the voltage drop VRosA ′ due to the resistor RosA is
VRosA ′ = RosA · Ipd + RosA · It / 2 (2)
It can be expressed.

Accordingly, the change vosA of the voltage drop due to the resistor RosA caused by the added current Ipd is obtained from the difference between the equations (1) and (2).
vosA = RosA · Ipd (3)
It can be expressed.
Therefore, the voltage between the gate and the source of the PMOS transistor 1102 is reduced by the change vosA of this voltage drop, and as a result, the current value flowing through the PMOS 1102 is reduced. The change ios of the current value is expressed by using the mutual conductance of the PMOS 1102 as gmp.
ios = vosA · gmp (4)
It can be expressed.

Therefore, the input equivalent offset voltage vosi of the NMOS transistor 1100 that generates the change ios of the current value represented by the equation (4) is expressed as follows, where the mutual conductance of the NMOS transistor 1100 is gmn.
vosi = ios / gmn (5)
It can be expressed.

Expression (5) is obtained by substituting Expression (4).
vosi = vosA · gmp / gmn (6)
And transformed.
Therefore, by using this circuit, it is possible to obtain the input conversion offset voltage vosi represented by the equation (6). In other words, by adjusting the resistance and current, the input conversion offset voltage vosi can be obtained as the offset voltage correction amount.

Next, an example in which each element value and current value when 50 [μV] is required as the input conversion offset voltage vosi is specifically obtained based on the equation (6) is shown.
In Equation (6), gmp / gmn depends on the amplifier design and is generally a value of around 1. Therefore, assuming that gmp / gmn = 1, from equation (6), vosA = vosi · gmn / gmp = 50 [μV]. Here, since vosA = Ipd · RosA from Equation (3), for example, assuming that Ipd = 1 [μA], then RosA = 50 μ / 1 μ = 50 [Ω].

This means that when the differential amplifier has an input converted offset voltage of 50 [μV], the differential operational amplifier having this offset voltage correction function corrects it by the resistor RosA and the offset voltage correction current. This means that there can be no offset voltage equivalently. Furthermore, the offset voltage correction amount (the magnitude of the input conversion offset voltage) can be freely changed by changing the resistance RosA or the current Ipd.
In the above description, the example in which the offset voltage correction current is generated on the resistor RosA side is shown. However, if the SWCTR1 is turned off and the SWCTR2 is turned on to generate the offset voltage correction current on the resistor RosB side, An input conversion offset voltage having a reverse polarity can be obtained.

In the differential operational amplifier having the offset voltage correction function, the offset voltage io current is obtained by the offset voltage correction current source Ipd and the resistor RosA controlling the source voltage of the PMOS transistor 1102. The voltage between the gate and the source is controlled by the voltage vosA determined by the resistor RosA and the current Ipd. As a result, the offset current ios is determined by ios = vosA · gmp shown in the equation (4).
That is, since the input conversion offset voltage vosi is determined by vosi = vosA · gmp / gmn shown in the equation (6), the sensitivity can be controlled to be lower than that when the offset current ios is directly given by the current source.

  An example of the offset voltage correction current value is as follows. In the differential operational amplifier having the offset voltage correction function, the offset voltage correction current necessary for obtaining the input conversion offset voltage of 50 [μV] is as described above. In the case of the resistance RosA = 50 [Ω], Ipd = 1 [μA], which can be obtained with higher accuracy than the conventional technique. Furthermore, if the resistance RosA = 5 [Ω], the required current is Ipd = 10 [μA], which can be obtained with higher accuracy. That is, the designer can freely determine the combination of the resistor RosA and the offset voltage correction current Ipd so that vosA = 50 [μV], so that the offset voltage correction current can be set freely.

That is, in the differential operational amplifier provided with this offset voltage correction function, an offset voltage correction current larger than that of the prior art can be used in order to obtain an input conversion offset voltage having the same magnitude. Since such a large current value can be obtained with higher accuracy than a small current value, the offset voltage correction amount (input conversion offset voltage) can be controlled with higher accuracy.
In addition, in the differential operational amplifier provided with the offset voltage correction function, it is possible to obtain a small input conversion offset voltage by using an offset voltage correction current larger than that of the conventional technique, so that the minimum resolution of the input conversion offset voltage can be reduced. It becomes possible to make it small, and the offset voltage correction amount of the differential amplifier can be set with high accuracy.

In addition to these, the differential operational amplifier having the offset voltage correction function is less sensitive to the process variation of the input-converted offset voltage, so that the characteristic variation is suppressed and the characteristic is stabilized against the process variation. The reason is that the mutual conductance gm of NMOS and PMOS tends to fluctuate in the same way when process fluctuation occurs, and as understood from Equation (6), their ratio is “gmp / This is because “gmn” is approximately constant, and the fluctuations cancel each other. For example, when the gate oxide film capacitance Cox changes, it is considered that the mutual conductance gm changes in the same direction at the same rate in both PMOS and NMOS. Accordingly, since the value of gmp / gmn does not vary greatly in the equation (6), the input conversion offset voltage vosi corresponding to the offset voltage correction amount does not vary greatly, and the variation is suppressed.
As described above, according to the differential operational amplifier having the offset voltage correction function, the offset voltage correction amount is not easily affected by the environmental change, and the offset voltage of the differential amplifier can be accurately corrected.

Next, the offset voltage value setting operation of the differential operational amplifier having this offset voltage correction function will be described.
This circuit changes the value of the current flowing through the resistors RosA and RosB by switching the current source changeover switches 401 to 404 according to each bit of the 4-bit binary code output from the control circuit 409, so that the optimum input conversion offset Voltage value can be set.

  For example, when the binary code output from the control circuit 409 is 0000, the current source changeover switches 401 to 404 are all off, and when the binary code is 1001, the current source changeover switch 401 is on, 402 and 403 are off, 404 is turned on. The use of a 4-bit binary code is an example, and the present invention is not limited to this example.

  The current sources 405 to 408 are weighted. In this example, the current source 408 has a current value ipd, the current source 407 has a current value 2ipd, the current source 406 has a current value 4ipd, The source 405 has a current value of 8 ipd. By using such a current value, it is possible to set an arbitrary current value in a range from a minimum of 0 to a maximum of 15 ipd with the current value ipd as a minimum unit by sequentially switching the 4-bit binary code.

In addition, when the switch SWCTR1 is on and the SWCTR2 is off, a current flows through the resistor RosA. On the other hand, when the switch SWCTR1 is off and the SWCTR2 is on, a current flows through the resistor RosB. Can do.
The control circuit 409 controls on / off of the current source changeover switches 401 to 404.

Next, a method for correcting the offset voltage using the differential operational amplifier having the offset voltage correction function described above will be described.
FIG. 5 is a flowchart showing an offset voltage correction method.
The offset voltage correction method described below corresponds to steps S4 to S6 in the offset voltage correction method for the class D amplifier described with reference to FIG.

First, the control circuit 409 turns on the switch SWCTR1 and turns off SWCTR2 (step S51).
Next, the control circuit 409 turns on all the current source changeover switches 401 to 404 (step S52). In other words, the binary code is set to 1111 in the circuit example shown in FIG.
Next, the control circuit 409 turns off the current source selector switch by binary code (step S53). For example, when the binary code is 1111, it is set to 1110 and only the current source changeover switch 404 is turned off.

Next, the control circuit 409 is connected to the output signals AOUTP and AOUTN of the differential operational amplifier having the offset voltage correction function, and compares the magnitudes of the output signals Comp of the comparator 140 (described in FIG. 1). It is determined whether the signal level is inverted (step S54). When the signal level of the output signal Comp is inverted, it means that the polarity of the offset voltage is inverted, and this condition becomes an appropriate offset voltage correction condition.
When the signal level of the output signal Comp is inverted (step S54; Yes), the control circuit 409 stores the binary code in the register (step S59) and ends the process. When the signal level of the output signal Comp is not inverted (step S54; No), the process proceeds to step S55.

Next, the control circuit 409 determines whether or not all the current source changeover switches are off (step S55). If all are off (Yes), the process proceeds to step S56. If not all off (No), the process returns to step S53.
Next, the control circuit 409 turns off the switch SWCTR1 and turns on SWCTR2 (step S56). Thereby, an offset voltage of reverse polarity can be added.

Next, the control circuit 409 turns on the current source changeover switch 1 by binary code (step S57). For example, in the case of the 4-bit configuration shown in FIG. 4, when the binary code is 0000, it becomes 0001, and only the current source changeover switch 404 is turned on.
Next, the control circuit 409 determines whether or not the signal level of the output signal Comp of the comparator 140 has been inverted (step S58). When the signal level of the output signal Comp is inverted (step S58; Yes), the control circuit 409 stores the binary code in the register (step S60) and ends the process. When the signal level of the output signal Comp is not inverted (step S58; No), the process proceeds to step S59.
Next, the control circuit 409 determines whether or not all the current source changeover switches are on (step S59). If all are on (Yes), the control circuit 409 stores the binary code in the register (step S60) and ends the process. If all are not on (No), the process returns to step S57.
By using the differential operational amplifier having the offset voltage correction function as described above, the class D amplifier according to this embodiment can be realized.

(Second Embodiment)
In the present embodiment, an example in which the offset voltage is corrected in a class D amplifier having a configuration different from that of the first embodiment will be described. Specifically, an example of a class D amplifier using another circuit as the pulse width modulation circuit 120 is shown.
FIG. 6 is a circuit diagram of a pulse width modulation circuit used in the class D amplifier according to the second embodiment of the present invention.

  A class D amplifier (same as the configuration of the class D amplifier shown in FIG. 1) configured by using the pulse width modulation circuit shown in FIG. 1 corresponds to the signal level of the analog input signal AIN from the external signal source SIG. A signal of a predetermined level is output from one of the two output terminals, and pulse signals OUTP and OUTM obtained by pulse width modulation of the analog input signal by comparing the triangular wave signal and the signal level from the other are output from the other. This is a so-called filterless class D amplifier configured to generate and output.

Next, the configuration of the pulse width modulation circuit used in the class D amplifier according to this embodiment will be described in detail. The pulse width modulation circuit 120 includes a pulse width modulation unit 1200, a triangular wave generation circuit 1400, and a signal conversion unit 1510.
The pulse width modulation unit 1200 includes comparators 121 and 122. Among these, the non-inverting input part of the comparator 121 is connected to the non-inverting output part of the differential operational amplifier 111 having the offset voltage correction function, and the non-inverting input part of the comparator 122 is the difference having the offset voltage correction function. It is connected to the inverting output part of the dynamic operational amplifier 111. Triangular wave signals (triangular wave signals having a constant period and peak value) are commonly input from the triangular wave generation circuit 1400 to the inverting input portions of the comparators 121 and 122.

The signal conversion unit 1510 includes inverters 151A, 151B, 151F, and 151G, a delay unit 151E, and negative AND gates 151C and 151H.
Here, the pulse signal SE is given to the input part of the inverter 151A from the pulse width modulation part 1200, and the output part of the inverter 151A is connected to the input part of the inverter 151B. The output part of the inverter 151B is connected to one input part of the negative AND gate 151C.

  Further, the pulse signal SF is given from the pulse width modulation unit 1200 to the input unit of the delay unit 151E, the output unit of the delay unit 151E is connected to the input unit of the inverter 151F, and the output unit of the inverter 151F is It is connected to the input part of the inverter 151G. The output part of the inverter 151G is connected to one input part of the negative AND gate 151H. The other input part of the negative AND gate 151C is connected to the output part of the inverter 151F, and the other input part of the negative AND gate 151H is connected to the output part of the inverter 151A.

Next, the operation of the class D amplifier according to this embodiment will be described.
(1) No signal input state When the signal level of the analog input signal AIN is 0 V, that is, in the no signal input state, the waveform of the positive phase signal SC and the waveform of the negative phase signal SD match, and the pulse signals SE, The relationship between the triangular wave signal, the positive phase signal SC, and the negative phase signal SD is set so that the duty ratio of SF is 50%.

First, the amplification operation will be described.
Since the operation other than the pulse width modulation circuit is the same as the operation described in the first embodiment, the description thereof is omitted.
The comparators 121 and 122 of the pulse width modulation unit 1200 compare the positive phase signal SC and the negative phase signal SD output from the integration circuit 110 with the triangular wave signal output from the triangular wave generation circuit 1400, thereby performing pulse width modulation. The pulse signals SE and SF thus output are output to the signal converter 1510.

  Here, the high level period (pulse width) of the pulse signals SE and SF depends on the signal levels of the positive phase signal SA and the negative phase signal SB, and the signal levels of the positive phase signal SA and the negative phase signal SB are analog inputs. It depends on the signal levels of the signals AIN (+) and AIN (−). Therefore, the pulse widths of the pulse signals SE and SF depend on the signal levels of the analog input signals AIN (+) and AIN (−), thereby realizing pulse width modulation.

  Next, the operation of the signal conversion unit 1510 will be described. Schematically, the signal converter 1510 converts the pulse signals SE and SF into pulse signals P and M that are complementarily set to a low level (predetermined level) according to the signal level of the analog input signal AIN. The pulse signal SE is applied to one input part of the negative AND gate 151C via the inverters 151A and 151B. The pulse signal SF is delayed by a predetermined time by the delay unit 151E, and then output from the delay unit 151E as the pulse signal Sd. This pulse signal Sd is inverted by the inverter 151F and supplied to the other input portion of the negative AND gate 151C, and also supplied to the other input portion of the negative AND gate 151H via the inverters 151F and 151G. .

  The negative AND gate 151C outputs a low level to the output buffer 131 when the first input condition in which the pulse signal SE is at a high level and the pulse signal Sd is at a low level is satisfied. On the other hand, when the negative AND gate 151H satisfies the second input condition in which the pulse signal SE is at a low level and the pulse signal Sd is at a high level (that is, an input condition complementary to the first input condition). The low level is output to the output buffer 132.

  Here, in the present embodiment, the first input condition is to specify the signal levels of the pulse width modulated pulse signal SE and the pulse signal Sd when the polarity of the signal level of the analog input signal AIN (+) is positive. The second input condition is a specific combination of the signal levels of the pulse signal SE and the pulse signal Sd that are pulse width modulated when the polarity of the signal level of the analog input signal AIN (+) is negative. Is set as

  Thus, by setting the first and second input conditions that are complementary to each other, the pulse signals SE and SF subjected to pulse width modulation are converted into signals P and M that are complementarily fixed at a low level. It is possible to do. However, the present invention is not limited to this example, and any combination of signal levels corresponding to changes in the pulse widths of the pulse signal SE and the pulse signal Sd by pulse width modulation can be arbitrarily set.

  Here, in the no-signal input state, the period in which the first input condition is satisfied is a fixed period from the transition of the pulse signal SE to the high level to the transition of the pulse signal Sd to the high level. Corresponds to the delay time tD in the delay unit 151E. The period in which the second input condition is satisfied is a fixed period from when the pulse signal SE transitions to the low level until the pulse signal Sd transitions to the low level, and this period is also the time at the delay unit 151E. This corresponds to the delay time tD. After all, when no signal is input, the signal conversion unit 1510 converts the pulse signals SC and SD into a pulse signal having a short pulse width (for example, a duty ratio of 10%) corresponding to the delay time tD, and converts this into a cycle of the triangular wave signal. Output intermittently.

  That is, the pulse signal P output from the negative AND gate 151C and the pulse signal M output from the negative AND gate 151H are input to the output buffers 131 and 132, respectively, and are shown in FIG. Inverted as shown and output as output pulse signals OUTP and OUTM to drive the speaker.

(2) Signal Input State Next, when the signal level AIN (+) of the analog input signal is lowered and the signal level AIN (−) of the analog input signal having the opposite polarity is raised, the signal is output from the integrating circuit 110. As the signal level of the positive phase signal SC increases, the signal level of the negative phase signal SD decreases, and the signal level of the positive phase signal SC exceeds the signal level of the negative phase signal SD. Note that the delay time of the delay unit 151E is ignored.

  As a result, the duty ratio of the pulse signal SE increases and the duty ratio of the pulse signal SF decreases. Accordingly, since the second input condition described above is not satisfied, the output pulse signal OUTM is fixed at a low level as shown in FIG. 7B. The pulse width of the output pulse signal OUTP is a pulse width modulated according to the signal level of the analog input signal AIN.

  On the other hand, when the signal level AIN (+) of the analog input signal is increased and the signal level AIN (−) of the analog input signal having the opposite polarity is decreased, the signal level of the positive phase signal SC output from the integrating circuit 110 is decreased. Decreases, the signal level of the negative phase signal SD increases, and the signal level of the negative phase signal SD exceeds the signal level of the positive phase signal SC. Note that the delay time of the delay unit 151E is ignored.

  As a result, the duty ratio of the pulse signal SE output from the pulse width modulation unit 1200 decreases and the duty ratio of the pulse signal SF increases. Therefore, since the first input condition is not satisfied, the output pulse signal OUTP is fixed at a low level as shown in FIG. 7C. The pulse width of the output pulse signal OUTM is a pulse width modulated according to the signal level of the analog input signal AIN.

As described above, in a normal amplification operation, one of the output pulse signals OUTP and OUTM is fixed at a low level according to an analog input signal, and the other includes a pulse width-modulated pulse. When such output pulse signals OUTP and OUTM are supplied to the speaker, a differential voltage is generated between the input terminals of the speaker, and the speaker is driven.
As described above, the class D amplifier according to this embodiment functions as a so-called filterless amplifier that can drive a speaker without using a low-pass filter connected to the output terminals T21 and T22 of the class D amplifier. can do.

Next, the offset voltage generation operation will be described.
Also in the class D amplifier according to the present embodiment, the offset voltage is generated on the same principle as in the first embodiment. The average value of the output pulse signals OUTP and OUTM at the time of no-signal input in this embodiment depends on the pulse width, and is about 1V, for example. On the other hand, since the average voltages of the signals SA and SB are 1.65 V, currents corresponding to the potential difference flow through the input resistors R31 and R32 and the feedback resistors R41 and R42. Therefore, when there is a difference in resistance value between the positive phase side and the negative phase side, an offset voltage is generated at the output.

  Also in this embodiment, the offset voltage correction operation is the same as the operation described in the first embodiment, and is performed according to the flow shown in FIG. As a result, in addition to the offset voltage caused by the difference in resistance between the positive phase side and the negative phase side, the offset voltage of the differential operational amplifier can be corrected simultaneously.

The effects of the first embodiment and the second embodiment are summarized below.
According to the embodiments described so far, the offset voltage generated when there is a difference in resistance between the positive phase side and the negative phase side of the input resistance and the feedback resistance in this type of amplifier is very simple. (Switches SWOS1, SWOS2, SWOUT1, SWOUT2, differential operational amplifier 111 having an offset voltage correction function, output impedance control means provided in output buffers 131, 132, comparator 140, control circuit 141, DC voltage source 160 for offset voltage correction ) Can be effectively corrected just by adding.

Further, in addition to the offset voltage, the offset voltage of the differential operational amplifier can be corrected simultaneously by a single offset voltage correction operation.
Further, since the switches SWOS1 and SWOS2 are turned off, offset voltage correction can be performed even when an input signal is input.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included. For example, the differential operational amplifier having the offset voltage correction function may be a circuit having any configuration, and is not limited to the circuit shown in FIG. The configuration of the class D amplifier may be any configuration. Further, the voltage of the offset voltage correcting DC voltage source is not limited to the average voltage of the output pulse signal when no signal is input, and may be 0 V (ground voltage) or an arbitrary voltage, for example.

1 is a circuit diagram of a class D amplifier according to a first embodiment of the present invention. It is a wave form diagram of a D class amplifier same as the above. It is the flowchart which showed the offset voltage correction method of a D class amplifier same as the above. It is a circuit diagram of the differential operational amplifier provided with the offset voltage correction function used for the D class amplifier same as the above. It is the flowchart which showed the offset voltage correction method of the differential operational amplifier provided with the offset voltage correction function used for a class D amplifier same as the above. It is a circuit diagram of a pulse width modulation circuit used for a class D amplifier according to a second embodiment of the present invention. It is a wave form diagram of a D class amplifier same as the above. It is a circuit diagram of the class D amplifier concerning a prior art.

Explanation of symbols

  R11, R12; input resistors, R21, R22; feedback resistors, SWOUT1, SWOUT2; switch, 100; input stage amplifier circuit, 110; integrating circuit, 120; pulse width modulation circuit, 130; drive circuit, 140; Control circuit, 160; DC voltage source for offset voltage correction, 1200; pulse width modulation unit, 1400; triangular wave generation circuit, 1510; signal conversion unit.

Claims (5)

An input means for inputting an input signal;
An integrating means for integrating an input signal input via the input means, comprising a differential operational amplifier having an offset voltage correction function;
Modulation means for generating a pulse signal in which the integration result of the integration means is subjected to pulse width modulation and the integration result is reflected in the pulse width;
An output means for outputting the pulse signal;
Feedback means for superimposing the output signal of the output means on the input signal and feeding back to the integrating means;
Input control means for setting the input means to a no-signal input state;
A class D amplifier comprising output control means for setting a voltage of an output signal of the output means to a voltage to be fed back by the feedback means in the no-signal input state. The output control means is
Output impedance control means for controlling the output impedance of the output means to a high impedance state;
Voltage application means for applying a voltage to be fed back by the feedback means;
2. The signal path control unit according to claim 1, further comprising: a signal path control unit that opens a connection between the output of the output unit and one end of the feedback unit and connects one end of the feedback unit to the voltage application unit. Class D amplifier. The input control means is
The class D amplifier according to claim 1 or 2, wherein the switch is connected between an input resistance of the input means and an input section of a differential operational amplifier.   The pulse width modulation of the input signal is performed, and first and second pulse signals whose duty ratios change complementarily according to the signal level of the input signal are generated and output. Item 4. The class D amplifier according to any one of Items 1 to 3.   The pulse signal that outputs a signal of a predetermined level from one of the first and second output terminals according to the signal level of the input signal and is pulse-width modulated from the other of the first and second output terminals The class-D amplifier according to claim 1, wherein the class-D amplifier is configured to output a signal.

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